Mask plate for etching rectangular array dot matrix and method for preparing array dot matrix pattern by using mask plate

Abstract

The invention discloses a mask plate for etching a rectangular array dot matrix and a method for preparing an array dot matrix pattern by using the mask plate. The invention provides a mask plate and a method for patterning a rectangular array dot matrix array through dry etching for the first time. The use of a photoresist or a polar solvent and the like is avoided, the containment of an MEMS (Micro Electro Mechanical System) process is improved, and more novel films with excellent performance can be applied to microelectronic devices; the array pattern manufactured by using the layout etching method can be compatible in any MEMS manufacturing factory, alignment marks of the substrate and the mask can be compatible in a first layer circuit wiring process, and the manufacturing cost is saved.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuit manufacturing, and in particular relates to a mask plate for etching a rectangular array dot matrix and a method for preparing an array dot matrix pattern using the mask plate. Background Art

[0002] Calcium etching is an important process in the manufacture of semiconductor devices and integrated circuits, and is an important means of patterning in integrated circuit devices. Usually, the etching process is carried out after the photolithography technology, and the device structure pattern generated by the photolithography is prepared on the underlying substrate through etching. Simply put, the photoresist is first reacted under light source or laser exposure using photolithography technology, and then immersed in a developer to reveal the pattern to be removed; then the etching process is used to remove the part of the pattern that is not blocked by the photoresist, and then the photoresist is removed. Etching includes wet etching and dry etching. Wet etching uses various corrosive solutions to remove the pattern protected by the photoresist by immersion; while dry etching is completed with the help of special etching technology using equipment, including reactive ion beam etching (RIE) technology, inductively coupled plasma etching (ICP) technology and ion beam etching (IBE) technology.

[0003] The above etching scheme is a common strategy in the manufacture of semiconductor devices and integrated circuits. However, with the continuous emergence of high-performance new materials, new challenges are constantly being raised to the MEMS manufacturing process. For example, the physical and chemical properties of new materials are often not suitable for existing MEMS manufacturing (for example, some materials are easily corroded by photoresists or polar solvents), resulting in process incompatibility, thus limiting the use of new materials in microelectronic chips. Another example is halide perovskite materials with suitable band gap, high carrier mobility, high absorption coefficient, low exciton binding energy, and long carrier lifetime, which have attracted global attention in recent years. Their quantum dots, nanowires and other structures have become a new generation of optoelectronic functional materials, and have excellent performance in light-emitting diodes, light sensors, memristors, etc., but they are easily corroded by polar solutions (water, ethanol, acetone, photoresist, etc.); another example is MnBi2Te4 material, which is an antiferromagnetic topological insulator, with strange states such as quantum anomalous Hall insulator, axion insulator, Weyl semimetal, etc., which is not only attractive in basic research, but also has great potential in practical applications, but this functional material is also easily corroded by polar solvents. With the development of science and technology, the number and types of new materials of this type are becoming more and more numerous. In order to avoid contact with solvents of the same polarity, the photolithography scheme and wet etching scheme need to be excluded first, so only the dry etching scheme can be carried out. However, it is necessary to use a mask plate to pattern the material by blocking.

[0004] Usually, the mask plate is hollowed out, the shielded and protected part is the part that needs to be patterned, and the exposed part is the removed part; the characteristic is that the pattern of the non-hollowed part of the mask plate must be coherent, that is, the pattern of the shielded and protected part is coherent; on the contrary, if the pattern of the hollowed part is coherent, and the pattern of the shielded and protected part is incoherent, the mask plate with such a graphic design itself does not exist, such as Figure 1 Therefore, in dry etching, if array-type pattern etching is encountered, it is impossible to directly dry-etch the pattern using a mask. Summary of the invention

[0005] The object of the present invention is to provide a mask plate for etching a rectangular array dot matrix, and at the same time, providing a method for etching a rectangular array dot matrix using the mask plate is the second invention object of the present invention.

[0006] In order to achieve the above-mentioned object of the invention, the present invention adopts the following technical solutions:

[0007] A mask plate for etching a rectangular array dot matrix, wherein the number of array dots of the rectangular array dot matrix is ​​N*M, the dot matrix size is a square of a*b, the column resolution is c, and the row resolution is d; the mask plate comprises a first layer layout, a second layer layout and a third layer layout;

[0008] The first layer of the layout is used to make various alignment marks and lower layer circuits of functional films, including:

[0009] 1) The film and circuit area located in the center of the layout and the blank area located on the periphery of the layout, wherein the blank area is the layout drawing area of ​​other leads and pads of the circuit; the film and circuit area is a rectangle centered on the layout center (0, 0), with a side length of N*c and a width of M*d;

[0010] 2) setting first etching alignment marks at four corners outside the film and circuit area;

[0011] 3) First alignment marks are set at the four corners of the blank area of ​​the first layer layout for alignment between the mask and the substrate;

[0012] The second layer of pattern is used to make a mask plate for etching, including:

[0013] 4) A second hollow area corresponding to the film and circuit area of ​​the first layer layout, and a second mask area corresponding to the blank area of ​​the first layer layout, wherein the second hollow area is an etching mask area, and has a grating stripe structure, wherein each stripe is a rectangle with a length of N*c and a width of b, and there are M stripes in total, and the center of the rectangle formed by the M stripes is the layout center (0, 0);

[0014] 5) second etching alignment marks are set at the four corners of the second hollowed-out area, which are used for position calibration between the mask etching area and the substrate, and are consistent with the first etching alignment marks of the first layer layout;

[0015] 6) The second hollowed-out area is provided with a second alignment mark corresponding to the first alignment mark, for aligning the contact position between the mask plate and the substrate;

[0016] The third layer pattern is used to make a mask plate for etching, including:

[0017] 7) A third hollow area corresponding to the film and circuit area of ​​the first layer layout, and a third mask area corresponding to the blank area of ​​the first layer layout; the third hollow area is an etching mask area, which has a grating stripe structure and is arranged vertically with the grating stripe structure of the etching mask area layout of the second layer layout, wherein each stripe is a rectangle with a length of M*d and a width of a, and there are N stripes in total, and the center of the rectangle formed by the N stripes is the layout center (0, 0);

[0018] 8) third etching alignment marks are set at the four corners of the third hollowed-out area, the third etching alignment marks are used for position calibration between the mask etching area and the substrate, and are consistent with the first etching alignment marks of the first layer layout;

[0019] 9) A third alignment mark is set in the mask area of ​​the third layer layout: it is used to align the contact position between the mask plate and the substrate, and corresponds to the first alignment mark of the first layer layout.

[0020] As a further preferred embodiment of the present invention, the center positions of the first, second and third etching alignment marks are c away from the center position (0, 0) of the layout, where c>(N 2 c 2 +M 2 d 2 ) 1 / 2 / 2, and the hierarchical structure of the first, second and third etching alignment marks ranges from a hundred-micron-level cross to a micron-level cross; the first, second and third alignment marks are in a cross-shaped structure and are designed with multi-level precision, and the size of the cross ranges from a thousand-micron level to a micron level; the first, second and third etching alignment marks and the next level of the first, second and third alignment marks are all set at the blank positions at the four corners of the previous level; the levels of the first, second and third alignment marks are determined according to the accuracy of the etching pattern. If the accuracy of the layout pattern is at the hundred-micron level, the alignment mark cross between the mask plate and the substrate is drawn from a thousand-micron level to ten-micron level. The first-level cross of the layout is at the thousand-micron level (millimeter level), and the position between the mask plate and the substrate can be judged by the naked eye for the first time; the second level is at the hundred-micron level, which can be judged by an optical microscope; the third level is at the ten-micron level; the fourth level is at the several micron level; and so on, according to the increasing level of accuracy, the cross of each level is located at the blank position at the four corners of the previous level and the cross.

[0021] The present invention also discloses a method for etching a rectangular array dot matrix pattern using the mask plate, comprising the following steps:

[0022] S1: First use the first layer layout:

[0023] S11: manufacturing a circuit and various patterned alignment marks in the lower layer of the functional thin film array region on the substrate;

[0024] S12: After the lower layer circuit and the alignment mark are patterned at the array points, a functional film is deposited on the upper layer of the circuit. The functional film is deposited by a thermal evaporation method or a coating method.

[0025] S2: Use the second layer pattern to make a mask plate for etching:

[0026] S21: The material of the mask plate can be a metal thin plate such as stainless steel, or a silicon-based wafer or a ceramic thin film material such as silicon nitride and silicon dioxide. The red area in the layout is the removal area of ​​the mask plate, that is, the hollow area, and the white area is the reserved area, that is, the mask area.

[0027] S22: Alignment of the mask plate and the substrate: When the two are in contact and aligned for the first time, the mask plate and the substrate can be judged by naked eyes according to the thousand-micrometer-level cross-shaped alignment marks at the four corners of the mask plate and the substrate, and the relative position of the mask plate and the substrate is adjusted to make the mask plate and the substrate make the first contact; then, the position of the mask plate and the substrate is continued to be adjusted using the substrate transfer platform, and the alignment between the mask plate and the substrate is roughly adjusted according to the hundred-micrometer-level cross-shaped alignment marks at the four corners of the mask plate and the substrate; the alignment between the mask plate and the substrate is finely adjusted using the substrate transfer platform again according to the ten-micrometer-level and micrometer-level cross-shaped alignment marks at the four corners of the mask plate and the substrate;

[0028] S23: Etching position alignment confirmation: After the positions of the mask plate and the substrate are adjusted, the substrate transfer platform is used to observe whether the alignment marks at the four corners of the functional film and the circuit area are aligned at each level. If not, the positions of the mask plate and the substrate can be further fine-tuned according to the situation;

[0029] S24: After the alignment is completed, the mask plate and the substrate are fixed by using a pressure spring and / or resin glue;

[0030] S25: placing the fixed mask plate and substrate together into an etcher to perform the first etching;

[0031] S3: After the first etching is completed, the mask plate of the second layer of layout pattern is removed; the mask plate of the third layer of layout pattern is used to align the mask plate and the substrate again;

[0032] S4: Repeat S2 to S3, and the array dot matrix pattern etching is completed.

[0033] As a further preferred embodiment of the present invention, in S11, the circuit is a metal layer, and the first layer of the layout is used as a photolithography layout to complete the graphic process: photolithography - development - deposition of conductive metal layer - stripping or deposition of conductive metal layer - photolithography - development - etching; or, the first layer of the layout can be made into a mask plate, which is attached to the surface of the substrate, and the thin film production of the circuit and the alignment mark can be completed by using a physical vapor deposition process.

[0034] Compared with the prior art, the present invention has the following beneficial effects:

[0035] 1. The present invention proposes for the first time a mask plate and method for dry etching a rectangular array dot matrix array dot pattern;

[0036] 2. The present invention avoids the use of photoresist or polar solvents, improves the MEMS process tolerance, and enables more new films with superior performance to be applied in microelectronic devices;

[0037] 3. The array pattern produced by the layout etching method of the present invention can be compatible with any MEMS manufacturing factory, and the alignment marks of the substrate and the mask can be compatible with the first-layer circuit wiring process, saving manufacturing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solution of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without paying creative work.

[0039] Figure 1 It is a schematic diagram for explaining the situation that the existing mask plate cannot etch the array pattern;

[0040] Figure 2 It is a rectangular dot matrix pattern completed by the present invention;

[0041] Figure 3 It is the first level layout design plan and instructions;

[0042] Figure 4 It is the second-level layout design plan and instructions;

[0043] Figure 5 It is the third-level layout design plan and instructions;

[0044] Figure 6 It is a schematic diagram of the process of etching a rectangular array dot matrix of the present invention. DETAILED DESCRIPTION

[0045] In order to make the purpose, technical scheme and advantages of the present invention clearer, the technical scheme of the present invention is described in detail below, but the following embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other implementation methods obtained by those skilled in the art without making creative work belong to the scope of protection of the present invention.

[0046] Example 1

[0047] This embodiment provides a mask plate for etching a rectangular array dot matrix, wherein the rectangular array dot matrix is ​​as follows: Figure 2 The number of array points shown is N*M, the dot size is a*b square, the column resolution (the distance from the center of adjacent dots in the vertical direction) is c, and the row resolution (the distance from the center of adjacent dots in the horizontal direction) is d;

[0048] The mask plate includes a first layer layout, a second layer layout and a third layer layout:

[0049] The first layer of the layout is used to make various alignment marks and lower layer circuits of functional films, such as Figure 3 As shown, including:

[0050] 1) The film and circuit area located in the center of the layout ( Figure 3 The purple area in the middle, Figure 3 The upper left figure shows the blank area on the periphery of the layout, which is the layout drawing area for other leads and pads of the circuit; the film and circuit area (purple area) is a rectangle centered on the center of the layout (0, 0), with a side length of N*c (N is the number of rectangular dot arrays, c is the resolution of the rectangular dot array), and a width of M*d (M is the number of rectangular dot array rows, d is the resolution of the rectangular dot array rows). The circuit layout design of the lower layer of the film and the circuit leads outside the film layer (purple area) are formulated according to the dot matrix and device structure of the film. This layout does not provide a specific design solution. This layout is only used to draw the functional film and the circuit area (purple area) of the lower layer of the film;

[0051] 2) The first etching alignment mark 1 is set at the four corners outside the film and circuit area (purple area), and the center position of the first etching alignment mark 1 is c from the center position of the layout (the center of the purple area) (0, 0), where c>(N 2 c 2 +M 2 d 2 ) 1 / 2 / 2. The first etching marks the hierarchical structure from a hundred-micrometer-level cross to a micrometer-level cross;

[0052] 3) The first alignment marks 2 are set at the four corners of the blank area of ​​the first layer of the layout ( Figure 3Right), used for alignment between the mask plate and the substrate, the alignment mark is a cross-shaped structure, and has a multi-level precision design, and the size of the cross ranges from kilomicrons to microns;

[0053] The second layer of pattern (mask) is used to make a mask for etching, such as Figure 4 As shown, including:

[0054] 4) A second hollow area 3 corresponding to the film and circuit area of ​​the first layer layout, and a second mask area 4 corresponding to the blank area of ​​the first layer layout, such as Figure 4 The red area shown is a hollow area, and the white area is a mask area; the second hollow area 3 is an etching mask area, which has a grating stripe structure as shown in FIG. Figure 4 As shown on the left, each stripe is N*c long (N is the number of matrix columns, c is the matrix column resolution), and is a rectangle with a width of b (array point width). There are M stripes in total, and the center of the rectangle formed by the M stripes is the center of the layout (0, 0);

[0055] 5) The second etching alignment marks 5 of the etching array are arranged at the four corners of the etching mask area. Figure 4 As shown in the middle and lower part, it is used for position calibration between the etching area of ​​the mask plate and the substrate, and is consistent with the first etching alignment mark 1 of the first layer layout;

[0056] 6) The second hollow area 3 is provided with a second alignment mark 6 corresponding to the first alignment mark 2 ( Figure 4 As shown on the right), it is used to align the contact position between the mask plate and the substrate;

[0057] The third layer of the pattern (mask plate) is used to make a mask plate for etching, such as Figure 5 As shown, including:

[0058] 7) A third hollow region 7 corresponding to the film and circuit region of the first layer layout, and a third mask region 8 corresponding to the blank region of the first layer layout, such as Figure 5 As shown in the upper middle, the red area is the hollow area, and the white area is the mask area; the third hollow area 7 is the etching mask area, which has a grating stripe structure (such as Figure 5 As shown on the left, and is arranged perpendicularly to the grid stripe structure of the second-layer layout etching mask area layout, wherein each stripe is M*d in length (M is the number of matrix rows, which is the matrix row resolution), and is a rectangle with a width of a (the length of the array point), with a total of N stripes, and the center of the rectangle formed by the N stripes is the layout center (0, 0);

[0059] 8) The third etching alignment marks 9 of the etching array are arranged at the four corners of the third hollow area 7. Figure 5 As shown in the middle and lower part, the third etching alignment mark 9 is used for position calibration between the etching area of ​​the mask and the substrate, and is consistent with the first etching alignment mark 1 of the first layer layout;

[0060] 9) The third alignment marks 10 are set at the four corners of the mask area of ​​the third layer layout ( Figure 5 Right): The third alignment mark 10 is used to align the contact position between the mask plate and the substrate, corresponding to the first alignment mark 2 of the first layer layout.

[0061] In this embodiment, the center positions of the first, second, and third etching alignment marks are located at a distance c from the center position (0, 0) of the layout, where c>(N 2 c 2 +M 2 d 2 ) 1 / 2 / 2, and the hierarchical structure of the first, second and third etching alignment marks ranges from a hundred-micron-level cross to a micron-level cross; the first, second and third alignment marks are in a cross-shaped structure and are designed with multi-level precision, with the size of the cross ranging from a thousand-micron level to a micron level; the first, second and third etching alignment marks and the next level of the first, second and third alignment marks are all set in the blank positions at the four corners of the previous level.

[0062] The first, second and third alignment mark levels are set according to the accuracy of the etching pattern. If the layout pattern accuracy is at the level of 100 microns, the alignment mark cross between the mask and the substrate is drawn from 1000 microns to 10 microns. The first level of the cross in the layout is at the level of 1000 microns (millimeter level), and the position between the mask and the substrate can be judged by naked eyes for the first time; the second level is at the level of 100 microns, which can be judged by an optical microscope; the third level is at the level of 10 microns; the fourth level is at the level of several microns; and so on, according to the increasing level of accuracy, each level of cross is located at the blank position of the previous level and the four corners of the cross;

[0063] When using the first, second and third four-corner alignment marks: first place the mask plate on the substrate surface, and judge the position by naked eyes according to the first-level thousand-micron cross shape; secondly, use the substrate transfer table to coarsely adjust the position between the mask plate and the substrate according to the second-level hundred-micron cross shape, and then use the substrate transfer table to fine-tune the position of the mask plate and the substrate according to the third-level ten-micron and fourth-level several-micron cross structures.

[0064] Example 2

[0065] This embodiment provides a method for etching a square array dot pattern using a mask plate of the present invention, comprising the following steps:

[0066] S1: First use the first layer layout:

[0067] S11: Make the circuit of the lower layer of the functional thin film array area on the substrate, and each patterned alignment mark is also made in this step. Generally, the circuit is a metal layer, and its patterned alignment mark production process is not restricted by photoresist or polar solvent corrosion. Therefore, the MEMS general process can be used to use the first layer of the layout as the photolithography layout to complete the patterning process: photolithography - development - deposition of conductive metal layer - peeling or deposition of conductive metal layer - photolithography - development - etching (wet / dry etching); or, the first layer of the layout can be made into a mask plate, attached to the surface of the substrate, and the thin film production of the circuit and alignment mark can be completed using a physical vapor deposition process (electron beam evaporation coating process, thermal evaporation coating process, magnetron sputtering coating process);

[0068] S11: After the lower circuit and alignment mark of the array point are patterned, a functional film is deposited on the upper layer of the circuit. The deposition method of the functional film can be made by a thermal evaporation method, a coating method, etc., which is specifically set according to the specific functional film production situation, and will not be described in detail here;

[0069] S2: Use the second layer pattern to make a mask plate for etching:

[0070] S21: The mask plate can be made of metal thin plates such as stainless steel, or silicon-based wafers or ceramic thin film materials such as silicon nitride and silicon dioxide. The red area in the layout is the removed area (hollow area) of the mask plate, and the white area is the retained area (mask area);

[0071] S22: Alignment of the mask plate and the substrate: When the two are in contact and aligned for the first time, the mask plate and the substrate can be judged by naked eyes according to the thousand-micrometer-level cross-shaped alignment marks at the four corners of the mask plate and the substrate, and the relative position of the mask plate and the substrate is adjusted to make the mask plate and the substrate make the first contact; then, the position of the mask plate and the substrate is continued to be adjusted using the substrate transfer platform, and the alignment between the mask plate and the substrate is roughly adjusted according to the hundred-micrometer-level cross-shaped alignment marks at the four corners of the mask plate and the substrate; the alignment between the mask plate and the substrate is finely adjusted using the substrate transfer platform again according to the ten-micrometer-level and micrometer-level cross-shaped alignment marks at the four corners of the mask plate and the substrate;

[0072] S23: Etching position alignment confirmation: After the positions of the mask plate and the substrate are adjusted, the substrate transfer platform is used to observe whether the alignment marks at the four corners of the functional film and the circuit area are aligned at each level. If not, the positions of the mask plate and the substrate can be further fine-tuned according to the situation;

[0073] S24: After the alignment is completed, the mask plate and the substrate are fixed by using a pressure spring and / or resin glue; wherein the resin glue plays a buffering role to prevent vibration dislocation between the mask plate and the substrate; the pressure spring plays a fixing role to prevent a large degree of dislocation from occurring during the process of transferring the mask plate and the substrate to the etcher;

[0074] S25: placing the fixed mask plate and substrate together into the etcher for the first etching; the specific equipment, etching parameters and other details used in the etching process are related to the physical and chemical properties of the etched film, and the process links need to be adjusted according to the specific situation, which will not be explained in detail in this description;

[0075] S3: After the first etching is completed, the mask plate of the second layer of layout pattern is removed; the mask plate of the third layer of layout pattern is used to align the mask plate and the substrate again;

[0076] S4: Repeat S2 to S3, and the etching of the square array dot square array pattern is completed.

[0077] The above process can be seen in Figure 6 shown.

[0078] The above embodiments are preferred implementation modes of the present invention, but the implementation modes of the present invention are not limited to the above embodiments. Any other changes, modifications, substitutions, combinations, and simplifications that do not deviate from the spirit and principles of the present invention should be equivalent replacement methods and are included in the protection scope of the present invention.

Claims

1. A mask plate for etching a rectangular array dot matrix, characterized in that: The number of array points of the rectangular array dot matrix is ​​N*M, the dot matrix size is a*b square, the column resolution is c, and the row resolution is d; the mask plate includes a first layer layout, a second layer layout and a third layer layout; The first layer of the layout is used to make various alignment marks and lower layer circuits of functional films, including: 1) The film and circuit area located in the center of the layout and the blank area located on the periphery of the layout, wherein the blank area is the layout drawing area of ​​other leads and pads of the circuit; the film and circuit area is a rectangle centered on the layout center (0, 0), with a side length of N*c and a width of M*d; 2) setting first etching alignment marks at four corners outside the film and circuit area; 3) First alignment marks are set at the four corners of the blank area of ​​the first layer layout for alignment between the mask and the substrate; The second layer of pattern is used to make a mask plate for etching, including: 4) A second hollow area corresponding to the film and circuit area of ​​the first layer layout, and a second mask area corresponding to the blank area of ​​the first layer layout, wherein the second hollow area is an etching mask area, and has a grating stripe structure, wherein each stripe is a rectangle with a length of N*c and a width of b, and there are M stripes in total, and the center of the rectangle formed by the M stripes is the layout center (0, 0); 5) second etching alignment marks are set at the four corners of the second hollowed-out area, which are used for position calibration between the mask etching area and the substrate, and are consistent with the first etching alignment marks of the first layer layout; 6) The second hollowed-out area is provided with a second alignment mark corresponding to the first alignment mark, for aligning the contact position between the mask plate and the substrate; The third layer pattern is used to make a mask plate for etching, including: 7) A third hollow area corresponding to the film and circuit area of ​​the first layer layout, and a third mask area corresponding to the blank area of ​​the first layer layout; the third hollow area is an etching mask area, which has a grating stripe structure and is arranged vertically with the grating stripe structure of the etching mask area layout of the second layer layout, wherein each stripe is a rectangle with a length of M*d and a width of a, and there are N stripes in total, and the center of the rectangle formed by the N stripes is the layout center (0, 0); 8) third etching alignment marks are set at the four corners of the third hollowed-out area, the third etching alignment marks are used for position calibration between the mask etching area and the substrate, and are consistent with the first etching alignment marks of the first layer layout; 9) A third alignment mark is set in the mask area of ​​the third layer layout: it is used to align the contact position between the mask plate and the substrate, and corresponds to the first alignment mark of the first layer layout.

2. The mask plate for etching a rectangular array dot matrix according to claim 1, characterized in that: The center positions of the first, second, and third etching alignment marks are c away from the center position (0, 0) of the layout, where c>(N 2 c 2 +M 2 d 2 ) 1 / 2 / 2, and the hierarchical structure of the first, second and third etching alignment marks ranges from a hundred-micron-level cross to a micron-level cross; the first, second and third alignment marks are in a cross-shaped structure and are designed with multi-level precision, with the size of the cross ranging from a thousand-micron level to a micron level; the first, second and third etching alignment marks and the next level of the first, second and third alignment marks are all set in the blank positions at the four corners of the previous level.

3. A method for etching a rectangular array dot matrix pattern using the mask plate of claim 1 or 2, characterized in that: The following steps are involved: S1: First use the first layer layout: S11: manufacturing a circuit and various patterned alignment marks in the lower layer of the functional thin film array region on the substrate; S11: After the lower layer circuit and the alignment mark are patterned at the array point, a functional film is deposited on the upper layer of the circuit. The deposition method of the functional film is thermal evaporation or coating method. S2: Use the second layer pattern to make a mask plate for etching: S21: The material of the mask plate can be a metal thin plate such as stainless steel, or a silicon-based wafer or a ceramic thin film material such as silicon nitride and silicon dioxide. The red area in the layout is the removal area of ​​the mask plate, that is, the hollow area, and the white area is the reserved area, that is, the mask area. S22: Alignment of the mask plate and the substrate: When the two are in contact and aligned for the first time, the mask plate and the substrate can be judged by naked eyes according to the thousand-micrometer-level cross-shaped alignment marks at the four corners of the mask plate and the substrate, and the relative position of the mask plate and the substrate is adjusted to make the mask plate and the substrate make the first contact; then, the position of the mask plate and the substrate is continued to be adjusted using the substrate transfer platform, and the alignment between the mask plate and the substrate is roughly adjusted according to the hundred-micrometer-level cross-shaped alignment marks at the four corners of the mask plate and the substrate; the alignment between the mask plate and the substrate is finely adjusted using the substrate transfer platform again according to the ten-micrometer-level and micrometer-level cross-shaped alignment marks at the four corners of the mask plate and the substrate; S23: Etching position alignment confirmation: After the positions of the mask plate and the substrate are adjusted, the substrate transfer platform is used to observe whether the alignment marks at the four corners of the functional film and the circuit area are aligned at each level. If not, the positions of the mask plate and the substrate can be further fine-tuned according to the situation; S24: After the alignment is completed, the mask plate and the substrate are fixed by using a pressure spring and / or resin glue; S25: placing the fixed mask plate and substrate together into an etcher to perform the first etching; S3: After the first etching is completed, the mask plate of the second layer of layout pattern is removed; the mask plate of the third layer of layout pattern is used to align the mask plate and the substrate again; S4: Repeat S2 to S3, and the array dot matrix pattern etching is completed.

4. The method for etching a rectangular array dot matrix pattern according to claim 2, characterized in that: In S11, the circuit is a metal layer, and the first layer of the layout is used as a photolithography layout to complete the graphic process: photolithography - development - deposition of conductive metal layer - stripping or deposition of conductive metal layer - photolithography - development - etching; or, the first layer of the layout can be made into a mask plate, attached to the surface of the substrate, and the thin film production of the circuit and the alignment mark can be completed by using a physical vapor deposition process.

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