Instruction dispatching method and device, processor, computing equipment and program product

Abstract

The invention provides an instruction dispatching method and device, a processor, computing equipment and a program product, and the method comprises the steps: dividing a transmitting queue into a plurality of transmitting queue clusters according to the type of an operation instruction to be dispatched; polling and distributing the to-be-dispatched operation instructions to operation instruction registers corresponding to the transmitting queue clusters respectively; and executing the following operation on each transmitting queue cluster: assigning the operation instruction in the operation instruction register corresponding to the transmitting queue cluster to each transmitting queue in the transmitting queue cluster in a polling manner. According to the method, the instruction dispatching logic can be simplified, the instruction dispatching efficiency is improved, and therefore the frequency and performance of the processor can be improved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to an instruction dispatching method, apparatus, processor, computing device and program product. Background Art

[0002] In processors that use instruction pipeline technology, in order to improve processor performance, the number of supported execution units is increasing, and the pipeline width is also increasing. At this time, when dispatching pipeline instructions to the emission queue, in order to ensure that the instructions are dispatched to each emission queue more evenly, it is necessary to consider how many instructions each emission queue has already dispatched, and then compete with other queues to win all the competitions. In this way, the later dispatch channels will superimpose the logic dispatched in the front, resulting in a long logic level, which cannot meet the timing requirements of instruction dispatch, and then cause the processor frequency to decrease. Summary of the invention

[0003] Based on the above technical problems, the present application proposes an instruction dispatching method, apparatus, processor, computing device and program product, which can simplify the instruction dispatching logic and improve the instruction dispatching efficiency, thereby helping to improve the processor frequency and performance.

[0004] In a first aspect, the present application provides an instruction dispatching method, which is applied to a processor using pipeline technology, wherein the processor includes an operation instruction register for storing operation instructions assigned to an emission queue cluster, and the method includes:

[0005] According to the type of the operation instruction to be dispatched, the transmission queue is divided into a plurality of transmission queue clusters;

[0006] Polling and distributing the operation instructions to be dispatched to the operation instruction registers corresponding to each of the transmission queue clusters;

[0007] The following operations are performed for each of the transmit queue clusters: the operation instructions in the operation instruction register corresponding to the transmit queue cluster are polled and dispatched to each transmit queue in the transmit queue cluster.

[0008] In some implementations, the operation instructions to be dispatched include operation instructions that can only be transmitted through a specific transmission queue and operation instructions that can be transmitted through any transmission queue;

[0009] According to the type of operation instructions to be dispatched, the transmission queue is divided into multiple transmission queue clusters, including:

[0010] According to the operation instructions to be dispatched that can only be transmitted through a specific transmission queue, the transmission queue is divided into transmission queue clusters to obtain a plurality of transmission queue clusters;

[0011] Among them, the transmission queues in a transmission queue cluster are used to transmit the same type of operation instructions.

[0012] In some implementations, the operation instructions to be dispatched include operation instructions that can be transmitted only through a specific transmission queue, and operation instructions that can be transmitted through any transmission queue;

[0013] The method of polling and distributing the operation instructions to be dispatched to the operation instruction registers corresponding to the transmission queue clusters comprises:

[0014] Allocating, among the operation instructions to be dispatched, an operation instruction that can only be transmitted through a specific transmission queue to an operation instruction register corresponding to a transmission queue cluster used for transmitting operation instructions of a type corresponding to the operation instruction;

[0015] The operation instructions to be dispatched that can be transmitted through any transmission queue are polled and allocated to the operation instruction registers corresponding to each of the transmission queue clusters.

[0016] In some implementations, polling and allocating the operation instructions that can be transmitted through any transmission queue among the operation instructions to be dispatched to the operation instruction registers corresponding to each of the transmission queue clusters includes:

[0017] According to the number of allocated operation instructions in the operation instruction registers corresponding to each of the transmitting queue clusters, and in accordance with the set instruction allocation rules, the operation instructions to be dispatched that can be transmitted through any transmitting queue are polled and allocated to the operation instruction registers corresponding to each of the transmitting queue clusters.

[0018] In some implementations, the set instruction allocation rules include: a rule that balances the number of operation instructions allocated to each transmission queue cluster, or a rule that the difference between the number of operation instructions allocated to a first transmission queue cluster and the number of operation instructions allocated to a second transmission queue cluster is a first value.

[0019] In some implementations, the operation instruction register corresponding to the transmit queue cluster includes operation instructions that can only be transmitted through a specific transmit queue and operation instructions that can be transmitted through any transmit queue;

[0020] The operation instructions in the operation instruction register corresponding to the transmission queue cluster are polled and dispatched to each transmission queue in the transmission queue cluster, including:

[0021] According to the type of operation instructions in the operation instruction register corresponding to the transmission queue cluster and the rule of balancing the number of operation instructions assigned to each transmission queue, the operation instructions in the operation instruction register corresponding to the transmission queue cluster are polled and dispatched to each transmission queue in the transmission queue cluster.

[0022] In some implementations, according to the type of the operation instruction in the operation instruction register corresponding to the transmit queue cluster and the rule of balancing the number of operation instructions assigned to each transmit queue, the operation instruction in the operation instruction register corresponding to the transmit queue cluster is polled and dispatched to each transmit queue in the transmit queue cluster, including:

[0023] According to the type of the operation instruction in the operation instruction register corresponding to the transmission queue cluster, the operation instruction in the operation instruction register that can only be transmitted through a specific transmission queue is dispatched to a specific transmission queue in the transmission queue cluster;

[0024] According to the number of operation instructions dispatched to each transmit queue and the rule of balancing the number of operation instructions dispatched to each transmit queue, the operation instructions in the operation instruction register that can be transmitted by any transmit queue are polled and dispatched to each transmit queue in the transmit queue cluster.

[0025] In a second aspect, the present application provides an instruction dispatching device, which is applied to a processor using pipeline technology, wherein the processor includes an operation instruction register for storing operation instructions assigned to an emission queue cluster, and the device includes:

[0026] A queue division unit, used for dividing the transmission queue into a plurality of transmission queue clusters according to the type of the operation instruction to be dispatched;

[0027] A first dispatching unit, configured to poll and distribute the operation instructions to be dispatched to the operation instruction registers corresponding to the respective transmission queue clusters;

[0028] The second dispatching unit is used to perform the following operations on each of the transmit queue clusters: dispatching the operation instructions in the operation instruction register corresponding to the transmit queue cluster to each transmit queue in the transmit queue cluster in a polling manner.

[0029] A third aspect of the present application provides a processor, which is configured to implement the above-mentioned instruction dispatching method.

[0030] A fourth aspect of the present application provides a computing device, comprising the above-mentioned processor.

[0031] A fifth aspect of the present application proposes a computer program product, comprising computer program instructions, which, when executed by a processor, cause the processor to execute the above-mentioned instruction dispatching method.

[0032] The instruction dispatching method proposed in the present application divides the transmission queue into multiple transmission queue clusters according to the type of operation instructions to be dispatched; the operation instructions to be dispatched are polled and assigned to the operation instruction registers corresponding to each of the transmission queue clusters; then, the following operations are performed on each of the transmission queue clusters: the operation instructions in the operation instruction register corresponding to the transmission queue cluster are polled and dispatched to each transmission queue in the transmission queue cluster. The above scheme divides the instruction dispatching into two stages for execution. In the first stage, the transmission queues are clustered first, and the operation instructions are assigned to the operation instruction registers corresponding to each of the transmission queue clusters. In the second stage, each transmission queue cluster executes the internal operation instruction to the transmission queue. In this way, the operation instruction dispatching is divided into two stages, which can reduce the complexity of instruction dispatching. Since each transmission queue cluster only dispatches instructions for a few internal transmission queues, the dispatching logic can be simplified. Multiple transmission queue clusters perform instruction dispatching in parallel, which can improve the efficiency of instruction dispatching. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0034] Figure 1 A schematic diagram of the processor pipeline operation process provided in an embodiment of the present application.

[0035] Figure 2 A schematic diagram of the hardware structure of a processing pipeline provided in an embodiment of the present application.

[0036] Figure 3 A schematic diagram of the hardware structure of another processor pipeline provided in an embodiment of the present application.

[0037] Figure 4 A flowchart of an instruction dispatching method provided in an embodiment of the present application.

[0038] Figure 5 A schematic diagram of the structure of an instruction dispatching device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0039] A superscalar out-of-order processor is a modern high-performance microprocessor that uses pipeline technology to fetch multiple instructions in each clock cycle and execute multiple instructions out of order in parallel internally. This feature improves the CPU's instruction throughput and speeds up program execution.

[0040] During the operation of the processor pipeline, it will go through the stages of instruction fetch, decoding, register renaming, issue, execution, write back, and commit.

[0041] In the instruction fetching stage, in addition to fetching instructions from the I-Cache, the address of the instruction for the next cycle must also be determined. The result of the branch instruction can only be obtained in the execution stage, so it is necessary to predict the behavior of the branch instruction, including the jump direction and jump address.

[0042] The task of the instruction decoding stage is to extract the information carried in the instruction, which will be used by the subsequent stages of the processor to continue execution.

[0043] Next, in a superscalar out-of-order processor, the instructions will enter the register renaming stage. During the execution of the processor, there is a certain correlation between instructions. The so-called correlation means that the execution of one instruction depends on the execution result of another instruction. The execution order between instructions cannot be changed, which restricts the selection range of the instruction issuance stage. In a processor that uses out-of-order execution, register renaming solves the dependency between instructions by mapping logical registers (registers represented in instructions) to physical registers (registers involved in operations in the processor) through a mapping table. Instructions that do not have dependencies can be executed simultaneously.

[0044] In the emission phase, instructions that meet certain conditions are selected from the emission queue and sent to the execution unit for execution.

[0045] During the execute phase, the instructions are executed in the execution units.

[0046] In the write-back phase, the result of the execution unit calculation is written to the physical register file, and the calculation result is sent to the required place through the bypass network, awakening the instructions that depend on the calculation result of this instruction

[0047] In the submission phase, the program's instruction stream enters the processor sequentially, is executed out of order, and is submitted in the order in which the instructions enter the ROB (Reorder Buffer), which ensures the correctness of program execution.

[0048] Figure 1 It shows the processing process of each instruction in each clock cycle during the operation of the processor pipeline.

[0049] Among them, one clock cycle corresponds to one stage of the processor pipeline mentioned above, or is called one beat of the processor pipeline. Figure 1As shown, in each beat, multiple instructions can be processed differently at the same time. For example, in the first beat, instruction 1 is fetched; in the second beat, instruction 1 is decoded and instruction 2 is fetched; in the third beat, the register of instruction 1 is renamed, instruction 2 is decoded, and instruction 3 is fetched, and so on.

[0050] For an instruction, in the above instruction pipeline, each beat completes one stage of processing, that is, each of the stages of instruction fetch, decode, register rename, issue, execute, write back, and commit is completed in one beat.

[0051] During the operation of the processor pipeline described above, each beat needs to be written to the register after execution, that is, the processing result of the current beat is written to the register, and the processing result of the current beat is read from the register when the next beat is executed.

[0052] Figure 2 The hardware schematic diagram of the three-stage pipeline is shown. The three pipeline stages A, B, and C are connected in series in sequence, and each stage contains its own processing logic and registers. After the processing logic of stage A is completed, the processing result is stored in the register of stage A, and then the processing logic of stage B reads the processing result of stage A from the register of stage A and performs the processing of stage B, and then stores the processing result of stage B in the register of stage B. After that, the processing logic of stage C reads the processing result of stage B from the register of stage B and performs the processing of stage C, and then stores the processing result of stage C in the register of stage C.

[0053] In the above pipeline process, after being decoded and renamed, the predicted instructions need to be dispatched to the issue queue for issuance, so that the instructions are issued to the execution unit for execution.

[0054] In order to improve processor performance, the number of execution units supported by the processor is increasing, and the pipeline width is also increasing. At this time, when dispatching pipeline instructions to the emission queue, in order to ensure that the instructions are dispatched to each emission queue more evenly, it is necessary to consider how many instructions each emission queue has already dispatched, and then compete with other queues to win all of them in order to compete successfully. In this way, the later dispatch channel will superimpose the logic of the previous dispatch, resulting in a long logic level. The traditional instruction dispatch algorithm completes instruction dispatch within one beat, that is, after completing register renaming, the instruction dispatch to the emission queue is completed within the beat of instruction issuance, and the emission queue sends the instructions in the queue to the execution unit. When the instruction dispatch logic level is very long, it will lead to the failure to meet the timing requirements of instruction dispatch, which will lead to a decrease in processor frequency.

[0055] In response to the above technical problems, the present application proposes a new instruction dispatching scheme, which divides instruction dispatching into two-beat execution and simplifies the dispatching logic, thereby reducing the overall algorithm complexity of instruction dispatching, improving the efficiency of instruction dispatching, making instruction dispatch meet timing requirements, and helping to improve processor frequency and performance.

[0056] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0057] First, the embodiment of the present application improves the hardware structure of the processor pipeline, specifically, the hardware structure of the transmit stage is improved to a two-level register structure. Figure 3 As shown, in a processor pipeline including fetch, decode, register rename, issue, execute, write back, and commit, the pipeline structure of the issue stage is divided into two sub-stages, and the two sub-stages correspond to the first-level registers respectively, so that the instruction dispatch operation originally completed in one shot can be divided into two shots for execution. The execution result of the first shot is stored in the register corresponding to the first sub-stage of the issue stage. When the second shot is running, the execution result of the first shot is read from the register corresponding to the first sub-stage and then the second shot is processed, and the processing result is stored in the register corresponding to the second sub-stage.

[0058] Among them, the registers corresponding to the second sub-stage can use the original registers of the emission stage, while the registers corresponding to the first sub-stage are one or more registers newly added on the basis of the original registers of the emission stage. In an embodiment of the present application, the registers of the first sub-stage are used as operation instruction registers to store the pre-allocation results of the renamed operation instructions. The above-mentioned pre-allocation results include the pre-allocation results of allocating the operation instructions to the emission queue or the emission queue cluster.

[0059] The first beat processing may be pre-dispatching the renamed instructions to the issue queue, while the second beat processing is to dispatch the instructions to each issue queue based on the pre-dispatching result of the first beat. The issue queue sends the instructions to the execution unit when it determines that the instructions in the queue meet certain conditions.

[0060] In addition, in the embodiment of the present application, there is a certain coupling relationship between the emission queue in the pipeline and the subsequent execution unit. That is to say, for a emission queue, it only emits the instructions in the queue to the execution unit with which it has a coupling relationship. Based on the above coupling relationship, after the instruction is assigned to the emission queue, the emission queue does not need to find which execution unit to emit the instruction in the queue from the numerous execution units. As long as the execution unit coupled with the emission queue is in an idle state, the emission queue can emit the instruction in the queue to the idle execution unit coupled with it. It can be understood that the coupling relationship between the above emission queue and the execution unit makes it possible to regard the instruction as being assigned to the specific execution unit as long as the instruction is assigned to the emission queue. After receiving the assigned operation instruction, the emission queue only needs to emit the instruction to the execution unit coupled with it when confirming that the operation instruction in the queue meets certain conditions. Therefore, the instruction emission efficiency after the instruction is assigned to the reflection queue can be improved.

[0061] Based on the above processor pipeline hardware improvement, the present application embodiment first proposes an instruction dispatching method, see Figure 4 As shown, the method includes:

[0062] S101. Divide a transmission queue into a plurality of transmission queue clusters according to the type of the operation instruction to be dispatched.

[0063] The above-mentioned operation instruction to be dispatched refers to the operation instruction to be dispatched to the emission queue after being decoded and renamed in the instruction pipeline. In the embodiment of the present application, the above-mentioned operation instruction to be dispatched refers to the macro operation (Macro operation, Mop) instruction obtained after being decoded and renamed.

[0064] The types of operation instructions to be dispatched can be divided according to the type of operation, such as write operation instructions and read operation instructions; in addition, they can also be divided according to the requirements of the instructions for the transmission queue, such as operation instructions that can only be transmitted through a specific transmission queue and operation instructions that can be transmitted through any transmission queue.

[0065] The embodiment of the present application divides the transmission queue into transmission queue clusters according to the types of each operation instruction to be dispatched.

[0066] Exemplarily, each operation instruction to be dispatched can be classified first, and all the operation instructions to be dispatched can be divided into multiple operation instruction classes, each operation instruction class contains at least one operation instruction, and the types of the operation instructions contained are the same. Then, corresponding to each operation instruction class, a transmission queue suitable for transmitting the operation instructions in the operation instruction class is selected from the transmission queue, and these transmission queues are grouped into a transmission queue cluster. In the above manner, the transmission queue cluster corresponding to each operation instruction class can be determined.

[0067] For example, suppose that the operation instructions to be dispatched are divided into two types of operation instructions: write operation instructions and read operation instructions. For the write operation instruction type, the emission queue for emitting write operation instructions is selected from the emission queues, and the selected emission queues for emitting write operation instructions are formed into an emission queue cluster; for the read operation instruction type, the emission queue for emitting read operation instructions is selected from the emission queues, and the selected emission queues for emitting read operation instructions are formed into an emission queue cluster.

[0068] In another embodiment, it is also disclosed that the operation instructions to be dispatched are classified according to whether they must be transmitted through a specific transmission queue, that is, the operation instructions to be dispatched are divided into operation instructions that can only be transmitted through a specific transmission queue and operation instructions that can be transmitted through any transmission queue.

[0069] The operation instruction that can only be transmitted through a specific transmission queue refers to an operation instruction that can only be transmitted through a specific type of transmission queue, or can only be transmitted through a certain transmission queue.

[0070] It can be understood that the above-mentioned operation instructions that can only be transmitted through a specific transmission queue have stricter requirements on the transmission queue. If they are assigned to an incompatible transmission queue, they may not be transmitted or a transmission error may occur. However, the operation instructions that can be transmitted through any transmission queue have more lenient requirements on the transmission queue and can be successfully transmitted if they are assigned to any transmission queue.

[0071] In an embodiment of the present application, according to the operation instructions to be dispatched that can only be transmitted through a specific transmission queue, the transmission queue is divided into transmission queue clusters to obtain multiple transmission queue clusters; wherein the transmission queues in a transmission queue cluster are used to transmit the same type of operation instructions.

[0072] Specifically, the operation instructions to be dispatched that can only be transmitted through specific transmission queues are first classified. Specifically, based on the requirements of the operation instructions for the transmission queues, the operation queues that are transmitted through the same type of transmission queues are classified into the same category, so as to determine which types of transmission queues are required to transmit the operation instructions to be dispatched, and then the transmission queues used to transmit the same type of operation instructions are divided into the same transmission queue cluster.

[0073] For example, it is assumed that the operation instructions to be dispatched include operation instructions that can only be transmitted through the transmission queue of type A, operation instructions that can only be transmitted through the transmission queue of type B, and operation instructions that can only be transmitted through the transmission queue of type C. Accordingly, all the transmission queues of type A can be grouped into one transmission queue cluster, all the transmission queues of type B can be grouped into one transmission queue cluster, and all the transmission queues of type C can be grouped into one transmission queue cluster.

[0074] The above-mentioned division of the transmit queue clusters can facilitate the subsequent allocation of the transmit queues to be dispatched to the corresponding transmit queue clusters, and then execute the instruction dispatch within the cluster.

[0075] S102, polling and distributing the operation instructions to be dispatched to the operation instruction registers corresponding to each of the transmission queue clusters.

[0076] Specifically, the operation instruction register corresponding to the transmission queue cluster is a register for storing operation instructions assigned to the transmission queue cluster. That is, in the operation instruction register corresponding to a transmission queue cluster, operation instructions that need to be dispatched and transmitted through the transmission queue cluster are stored.

[0077] The above operation instruction register is Figure 3 The registers of the first sub-stage of the issue stage are shown as registers allocated for the issue queue cluster.

[0078] Among them, the operation instruction register corresponding to each transmission queue cluster can be that each transmission queue cluster corresponds to the same operation instruction register, and each transmission queue cluster occupies different storage areas in the operation instruction register, so as to distinguish the transmission queue cluster corresponding to the operation instruction stored in the operation instruction register through different storage areas. After the transmission queue is divided into multiple transmission queue clusters through step S101, a storage area can be divided for each transmission queue cluster from the register of the first sub-stage of the transmission stage.

[0079] Alternatively, each transmit queue cluster may correspond to one operation instruction register. After the transmit queue is divided into multiple transmit queue clusters in step S101, one operation instruction register may be allocated to each transmit queue cluster from multiple registers in the first sub-phase of the transmit phase.

[0080] After the transmit queues on the processor pipeline are divided into a plurality of transmit queue clusters in step S101, the allocation of the operation instructions to be dispatched to each transmit queue cluster can be performed in step S102.

[0081] Exemplarily, the operation instruction to be dispatched may be assigned to the operation instruction register corresponding to the transmission queue cluster matching its type based on the type of the operation instruction to be dispatched. For example, the read operation instruction to be dispatched is assigned to the operation instruction register corresponding to the transmission queue cluster for transmitting the read operation instruction, and the write operation instruction to be dispatched is assigned to the operation instruction register corresponding to the transmission queue cluster for transmitting the write operation instruction.

[0082] In another embodiment, it is disclosed that, when the operation instructions to be dispatched are divided into operation instructions that can only be transmitted through a specific transmission queue and operation instructions that can be transmitted through any transmission queue, when the operation instructions to be dispatched are polled and assigned to the operation instruction registers corresponding to each transmission queue cluster, the operation instructions that can only be transmitted through a specific transmission queue among the operation instructions to be dispatched are first assigned to the operation instruction register corresponding to the transmission queue cluster used to transmit the operation instructions of the corresponding type of the operation instruction. For example, assuming that a certain operation instruction can only be transmitted through the transmission queue in the A transmission queue cluster, the operation instruction is assigned to the operation instruction register corresponding to the A transmission queue cluster, and assuming that a certain operation instruction can only be transmitted through the transmission queue in the B transmission queue cluster, the operation instruction is assigned to the operation instruction register corresponding to the B transmission queue cluster.

[0083] Then, for the operation instructions to be dispatched that can be transmitted through any transmission queue, they are polled and allocated to the operation instruction registers corresponding to the transmission queue clusters with remaining allocation ports.

[0084] Among them, polling and allocating the operation instructions to the operation instruction registers corresponding to the transmission queue clusters refers to allocating the operation instructions to the operation instruction registers corresponding to the transmission queue clusters in turn.

[0085] Table 1 shows the requirements of several different macro-operation instructions Mop on the issue queue, and the allocation of each macro-operation queue to the operation instruction register corresponding to each issue queue cluster cluster.

[0086] Table 1

[0087]

[0088] In another embodiment, it is disclosed that when the operation instructions to be dispatched that can be transmitted through any transmission queue are polled and allocated to the operation instruction registers corresponding to each transmission queue cluster, according to the number of operation instructions allocated in the operation instruction registers corresponding to each transmission queue cluster and in accordance with the set instruction allocation rules, the operation instructions to be dispatched that can be transmitted through any transmission queue are polled and allocated to the operation instruction registers corresponding to each transmission queue cluster.

[0089] Specifically, the number of operation instructions allocated in the operation instruction register corresponding to each transmission queue cluster refers to the number of operation instructions already in the operation instruction register corresponding to each transmission queue cluster after the operation instructions to be dispatched that can only be transmitted through a specific transmission queue are allocated to the operation instruction register corresponding to the transmission queue cluster used to transmit the operation instruction of the corresponding type of the operation instruction. For example, after the Mop that can only be transmitted through the transmission queue in the A transmission queue cluster is allocated to the operation instruction register corresponding to the A transmission queue cluster, and the Mop that can only be transmitted through the transmission queue in the B transmission queue cluster is allocated to the operation instruction register corresponding to the B transmission queue cluster, the number of operation instructions in the operation instruction register corresponding to the A transmission queue cluster is the number of Mops that can only be transmitted through the transmission queue in the A transmission queue cluster (A_only_num), and the number of operation instructions in the operation instruction register corresponding to the B transmission queue cluster is the number of Mops that can only be transmitted through the transmission queue in the B transmission queue cluster (B_only_num).

[0090] In the embodiment of the present application, after allocating the operation instructions to be dispatched that can only be transmitted through a specific transmission queue to the operation instruction register corresponding to the transmission queue cluster used to transmit the operation instruction of the corresponding type of the operation instruction, based on the number of operation instructions allocated in the operation instruction register corresponding to each transmission queue cluster and in accordance with the set instruction allocation rules, the operation instructions to be dispatched (Any type operation instructions) that can be transmitted through any transmission queue among the operation instructions to be dispatched are polled and allocated to the operation instruction register corresponding to each of the transmission queue clusters.

[0091] In some embodiments, the above-mentioned set instruction allocation rule may be a rule that balances the number of operation instructions allocated to each transmit queue cluster.

[0092] Under this instruction allocation rule, the operation instructions to be dispatched that can be transmitted through any transmission queue are evenly polled and distributed to the operation instruction registers corresponding to each transmission queue cluster, so that the number of operation instructions in the operation instruction registers corresponding to each transmission queue cluster is balanced.

[0093] Exemplarily, when the operation instructions to be dispatched that can be transmitted through any transmission queue (Any type Mop) are polled and allocated to the operation instruction registers corresponding to each transmission queue cluster, the polling allocation rules for Any type Mop can be determined based on the number of operation instructions allocated in the operation instruction registers corresponding to each transmission queue cluster, and the transmission queue cluster allocated by the last Mop in the previous shot.

[0094] Table 2 shows the polling allocation rules of the operation instructions that can be transmitted by any transmission queue to the A transmission queue cluster and the B transmission queue cluster.

[0095] Table 2

[0096]

[0097] In Table 2, A_only_num-B_only_num represents the difference between the number A_only_num of allocated operation instructions in the operation instruction register corresponding to the A transmit queue cluster and the number B_only_num of allocated operation instructions in the operation instruction register corresponding to the B transmit queue cluster.

[0098] As shown in Table 2, when A_only_num-B_only_num is equal to 0, it means that the number of operation instructions allocated in the operation instruction register corresponding to the A transmission queue cluster is equal to the number of operation instructions allocated in the operation instruction register corresponding to the B transmission queue cluster. At this time, the number of operation instructions allocated to the two is balanced. Subsequently, based on the transmission queue cluster allocated by the last Mop in the previous shot, Mops can be allocated alternately to the operation instruction registers corresponding to the two transmission queue clusters.

[0099] When A_only_num-B_only_num is equal to 1, it means that the number of operation instructions allocated in the operation instruction register corresponding to the A transmission queue cluster is 1 more than the number of operation instructions allocated in the operation instruction register corresponding to the B transmission queue cluster. At this time, the number of operation instructions allocated to the two is unbalanced. Subsequently, based on the transmission queue cluster allocated by the last Mop in the previous shot, one more Mop can be allocated to the transmission queue cluster with fewer allocated operation instructions, so that the number of operation instructions allocated by the two is balanced, and then Mops are allocated alternately to the operation instruction registers corresponding to the two transmission queue clusters.

[0100] When A_only_num-B_only_num is equal to 2, it means that the number of operation instructions allocated in the operation instruction register corresponding to the A transmission queue cluster is 2 more than the number of operation instructions allocated in the operation instruction register corresponding to the B transmission queue cluster. At this time, the number of operation instructions allocated to the two is unbalanced. Subsequently, based on the transmission queue cluster allocated by the last Mop in the previous shot, 2 more Mops can be allocated to the transmission queue cluster with fewer allocated operation instructions, so that the number of operation instructions allocated by the two is balanced, and then Mops are allocated alternately to the operation instruction registers corresponding to the two transmission queue clusters.

[0101] When A_only_num-B_only_num is greater than or equal to 3, it means that the number of operation instructions allocated in the operation instruction register corresponding to the A transmission queue cluster is at least 3 more than the number of operation instructions allocated in the operation instruction register corresponding to the B transmission queue cluster. At this time, the number of operation instructions allocated to the two is unbalanced. At this time, due to the large difference in the number of operation instructions allocated by the two, no matter which cluster the last Mop of the previous beat is allocated to, multiple Mops are continuously allocated to the transmission queue cluster with a smaller number of allocated operation instructions, so that the difference in the number of operation instructions allocated by the two is reduced, until the number of operation instructions allocated by the two is balanced, and then Mops are alternately allocated to the operation instruction registers corresponding to the two transmission queue clusters.

[0102] The above-mentioned operation instruction allocation method can balance the number of operation instructions allocated to each transmission queue cluster, which is beneficial to improving the instruction dispatching efficiency.

[0103] In other embodiments, the above-mentioned set instruction allocation rule can also be a rule that the difference between the number of operation instructions allocated to the first emission queue cluster and the number of operation instructions allocated to the second emission queue cluster is a first value, that is, the difference A_only_num-B_only_num between the number of operation instructions A_only_num allocated in the operation instruction register corresponding to the A emission queue cluster and the number of operation instructions B_only_num allocated in the operation instruction register corresponding to the B emission queue cluster is maintained at a specific value. For example, A_only_num-B_only_num=4, or B_only_num-A_only_num=4.

[0104] In this instruction allocation rule, it is necessary to consider the number of operation instructions allocated to the operation instruction registers corresponding to each transmission queue cluster, that is, the number of only type operation instructions (operation instructions that can only be transmitted through a specific transmission queue) that have been allocated to the operation instruction registers corresponding to each transmission queue cluster.

[0105] For example, when allocating operation instructions to each transmit queue cluster in rounds, the difference between the number of operation instructions allocated to the first transmit queue cluster and the number of operation instructions allocated to the second transmit queue cluster can be set to a first value, and then the operation instructions are allocated to the operation instruction registers corresponding to the first transmit queue cluster and the second transmit queue cluster in turn.

[0106] Table 3 shows the instruction allocation rule for polling allocation of operation instructions that can be transmitted by any transmission queue to the A transmission queue cluster and the B transmission queue cluster, under the rule that the difference between the number A_only_num of operation instructions allocated to the operation instruction register corresponding to the A transmission queue cluster and the number B_only_num of operation instructions allocated to the B transmission queue cluster is A_only_num-B_only_num=4.

[0107] Table 3

[0108] A_only_num B_only_num Round Robin Allocation Rules for Any Type Mop 0 A->A->A->A->B->B 1 A->A->A->B->B 2 A->A->B->B 3 A->B->B >＝4 B->B >＝2 A->A->A->A

[0109] In Table 3, A_only_num represents the number of operation instructions A_only_num allocated to the operation instruction register corresponding to the A transmission queue cluster, that is, the number of operation instructions that can only be transmitted through the transmission queue in the A transmission queue cluster; B_only_num represents the number of operation instructions B_only_num allocated to the operation instruction register corresponding to the B transmission queue cluster, that is, the number of operation instructions that can only be transmitted through the transmission queue in the B transmission queue cluster.

[0110] Based on A_only_num and B_only_num, when Any type Mop polling is assigned to the operation instruction registers corresponding to the A transmit queue cluster and the B transmit queue cluster, first assign Any type Mop to the operation instruction registers corresponding to the A transmit queue cluster or the B transmit queue cluster, so that A_only_num-B_only_num=4, and then assign Any type Mop to the operation instruction registers corresponding to the A transmit queue cluster and the B transmit queue cluster in turn.

[0111] Table 4 shows the instruction allocation rule for polling allocation of operation instructions that can be transmitted by any transmission queue to the A transmission queue cluster and the B transmission queue cluster, under the rule that the difference between the number B_only_num of operation instructions allocated to the operation instruction register corresponding to the B transmission queue cluster and the number A_only_num of operation instructions allocated to the A transmission queue cluster is B_only_num-A_only_num=4.

[0112] Table 4

[0113] A_only_num B_only_num Round Robin Allocation Rules for Any Type Mop 0 B->B->B->B->A->A 1 B->B->B->A->A 2 B->B->A->A 3 B->A->A >＝4 A->A >＝2 B->B->B->B

[0114] In Table 4, A_only_num represents the number of operation instructions A_only_num allocated to the operation instruction register corresponding to the A transmission queue cluster, that is, the number of operation instructions that can only be transmitted through the transmission queue in the A transmission queue cluster; B_only_num represents the number of operation instructions B_only_num allocated to the operation instruction register corresponding to the B transmission queue cluster, that is, the number of operation instructions that can only be transmitted through the transmission queue in the B transmission queue cluster.

[0115] Based on A_only_num and B_only_num, when Any type Mop is polled and assigned to the operation instruction registers corresponding to the A transmit queue cluster and the B transmit queue cluster, first assign Any type Mop to the operation instruction registers corresponding to the A transmit queue cluster or the B transmit queue cluster, so that B_only_num-A_only_num=4, and then assign Any type Mop to the operation instruction registers corresponding to the A transmit queue cluster and the B transmit queue cluster in turn.

[0116] The above instruction polling allocation method can allocate the operation instructions to be dispatched to the operation instruction registers corresponding to each transmission queue cluster according to the set instruction allocation rules, thereby realizing the pre-dispatch of the operation instructions to be dispatched. The above pre-dispatch operation can reduce the number of operation instructions that need to be dispatched for each transmission queue cluster, thereby improving the overall efficiency of instruction dispatch.

[0117] S103, performing the following operations on each of the transmit queue clusters: polling and dispatching the operation instructions in the operation instruction register corresponding to the transmit queue cluster to each transmit queue in the transmit queue cluster.

[0118] Specifically, after the operation instructions to be dispatched are allocated to the operation instruction registers corresponding to each transmission queue cluster through the processing of step S102, the operation instructions can be dispatched to the transmission queues in the cluster within each transmission queue cluster.

[0119] In the embodiment of the present application, each transmit queue cluster executes an operation instruction dispatching operation within the cluster, and each transmit queue cluster executes the operation instruction dispatching operation within the cluster in parallel.

[0120] For any transmission queue cluster, the operation instructions in the operation instruction register corresponding to the transmission queue cluster are polled and dispatched to each transmission queue of the transmission queue cluster. For example, one operation instruction is dispatched to each transmission queue in the transmission queue cluster in turn until all the operation instructions in the operation instruction register are dispatched.

[0121] Through the above-mentioned operation instruction dispatching operation, each transmit queue cluster can dispatch the operation instructions to be dispatched to the corresponding transmit queue in parallel.

[0122] In some embodiments, the operation instructions in the operation instruction register corresponding to the transmit queue cluster include operation instructions that can only be transmitted through a specific transmit queue and operation instructions that can be transmitted through any transmit queue.

[0123] In this case, when each transmission queue cluster performs instruction dispatching, the operation instructions in the operation instruction register corresponding to the transmission queue cluster are polled and dispatched to each transmission queue in the transmission queue cluster according to the type of operation instructions in the operation instruction register corresponding to the transmission queue cluster and the rule of balancing the number of operation instructions dispatched to each transmission queue.

[0124] That is, in each transmission queue cluster, when the operation instruction in the operation instruction register corresponding to the transmission queue cluster is dispatched to each transmission queue in the cluster, the operation instruction is dispatched to each transmission queue in round-robin fashion according to the principle of balancing the number of operation instructions dispatched to each transmission queue in the cluster. For example, dispatching one operation instruction to each transmission queue in the cluster in turn can balance the number of operation instructions dispatched to each transmission queue.

[0125] In another embodiment, it is disclosed that when each transmission queue cluster executes operation instruction dispatch within the cluster, the operation instruction in the operation instruction register corresponding to the transmission queue cluster is first dispatched to a specific transmission queue in the transmission queue cluster according to the type of operation instruction in the operation instruction register.

[0126] That is, when dispatching operation instructions within the transmission queue cluster, the type of operation instructions in the operation instruction register corresponding to the transmission queue cluster is first parsed to determine whether there is an operation instruction that can only be transmitted through a specific transmission queue in the transmission queue cluster. If there is, the operation instruction is dispatched to the specific transmission queue corresponding to it; if not, the processing of subsequent steps is continued.

[0127] Then, according to the number of operation instructions dispatched to each transmit queue and the rule of balancing the number of operation instructions dispatched to each transmit queue, the operation instructions in the operation instruction register that can be transmitted by any transmit queue are polled and dispatched to each transmit queue in the transmit queue cluster.

[0128] Specifically, after completing the dispatch of operation instructions that can only be transmitted through a specific transmission queue, some transmission queues in the transmission queue cluster may have dispatched one or more operation instructions, resulting in an imbalance in the number of operation instructions dispatched by each transmission queue in the cluster.

[0129] On this basis, when dispatching operation instructions that can be transmitted through any transmission queue, operation instructions are dispatched to the transmission queue with a smaller number of dispatched operation instructions according to the number of operation instructions already dispatched to each transmission queue, until the number of operation instructions dispatched to each transmission queue in the cluster is balanced, and then operation instructions are dispatched to each transmission queue in turn, for example, one operation instruction is dispatched to each transmission queue in turn, so that the number of operation instructions dispatched to each transmission queue is finally balanced.

[0130] Table 5 shows the instruction dispatching rules when dispatching operation instructions to the issue queues A_0 and A_1 in the A issue queue cluster.

[0131] Table 5

[0132]

[0133] Among them, A_0_only_num represents the number of operation instructions that can only be transmitted through the A_0 transmission queue. In the embodiment of the present application, A_0_only_num represents the number of operation instructions in the operation instruction register corresponding to the A transmission queue cluster that can only be transmitted through a specific transmission queue.

[0134] It can be seen from Table 5 that when there are no operation instructions that can only be transmitted through a specific transmission queue in the operation instruction register corresponding to the A transmission queue cluster, operation instructions are dispatched to A_0 and A_1 in turn, so that the number of operation instructions dispatched to A_0 and A_1 is balanced.

[0135] When there are operation instructions that can only be transmitted through a specific transmission queue in the operation instruction register corresponding to the A transmission queue cluster, for example, A_0_only_num is not 0, the operation instructions that can only be transmitted through the A_0 transmission queue are first dispatched to A_0, and then, when dispatching any type Mop (operation instructions that can be transmitted through any transmission queue), A_0_only_num any type Mops are first dispatched to the A_1 queue, and then the operation instructions are dispatched to A_0 and A_1 in turn, so that the number of operation instructions dispatched to A_0 and A_1 is balanced.

[0136] Table 6 shows the instruction dispatching rules when dispatching operation instructions to the issue queues B_0 and B_1 in the B issue queue cluster.

[0137] Table 6

[0138]

[0139] Among them, B_0_only_num represents the number of operation instructions that can only be transmitted through the B_0 transmission queue. In the embodiment of the present application, B_0_only_num represents the number of operation instructions in the operation instruction register corresponding to the B transmission queue cluster that can only be transmitted through a specific transmission queue.

[0140] It can be seen from Table 6 that when there are no operation instructions that can only be transmitted through a specific transmission queue in the operation instruction register corresponding to the B transmission queue cluster, operation instructions are dispatched to B_0 and B_1 in turn, so that the number of operation instructions dispatched to B_0 and B_1 is balanced.

[0141] When there are operation instructions that can only be transmitted through a specific transmission queue in the operation instruction register corresponding to the B transmission queue cluster, for example, B_0_only_num is not 0, the operation instructions that can only be transmitted through the B_0 transmission queue are first dispatched to B_0, and then, when dispatching any type Mop (operation instructions that can be transmitted through any transmission queue), B_0_only_num any type Mops are first dispatched to the B_1 queue, and then the operation instructions are dispatched to B_0 and B_1 in turn, so that the number of operation instructions dispatched to B_0 and B_1 is balanced.

[0142] It can be seen from the above introduction that the instruction dispatching method proposed in the embodiment of the present application divides the transmission queue into multiple transmission queue clusters according to the type of operation instructions to be dispatched; the operation instructions to be dispatched are polled and assigned to the operation instruction registers corresponding to each of the transmission queue clusters; then, the following operations are performed on each of the transmission queue clusters in parallel: the operation instructions in the operation instruction register corresponding to the transmission queue cluster are polled and dispatched to each transmission queue in the transmission queue cluster. The above scheme divides the instruction dispatch into two stages for execution. In the first stage, the transmission queues are clustered first, and the operation instructions are assigned to the operation instruction registers corresponding to each transmission queue cluster. In the second stage, each transmission queue cluster executes the operation instructions in the cluster to the transmission queue. In this way, the operation instruction dispatching is divided into two stages, which can reduce the complexity of instruction dispatching. Since each transmission queue cluster only dispatches instructions for a few internal transmission queues, the dispatching logic can be simplified. Multiple transmission queue clusters perform instruction dispatching in parallel, which can improve the efficiency of instruction dispatching.

[0143] Corresponding to the above-mentioned instruction dispatching method, the embodiment of the present application further provides an instruction dispatching device, which is applied to a processor using pipeline technology, wherein the processor includes an operation instruction register for storing operation instructions assigned to the transmission queue cluster, see Figure 5 As shown, the device comprises:

[0144] The queue division unit 100 is used to divide the transmission queue into a plurality of transmission queue clusters according to the type of the operation instruction to be dispatched;

[0145] A first dispatching unit 110 is used to poll and distribute the operation instructions to be dispatched to the operation instruction registers corresponding to each of the transmission queue clusters;

[0146] The second dispatching unit 120 is used to perform the following operations on each of the transmit queue clusters: dispatching the operation instructions in the operation instruction register corresponding to the transmit queue cluster to each transmit queue in the transmit queue cluster in a polling manner.

[0147] In some implementations, the operation instructions to be dispatched include operation instructions that can only be transmitted through a specific transmission queue and operation instructions that can be transmitted through any transmission queue;

[0148] The queue division unit 100 divides the transmission queue into a plurality of transmission queue clusters according to the type of the operation instruction to be dispatched, including:

[0149] According to the operation instructions to be dispatched that can only be transmitted through a specific transmission queue, the transmission queue is divided into transmission queue clusters to obtain a plurality of transmission queue clusters;

[0150] Among them, the transmission queues in a transmission queue cluster are used to transmit the same type of operation instructions.

[0151] In some implementations, the operation instructions to be dispatched include operation instructions that can be transmitted only through a specific transmission queue, and operation instructions that can be transmitted through any transmission queue;

[0152] The first dispatching unit 110 polls and distributes the operation instructions to be dispatched to the operation instruction registers corresponding to each of the transmission queue clusters, including:

[0153] Allocating, among the operation instructions to be dispatched, an operation instruction that can only be transmitted through a specific transmission queue to a transmission queue cluster used for transmitting operation instructions of a type corresponding to the operation instruction;

[0154] The operation instructions to be dispatched that can be transmitted through any transmission queue are polled and allocated to the operation instruction registers corresponding to each of the transmission queue clusters.

[0155] In some implementations, the first dispatching unit 110 polls and distributes the operation instructions that can be transmitted through any transmission queue among the operation instructions to be dispatched to the operation instruction registers corresponding to each of the transmission queue clusters, including:

[0156] According to the number of allocated operation instructions in the operation instruction registers corresponding to each of the transmitting queue clusters, and in accordance with the set instruction allocation rules, the operation instructions to be dispatched that can be transmitted through any transmitting queue are polled and allocated to the operation instruction registers corresponding to each of the transmitting queue clusters.

[0157] In some implementations, the set instruction allocation rules include: a rule that balances the number of operation instructions allocated to each transmission queue cluster, or a rule that the difference between the number of operation instructions allocated to a first transmission queue cluster and the number of operation instructions allocated to a second transmission queue cluster is a first value.

[0158] In some implementations, the operation instruction register corresponding to the transmit queue cluster includes operation instructions that can only be transmitted through a specific transmit queue and operation instructions that can be transmitted through any transmit queue;

[0159] The operation instructions in the operation instruction register corresponding to the transmission queue cluster are polled and dispatched to each transmission queue in the transmission queue cluster, including:

[0160] According to the type of operation instructions in the operation instruction register corresponding to the transmission queue cluster and the rule of balancing the number of operation instructions assigned to each transmission queue, the operation instructions in the operation instruction register corresponding to the transmission queue cluster are polled and dispatched to each transmission queue in the transmission queue cluster.

[0161] In some implementations, according to the type of the operation instruction in the operation instruction register corresponding to the transmit queue cluster and the rule of balancing the number of operation instructions assigned to each transmit queue, the operation instruction in the operation instruction register corresponding to the transmit queue cluster is polled and dispatched to each transmit queue in the transmit queue cluster, including:

[0162] According to the type of the operation instruction in the operation instruction register corresponding to the transmission queue cluster, the operation instruction in the operation instruction register that can only be transmitted through a specific transmission queue is dispatched to a specific transmission queue in the transmission queue cluster;

[0163] According to the number of operation instructions dispatched to each transmit queue and the rule of balancing the number of operation instructions dispatched to each transmit queue, the operation instructions in the operation instruction register that can be transmitted by any transmit queue are polled and dispatched to each transmit queue in the transmit queue cluster.

[0164] The instruction dispatching device provided in this embodiment belongs to the same application concept as the instruction dispatching method provided in the above embodiments of this application, and can execute the instruction dispatching method provided in any of the above embodiments of this application, and has the corresponding functional modules and beneficial effects of the execution method. For the technical details not fully described in this embodiment, please refer to the specific processing content of the instruction dispatching method provided in the above embodiments of this application, and will not be repeated here.

[0165] The functions implemented by the above queue division unit 100, the first dispatching unit 110 and the second dispatching unit 120 may be implemented by the same or different processors respectively, which is not limited in the embodiment of the present application.

[0166] It should be understood that the units in the above devices can be implemented in the form of a processor calling software. For example, the device includes a processor, the processor is connected to a memory, and instructions are stored in the memory. The processor calls the instructions stored in the memory to implement any of the above methods or realize the functions of each unit of the device, wherein the processor can be a general-purpose processor, such as a CPU or a microprocessor, etc., and the memory can be a memory in the device or a memory outside the device. Alternatively, the units in the device can be implemented in the form of hardware circuits, and the functions of some or all units can be realized by designing the hardware circuits. The hardware circuit can be understood as one or more processors; for example, in one implementation, the hardware circuit is an ASIC, and the functions of some or all of the above units are realized by designing the logical relationship of the components in the circuit; for another example, in another implementation, the hardware circuit can be implemented by PLD, taking FPGA as an example, which can include a large number of logic gate circuits, and the connection relationship between the logic gate circuits is configured by the configuration file, so as to realize the functions of some or all of the above units. All units of the above devices can be implemented in the form of a processor calling software, or in the form of hardware circuits, or in part by a processor calling software, and the remaining part is implemented in the form of hardware circuits.

[0167] In an embodiment of the present application, a processor is a circuit with the ability to process signals. In one implementation, the processor may be a circuit with the ability to read and run instructions, such as a CPU, a microprocessor, a GPU, or a DSP; in another implementation, the processor may implement certain functions through the logical relationship of a hardware circuit, and the logical relationship of the hardware circuit is fixed or reconfigurable, such as a hardware circuit implemented by an ASIC or PLD, such as an FPGA. In a reconfigurable hardware circuit, the process of the processor loading a configuration document to implement the hardware circuit configuration can be understood as the process of the processor loading instructions to implement the functions of some or all of the above units. In addition, it can also be a hardware circuit designed for artificial intelligence, which can be understood as an ASIC, such as an NPU, TPU, DPU, etc.

[0168] It can be seen that each unit in the above device can be one or more processors (or processing circuits) configured to implement the above method, such as: CPU, GPU, NPU, TPU, DPU, microprocessor, DSP, ASIC, FPGA, or a combination of at least two of these processor forms.

[0169] In addition, all or part of the units in the above device can be integrated together, or can be implemented independently. In one implementation, these units are integrated together and implemented in the form of a SOC. The SOC may include at least one processor for implementing any of the above methods or implementing the functions of each unit of the device. The type of the at least one processor may be different, for example, including a CPU and an FPGA, a CPU and an artificial intelligence processor, a CPU and a GPU, etc.

[0170] Optionally, an embodiment of the present application further provides a processor, which is configured to execute the instruction dispatching method described in any of the above embodiments. The specific processing process of the processor when executing the instruction dispatching method can refer to the introduction of the above corresponding embodiment.

[0171] Another embodiment of the present application further provides a computing device, which includes the above-mentioned processor, or the computing device is configured to execute the instruction dispatching method described in any of the above-mentioned embodiments. The computing device can be any hardware device with a processor, such as a personal computer, a laptop, a server, a workstation, a smart terminal, a wearable device, etc.

[0172] An embodiment of the present application also proposes a chip, which includes a processor and a data interface. The processor reads and runs a program stored in a memory through the data interface to execute the instruction dispatching method introduced in any of the above embodiments. The specific processing process and its beneficial effects can be found in the introduction to the embodiment of the above instruction dispatching method.

[0173] In addition to the above methods and devices, an embodiment of the present application may also be a computer program product, which includes computer program instructions, which, when executed by a processor, enable the processor to execute the steps of the instruction dispatching method described in any of the above embodiments of this specification.

[0174] The computer program product may be written in any combination of one or more programming languages ​​to write program codes for performing the operations of the embodiments of the present application, including object-oriented programming languages, such as Java, C++, etc., and conventional procedural programming languages, such as "C" language or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as an independent software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0175] In addition, an embodiment of the present application may also be a storage medium on which a computer program is stored, and the computer program is executed by a processor to execute the steps of the instruction dispatching method described in any of the above embodiments of this specification.

[0176] For the aforementioned method embodiments, for the sake of simplicity, they are all described as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the order of the actions described, because according to the present application, some steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

[0177] It should be noted that each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other. For the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0178] The steps in the methods of each embodiment of the present application can be adjusted in order, combined and deleted according to actual needs, and the technical features recorded in each embodiment can be replaced or combined.

[0179] The modules and sub-modules in the devices and terminals of the various embodiments of the present application can be combined, divided and deleted according to actual needs.

[0180] In the several embodiments provided in the present application, it should be understood that the disclosed terminals, devices and methods can be implemented in other ways. For example, the terminal embodiments described above are only schematic, for example, the division of modules or submodules is only a logical function division, and there may be other division methods in actual implementation, for example, multiple submodules or modules can be combined or integrated into another module, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or modules, which can be electrical, mechanical or other forms.

[0181] The modules or submodules described as separate components may or may not be physically separated, and the components of the modules or submodules may or may not be physical modules or submodules, that is, they may be located in one place, or they may be distributed on multiple network modules or submodules. Some or all of the modules or submodules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0182] In addition, each functional module or submodule in each embodiment of the present application may be integrated into one processing module, or each module or submodule may exist physically separately, or two or more modules or submodules may be integrated into one module. The above-mentioned integrated modules or submodules may be implemented in the form of hardware or in the form of software functional modules or submodules.

[0183] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0184] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly by hardware, software units executed by a processor, or a combination of the two. The software units may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0185] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0186] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for dispatching instructions, characterized in that: Applied to a processor using pipeline technology, the processor includes an operation instruction register for storing operation instructions assigned to a transmission queue cluster, and the method includes: According to the type of the operation instruction to be dispatched, the transmission queue is divided into a plurality of transmission queue clusters; Polling and distributing the operation instructions to be dispatched to the operation instruction registers corresponding to each of the transmission queue clusters; The following operations are performed for each of the transmit queue clusters: the operation instructions in the operation instruction register corresponding to the transmit queue cluster are polled and dispatched to each transmit queue in the transmit queue cluster.

2. The method according to claim 1, characterized in that The operation instructions to be dispatched include operation instructions that can only be transmitted through a specific transmission queue and operation instructions that can be transmitted through any transmission queue; According to the type of operation instructions to be dispatched, the transmission queue is divided into multiple transmission queue clusters, including: According to the operation instructions to be dispatched that can only be transmitted through a specific transmission queue, the transmission queue is divided into transmission queue clusters to obtain multiple transmission queue clusters; Among them, the transmission queues in a transmission queue cluster are used to transmit the same type of operation instructions.

3. The method according to claim 1, characterized in that The operation instructions to be dispatched include operation instructions that are only transmitted through a specific transmission queue, and operation instructions that can be transmitted through any transmission queue; The method of polling and distributing the operation instructions to be dispatched to the operation instruction registers corresponding to the transmission queue clusters comprises: Allocating, among the operation instructions to be dispatched, an operation instruction that can only be transmitted through a specific transmission queue to an operation instruction register corresponding to a transmission queue cluster used for transmitting operation instructions of a type corresponding to the operation instruction; The operation instructions to be dispatched that can be transmitted through any transmission queue are polled and allocated to the operation instruction registers corresponding to each of the transmission queue clusters.

4. The method according to claim 3, characterized in that The operation instructions to be dispatched that can be transmitted through any transmission queue are polled and distributed to the operation instruction registers corresponding to each of the transmission queue clusters, including: According to the number of allocated operation instructions in the operation instruction registers corresponding to each of the transmitting queue clusters, and in accordance with the set instruction allocation rules, the operation instructions to be dispatched that can be transmitted through any transmitting queue are polled and allocated to the operation instruction registers corresponding to each of the transmitting queue clusters.

5. The method according to claim 4, characterized in that The set instruction allocation rules include: a rule that balances the number of operation instructions allocated to each transmission queue cluster, or a rule that the difference between the number of operation instructions allocated to the first transmission queue cluster and the number of operation instructions allocated to the second transmission queue cluster is a first value.

6. The method according to any one of claims 1 to 5, characterized in that The operation instruction register corresponding to the transmission queue cluster includes operation instructions that can only be transmitted through a specific transmission queue and operation instructions that can be transmitted through any transmission queue; The operation instructions in the operation instruction register corresponding to the transmission queue cluster are polled and dispatched to each transmission queue in the transmission queue cluster, including: According to the type of operation instructions in the operation instruction register corresponding to the transmission queue cluster and the rule of balancing the number of operation instructions assigned to each transmission queue, the operation instructions in the operation instruction register corresponding to the transmission queue cluster are polled and dispatched to each transmission queue in the transmission queue cluster.

7. The method according to claim 6, characterized in that According to the type of the operation instruction in the operation instruction register corresponding to the transmission queue cluster, and in accordance with the rule of balancing the number of operation instructions assigned to each transmission queue, the operation instruction in the operation instruction register corresponding to the transmission queue cluster is polled and dispatched to each transmission queue in the transmission queue cluster, including: According to the type of the operation instruction in the operation instruction register corresponding to the transmission queue cluster, the operation instruction in the operation instruction register that can only be transmitted through a specific transmission queue is dispatched to a specific transmission queue in the transmission queue cluster; According to the number of operation instructions dispatched to each transmit queue and the rule of balancing the number of operation instructions dispatched to each transmit queue, the operation instructions in the operation instruction register that can be transmitted by any transmit queue are polled and dispatched to each transmit queue in the transmit queue cluster.

8. An instruction dispatching device, characterized in that: Applied to a processor using pipeline technology, the processor includes an operation instruction register for storing operation instructions assigned to a transmission queue cluster, and the device includes: A queue division unit, used for dividing the transmission queue into a plurality of transmission queue clusters according to the type of the operation instruction to be dispatched; A first dispatching unit, configured to poll and distribute the operation instructions to be dispatched to the operation instruction registers corresponding to the respective transmission queue clusters; The second dispatching unit is used to perform the following operations on each of the transmit queue clusters: dispatching the operation instructions in the operation instruction register corresponding to the transmit queue cluster to each transmit queue in the transmit queue cluster in a polling manner.

9. A processor, characterized in that: The processor is configured to implement the instruction dispatching method according to any one of claims 1 to 7.

10. A computing device, characterized in that: Comprising a processor as claimed in claim 9.

11. A computer program product, characterized in that The method comprises computer program instructions, which, when executed by a processor, cause the processor to execute the instruction dispatching method according to any one of claims 1 to 7.

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