Refresh circuit and memory

Abstract

The invention relates to a refresh circuit and a memory. The refresh circuit comprises at least two storage arrays which share the same address transmission bus; the signal synthesis circuit is used for receiving a refresh pulse signal and target address signals of the storage arrays sharing the same address transmission bus, and combining the target address signals of the storage arrays sharing the same address transmission bus into an address synthesis signal based on the refresh pulse signal, the address synthesis signal is transmitted to each storage array through the shared address transmission bus; and each storage array is used for acquiring the corresponding target address signal from the address synthesis signal. The circuit area can be saved, and the transmission line requirement can be met.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a refresh circuit and a memory. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory. Its main working principle is to use the amount of charge stored in a capacitor to represent whether a binary bit is 1 or 0. Due to the leakage of transistors in reality, the amount of charge stored on the capacitor is not enough to correctly judge the data, resulting in data corruption. Therefore, for DRAM, periodic charging is inevitable. It is this characteristic that requires regular refresh that makes DRAM called "dynamic" memory.

[0003] In the related art, during the regular refresh process of DRAM, a row hammer refresh (RHR) is inserted. The Joint Electron Device Engineering Council (JEDEC) requires that each storage array of DRAM can be activated separately, which results in different RHR addresses of each storage array. Different row hammer refresh circuits (RHR circuits) are required to record and transmit the frequently accessed row addresses in each storage array respectively, so as to perform row hammer refresh on each storage array separately. However, this places high requirements on the circuit area and transmission lines. Summary of the invention

[0004] Based on this, it is necessary to provide a refresh circuit and a memory that can save circuit area and meet the requirements of transmission lines.

[0005] In a first aspect, a refresh circuit is provided, the refresh circuit comprising:

[0006] At least two storage arrays share the same address transmission bus;

[0007] A signal synthesis circuit, used for receiving a refresh pulse signal and target address signals of the storage arrays sharing the same address transmission bus, merging the target address signals of the storage arrays sharing the same address transmission bus into an address synthesis signal based on the refresh pulse signal, and transmitting the address synthesis signal to the storage arrays through the shared address transmission bus;

[0008] Each of the storage arrays is used to obtain the corresponding target address signal from the address synthesis signal.

[0009] In one embodiment, the signal synthesis circuit includes:

[0010] A sampling signal generating circuit, configured to receive a refresh pulse signal and generate a plurality of sampling signals based on the refresh pulse signal, wherein the plurality of sampling signals correspond one-to-one to each of the storage arrays sharing the same address transmission bus, and time periods in which the plurality of sampling signals are at valid levels do not overlap;

[0011] The synthetic signal output circuit is coupled to the sampling signal generating circuit, and is used to receive the multiple sampling signals and the target address signals of the corresponding storage arrays, and output the corresponding target address signals of the storage array when each of the sampling signals is at a valid level, so as to merge the target address signals of the multiple storage arrays that share the same address transmission bus into an address synthetic signal.

[0012] In one embodiment, each of the target address signals includes an N-bit target address sub-signal, the address synthesis signal includes an N-bit address synthesis sub-signal, the address transmission bus includes N address transmission lines corresponding to the N-bit address synthesis sub-signals, and N is a positive integer; the synthesis signal output circuit includes:

[0013] The address selector comprises N multiplexers corresponding one to one with the N-bit target address sub-signals, the multiple input terminals of each multiplexer are used to respectively receive one-bit target address sub-signal corresponding to each storage array sharing the same address transmission bus, the multiple control terminals of the multiplexer are used to respectively receive the multiple sampling signals, and the output terminals of the multiplexer are connected to each storage array via a shared address transmission line.

[0014] In one embodiment, the multiplexer comprises:

[0015] A plurality of first tri-state inverters corresponding one to each of the storage arrays sharing the same address transmission line; an input terminal of each of the first tri-state inverters is used to receive a target address sub-signal of the corresponding storage array, and a control terminal of each of the first tri-state inverters is used to receive an inverted signal of the corresponding sampling signal;

[0016] A first NOT gate, wherein the input end of the first NOT gate is respectively connected to the output ends of the plurality of first three-state inverters, and the output end of the first NOT gate is used to output the address synthesis sub-signal.

[0017] In one embodiment, the synthesized signal output circuit further includes:

[0018] The latch circuit is used to enable the multiplexer to keep outputting the currently corresponding target address sub-signal when each of the sampling signals is at an invalid level.

[0019] In one embodiment, the latch circuit comprises:

[0020] An address latch signal generating circuit, used for combining a plurality of the sampling signals to generate an address latch signal;

[0021] A second three-state inverter, wherein the input end of the second three-state inverter is connected to the output end of the first NOT gate, the control end of the second three-state inverter is used to receive the address latch signal, and the output end of the second three-state inverter is connected to the input end of the first NOT gate.

[0022] In one embodiment, the address latch signal generating circuit includes:

[0023] At least two first NAND gates, each input end of the at least two first NAND gates is used to receive each of the sampling signals respectively;

[0024] NOR gate, each input end of the NOR gate is connected to the output ends of the at least two first NAND gates in a one-to-one correspondence, and the output end of the NOR gate is used to output the address latch signal.

[0025] In one embodiment, the sampling signal generating circuit includes:

[0026] A delay circuit is used to receive the refresh pulse signal, perform multiple delay processing on the pulse refresh signal to generate multiple intermediate signals, and output the undelayed refresh pulse signal and the multiple intermediate signals together as multiple delayed pulse signals; wherein the multiple delayed pulse signals have a first delay time in sequence;

[0027] The pulse width adjustment circuit is coupled to the delay circuit, and is used to receive the multiple delayed pulse signals respectively, and adjust the pulse widths of the multiple delayed pulse signals to generate the multiple sampling signals, and the multiple sampling signals also have the first delay time in sequence.

[0028] In one embodiment, the pulse width adjustment circuit includes a plurality of pulse width adjustment sub-circuits, each of which includes:

[0029] A delay device, wherein the input end of the delay device is used to receive a corresponding delayed pulse signal;

[0030] A second NOT gate, wherein an input end of the second NOT gate is connected to an output end of the delay device;

[0031] A second NAND gate, wherein the first input terminal of the second NAND gate is connected to the input terminal of the delay device, the second input terminal of the second NAND gate is connected to the output terminal of the second NAND gate, and the output terminal of the second NAND gate is used to output a corresponding sampling signal.

[0032] In one embodiment, the refresh circuit further includes:

[0033] A refresh pulse generator is used to receive a refresh instruction; based on the refresh instruction, generate and output a first refresh pulse and a second refresh pulse in sequence, so that each of the storage arrays performs a first refresh operation based on the first refresh pulse, and performs a second refresh operation based on the second refresh pulse and the corresponding target address signal; and output the first refresh pulse as the refresh pulse signal to the signal synthesis circuit.

[0034] In one embodiment, the second refresh pulse has a second delay time with the first refresh pulse, so that the time of generating the second refresh pulse is no earlier than the time when the target address signal is last received in each of the storage arrays sharing the same address transmission bus.

[0035] In one embodiment, the first refresh pulse includes a plurality of first refresh pulse sub-signals, each of the first refresh pulse sub-signals is in a different time period, and the plurality of first refresh pulse sub-signals are sequentially separated by a third delay time, each of the first refresh pulse sub-signals corresponds to at least one of the memory arrays sharing the same address transmission bus, and each of the memory arrays performs a first refresh operation based on the corresponding first refresh pulse sub-signal;

[0036] The second refresh pulse includes multiple second refresh pulse sub-signals corresponding one by one to multiple first refresh pulse sub-signals, each of the second refresh pulse sub-signals has the second delay time with a corresponding one of the first refresh pulse sub-signals; each of the second refresh pulse sub-signals is in a different time period, and multiple second refresh pulse sub-signals have the third delay time in sequence, each of the second refresh pulse sub-signals corresponds to at least one of the storage arrays sharing the same address transmission bus, and each of the storage arrays performs a second refresh operation based on the corresponding second refresh pulse sub-signal.

[0037] In one embodiment, the storage arrays corresponding to the same first refresh pulse sub-signal are arranged adjacent to each other in pairs, or the storage arrays corresponding to the same first refresh pulse sub-signal are evenly distributed in the corresponding memory.

[0038] In one embodiment, the storage arrays that share the same address transmission bus are arranged adjacent to each other in a first direction or a second direction, and the first direction and the second direction intersect vertically.

[0039] In a second aspect, a memory is provided, wherein the memory includes the refresh circuit provided in the first aspect.

[0040] The refresh circuit and memory include a signal synthesis circuit and at least two memory arrays sharing the same address transmission bus. The signal synthesis circuit receives a refresh pulse signal and target address signals of each memory array sharing the same address transmission bus. Based on the refresh pulse signal, the target address signals of each memory array sharing the same address transmission bus are merged into an address synthesis signal, and the address synthesis signal is transmitted to each memory array through the shared address transmission bus. Each memory array obtains the corresponding target address signal from the address synthesis signal, thereby realizing the transmission of the refresh address of each memory array. Moreover, at least two memory arrays share one address transmission bus, which can save the overall occupied area of ​​the memory and meet the requirements of the transmission line. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0042] Figure 1 It is an application scenario diagram of a refresh circuit in the related technology;

[0043] Figure 2 This is an application scenario diagram of a refresh circuit according to an embodiment;

[0044] Figure 3 is a structural schematic diagram of a refresh circuit according to an embodiment;

[0045] Figure 4 for Figure 3 The circuit timing diagram corresponding to the refresh circuit shown;

[0046] Figure 5 is a structural schematic diagram of a signal synthesis circuit according to an embodiment;

[0047] Figure 6 for Figure 5 The circuit timing diagram corresponding to the signal synthesis circuit shown;

[0048] Figure 7 is a schematic structural diagram of a synthetic signal output circuit according to an embodiment;

[0049] Figure 8 A schematic diagram of the structure of a multiplexer according to an embodiment;

[0050] Fig. 9 for Figure 8 The circuit timing diagram corresponding to the multiplexer shown;

[0051] Fig.10 A schematic diagram of the structure of a multiplexer according to an embodiment;

[0052] Fig.11 is a schematic structural diagram of a synthetic signal output circuit according to an embodiment;

[0053] Fig.12 is a schematic structural diagram of a synthetic signal output circuit according to an embodiment;

[0054] Fig.13 for Fig.12 The circuit timing diagram corresponding to the synthetic signal output circuit shown;

[0055] Fig.14 A schematic structural diagram of an address latch signal generating circuit according to an embodiment;

[0056] Fig.15 for Fig.14 The circuit timing diagram corresponding to the address latch signal generating circuit shown;

[0057] Fig.16 is a schematic structural diagram of a sampling signal generating circuit according to an embodiment;

[0058] Fig.17 for Fig.16 The circuit timing diagram corresponding to the sampling signal generating circuit shown;

[0059] Fig.18 A schematic diagram of the structure of a pulse width adjustment sub-circuit according to an embodiment;

[0060] Fig.19 for Fig.18 The circuit timing diagram corresponding to the pulse width adjustment subcircuit shown;

[0061] Fig. 20 is a structural schematic diagram of a refresh circuit according to an embodiment;

[0062] Fig.21 is a timing diagram of a refresh pulse of an embodiment;

[0063] Fig. 22 FIG. 4 is a schematic diagram of the structure of a refresh circuit according to an embodiment of the present invention.

[0064] Description of reference numerals:

[0065] 101, a storage array, 102, a row hammer refresh circuit (RHR circuit);

[0066] 201, storage array, 202, row hammer refresh circuit (RHR circuit);

[0067] 10. Signal synthesis circuit;

[0068] 11. sampling signal generating circuit, 111. delay circuit, 112. pulse width adjustment circuit, 113. pulse width adjustment sub-circuit, 114. delay device, 115. second NOT gate, 116. second NAND gate;

[0069] 12. a synthesized signal output circuit, 120. a multiplexer, 121. a first NOT gate, 122. a first three-state inverter, 123. a third NAND gate, 124. a plurality of second three-state inverters, 125. a latch circuit, 126. an address latch signal generating circuit, 127. a second three-state inverter, 128. a NOR gate, 129. a first NAND gate;

[0070] 20. Address transmission bus, 21. Address transmission line;

[0071] 30. Storage array;

[0072] 40. Refresh pulse generator. DETAILED DESCRIPTION

[0073] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0074] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0075] It is understood that the terms "first", "second", etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0076] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.

[0077] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the relevant listed items.

[0078] Low Power Double Data Rate SDRAM (LPDDR for short) is a low-power memory communication standard developed by JEDEC for portable electronic terminals. It can be simply divided into five generations of products: LPDDR, LPDDR2, LPDDR3, LPDDR4 (including LPDDR4X) and LPDDR5. LPDDR5 has 16 storage arrays, each of which has a row hammer refresh circuit (RHR circuit). Each row hammer refresh circuit (RHR circuit) records and transmits the frequently accessed row addresses in the corresponding storage array to perform row hammer refresh of the corresponding storage array.

[0079] Figure 1 It is an application scenario diagram of the refresh circuit in the related technology, such as Figure 1 As shown, 16 memory arrays 101 and 16 row hammer refresh circuits (RHR circuits) 102 are provided in the DRAM. The 16 memory arrays 101 are arranged in an array. The 16 row hammer refresh circuits (RHR circuits) 102 correspond to the 16 memory arrays 101 one by one, and each row hammer refresh circuit (RHR circuit) 102 is adjacent to and connected to the corresponding memory array 101. In this way, a separate reserved area is provided for the row hammer refresh circuit (RHR circuit) 102, and the overall area of ​​the DRAM is larger.

[0080] If 16 row hammer refresh circuits (RHR circuits) 102 are arranged together in the free area of ​​DRAM, each row hammer refresh circuit (RHR circuit) 102 needs to be individually provided with an address transmission bus (one address transmission bus usually includes 17 address transmission lines) connected between the row hammer refresh circuit (RHR circuit) 102 and the corresponding storage array 101, so as to transmit the address recorded by the row hammer refresh circuit (RHR circuit) 102 to the corresponding storage array 101. In this way, the number of lines that need to be arranged as a whole is relatively large (16*17=272), and a sufficient number of lines cannot be provided at present.

[0081] Based on the above situation, the present application provides a refresh circuit and memory, including a signal synthesis circuit and at least two storage arrays sharing the same address transmission bus. The signal synthesis circuit combines the target address signals of each storage array sharing the same address transmission bus into an address synthesis signal based on a refresh pulse signal, and transmits the address synthesis signal to each storage array through the shared address transmission bus. The row hammer refresh circuits (RHR circuits) corresponding to each storage array can be set together in the vacant area of ​​the memory chip to save the overall memory footprint. Moreover, at least two storage arrays share one address transmission bus, which can greatly reduce the number of lines that need to be set and meet the requirements of the transmission line.

[0082] Figure 2 FIG. 1 is an application scenario diagram of a refresh circuit according to an embodiment of the present invention. Figure 2 As shown, 16 memory arrays 201 and 16 row hammer refresh circuits (RHR circuits) 202 are provided in the DRAM. The 16 memory arrays 201 are arranged in an array. The 16 row hammer refresh circuits (RHR circuits) 202 are provided together in a spare area of ​​the DRAM. The 16 row hammer refresh circuits (RHR circuits) 202 correspond to the 16 memory arrays 201 one by one. Every 8 row hammer refresh circuits (RHR circuits) 202 are connected to the corresponding memory array 201 through the same address transmission bus 203. Figure 2 and Figure 1 In comparison, because the RHR circuit does not need to occupy the area of ​​the memory array region, the overall memory footprint is greatly reduced, and the number of lines that need to be set in the memory array region is also greatly reduced.

[0083] Figure 3 FIG. 1 is a schematic diagram of a refresh circuit according to an embodiment of the present invention. Figure 3As shown, the refresh circuit includes a signal synthesis circuit 10 and at least two storage arrays 30 sharing the same address transmission bus 20. The signal synthesis circuit 10 is used to receive a refresh pulse signal and a target address signal of each storage array 30 sharing the same address transmission bus 20, synthesize the target address signals of each storage array 30 sharing the same address transmission bus 20 into an address synthesis signal based on the refresh pulse signal, and transmit the address synthesis signal to each storage array 30 through the common address transmission bus 20. Each storage array 30 is used to obtain a corresponding target address signal from the address synthesis signal.

[0084] Figure 4 for Figure 3 The circuit timing diagram corresponding to the refresh circuit shown in FIG. Figure 4 As shown, target address signals of a plurality of memory arrays 30 are synthesized into one address synthesis signal.

[0085] In the above embodiment, the refresh circuit includes a signal synthesis circuit and at least two storage arrays sharing the same address transmission bus. The signal synthesis circuit receives a refresh pulse signal and a target address signal of each storage array sharing the same address transmission bus. Based on the refresh pulse signal, the target address signals of each storage array sharing the same address transmission bus are merged into an address synthesis signal, and the address synthesis signal is transmitted to each storage array through the common address transmission bus. Each storage array obtains the corresponding target address signal from the address synthesis signal, thereby realizing the transmission of the refresh address of each storage array. Moreover, at least two storage arrays share one address transmission bus, which can not only save the overall occupied area of ​​the memory, but also meet the requirements of the transmission line.

[0086] Figure 5 FIG. 1 is a schematic diagram of a signal synthesis circuit according to an embodiment of the present invention. Figure 5 As shown, M storage arrays share the same transmission address bus as an example for explanation, where M is a positive integer. In one embodiment, the signal synthesis circuit 10 includes a sampling signal generation circuit 11 and a synthesis signal output circuit 12. The sampling signal generation circuit 11 is used to receive a refresh pulse signal, and generate a plurality of sampling signals based on the refresh pulse signal. The plurality of sampling signals correspond to each storage array 30 sharing the same address transmission bus 20, and the time periods in which the plurality of sampling signals are at the effective level do not overlap. The synthesis signal output circuit 12 is coupled to the sampling signal generation circuit 11, and is used to receive a plurality of sampling signals and target address signals of the storage arrays 30 corresponding to each other, and output the target address signals of the corresponding storage arrays 30 when each sampling signal is at the effective level, so as to merge the target address signals of the plurality of storage arrays 30 sharing the same address transmission bus 20 into an address synthesis signal.

[0087] Figure 6 for Figure 5The circuit timing diagram corresponding to the signal synthesis circuit shown is as follows: Figure 6 As shown, exemplarily, the sampling signal generating circuit 11 uses the refresh pulse signal as the first sampling signal, delays the first sampling signal for a set time as the second sampling signal, delays the second sampling signal for a set time as the third sampling signal, and so on, until the M-1th sampling signal is delayed for a set time as the Mth sampling signal, thereby obtaining all sampling signals, and the time periods of each sampling signal at the effective level do not overlap. When each sampling signal is at the effective level, the target address signal of the corresponding storage array 30 is sampled and output as an address synthesis signal, so that the time periods of each target address signal do not overlap and can be combined into an address synthesis signal.

[0088] In the above embodiment, the signal synthesis circuit 10 includes a sampling signal generation circuit 11 and a synthesis signal output circuit 12. The sampling signal generation circuit 11 first generates a plurality of sampling signals based on a refresh pulse signal, and the time periods in which the plurality of sampling signals are at a valid level do not overlap. The synthesis signal output circuit 12 then outputs a corresponding target address signal of the storage array 30 when each sampling signal is at a valid level, thereby merging the target address signals of the plurality of storage arrays 30 sharing the same address transmission bus 20 into an address synthesis signal.

[0089] Figure 7 FIG. 1 is a schematic diagram of the structure of a synthetic signal output circuit according to an embodiment of the present invention, and takes M storage arrays sharing the same transmission address bus as an example for explanation. Figure 7 As shown, in one embodiment, each target address signal includes an N-bit target address sub-signal, the address synthesis signal includes an N-bit address synthesis sub-signal, and the address transmission bus 20 includes N address transmission lines 21 corresponding to the N-bit address synthesis sub-signals, where N is a positive integer.

[0090] The synthetic signal output circuit 12 includes an address selector, which includes N multiplexers 120 corresponding one-to-one to the N-bit target address sub-signals. The multiple input ends of each multiplexer 120 are used to respectively receive a one-bit target address sub-signal corresponding to the M storage arrays 30 that share the same address transmission bus 20. The multiple control ends of the multiplexer 120 are used to respectively receive multiple sampling signals. The output end of the multiplexer 120 is connected to each storage array 30 via a shared address transmission line 21.

[0091] Exemplarily, the first multiplexer 120 receives the first target address sub-signal in the target address signals of the storage arrays 30 that share the same address transmission bus 20, generates the first address synthesis sub-signal, and outputs it to the first address transmission line 21. The second multiplexer 120 receives the second target address sub-signal in the target address signals of the storage arrays 30 that share the same address transmission bus 20, generates the second address synthesis sub-signal, and outputs it to the second address transmission line 21. The third multiplexer 120 receives the third target address sub-signal in the target address signals of the storage arrays 30 that share the same address transmission bus 20, generates the third address synthesis sub-signal, and outputs it to the third address transmission line 21… and so on, until the Nth multiplexer 120 receives the Nth target address sub-signal in the target address signals of the storage arrays 30 that share the same address transmission bus 20, generates the Nth address synthesis sub-signal, and outputs it to the Nth address transmission line 21.

[0092] Since the address signal of each storage array 30 is composed of a multi-bit signal, a multiplexer 120 is used to merge the address signals of multiple storage arrays 30 for each bit signal, and a common address transmission line 21 can be used to transmit the merged signal to each storage array 30. In this way, the number of address transmission lines 21 is only determined by the number of bits of the address signal, and is independent of the number of storage arrays 30. It will not increase with the increase in the number of storage arrays 30. Only one set of address transmission lines 21 (the same number of address transmission lines as the number of address signal bits) can be used to meet the transmission requirements of multiple storage arrays 30 for row hammer address signals, which can save a large number of address transmission lines, save a large number of lines for the memory, and provide convenience for the layout and routing of the memory chip.

[0093] Figure 8 : is a schematic diagram of the structure of a multiplexer of an embodiment, and here, eight storage arrays 30 share one address transmission line 21 as an example for explanation (M=8, in other embodiments, M can be any integer greater than or equal to 2, and is not specifically limited here). Figure 8 As shown, in one implementation, the multiplexer 120 includes a first NOT gate 121 and a plurality of first three-state inverters 122. The plurality of first three-state inverters 122 correspond one-to-one to each storage array 30 that shares the same address transmission line 21. The input end of each first three-state inverter 122 is used to receive the target address sub-signal of the corresponding storage array 30, and the control end of each first three-state inverter 122 is used to receive the inverted signal of the corresponding sampling signal. The input end of the first NOT gate 121 is respectively connected to the output ends of the plurality of first three-state inverters 122, and the output end of the first NOT gate 121 is used to output the address synthesis sub-signal.

[0094] Fig. 9 for Figure 8 The circuit timing diagram corresponding to the multiplexer shown in FIG. Fig. 9 As shown, exemplarily, the input signals of the plurality of first tri-state inverters 122 are corresponding target address sub-signals (which may be H or L according to specific address information), and each first tri-state inverter 122 controls its output based on the inverted signal of the corresponding sampling signal received. Specifically, when the sampling signal is at a low level (its inverted signal is at a high level), the inverted signal of the corresponding target address sub-signal is controlled to be output, and when the sampling signal is at a high level (its inverted signal is at a low level), the output terminal is controlled to be in a high impedance state and no signal is output; the first NOT gate 121 inverts the output signal of each first tri-state inverter 122, and when the sampling signal is at a low level, the corresponding target address sub-signal is output. Since the time periods of the plurality of sampling signals being at an effective level (low level) do not overlap, the time periods of the corresponding target address sub-signals output by each first tri-state inverter 122 based on the corresponding sampling signal do not overlap, thereby realizing the sequential transmission of target address sub-signals of different storage arrays in different time periods on the same shared address transmission line 21.

[0095] In the above embodiment, the first NOT gate 121 and the plurality of first three-state inverters 122 cooperate to implement the multiplexer 120, which can combine one-bit target address sub-signals corresponding to each storage array 30 sharing the same address transmission bus 20 into one-bit address synthesis sub-signal transmitted by one address transmission line.

[0096] Fig.10 FIG. 1 is a schematic diagram of a structure of a multiplexer according to an embodiment of the present invention. Fig.10 As shown, in another implementation, the multiplexer 120 includes a third NAND gate 123 and a plurality of second three-state inverters 124. The plurality of second three-state inverters 124 correspond one-to-one to each storage array 30 that shares the same address transmission line 21. The input end of each second three-state inverter 124 is used to receive the target address sub-signal of the corresponding storage array 30, and the control end of each second three-state inverter 124 is used to receive the inverted signal of the corresponding sampling signal. The first input end of the third NAND gate 123 is respectively connected to the output ends of the plurality of second three-state inverters 124, the second input end of the third NAND gate 123 is used to receive the reset signal, and the output end of the third NAND gate 123 is used to output the address synthesis sub-signal.

[0097] In the above embodiment, the first NOT gate 121 is replaced by a third NAND gate 123, and one input end of the third NAND gate 123 receives a reset signal, so that when the reset signal is at a low level, the output end of the third NAND gate 123 continuously outputs a high level, and a reset can be performed. When the reset signal is at a high level, the third NAND gate 123 has the same function as the first NOT gate 121, and can output a one-bit address synthesis sub-signal that is a combination of one-bit target address sub-signals corresponding to each storage array 30 that shares the same address transmission bus 20.

[0098] Fig.11 FIG. 1 is a schematic diagram of a structure of a synthetic signal output circuit according to an embodiment of the present invention. Fig.11 As shown, in one embodiment, the synthesized signal output circuit 12 further includes a latch circuit 125. The latch circuit 125 is used to enable the multiplexer 120 to keep outputting the currently corresponding target address signal when each sampling signal is at an invalid level.

[0099] For example, Fig.11 As shown, the synthesized signal output circuit 12 includes a plurality of latch circuits 125 , and the latch circuits 125 are connected to the multiplexers 120 in a one-to-one correspondence.

[0100] In the above embodiment, by adding the latch circuit 125 , the multiplexer 120 can continuously output the current corresponding target address signal before transmitting the next target address signal, so as to ensure that the memory array 30 can receive the corresponding target address signal.

[0101] Fig.12 FIG. 1 is a schematic diagram of the structure of a synthetic signal output circuit according to an embodiment, in which eight storage arrays 30 share one address transmission line 21 as an example for explanation (M=8, in other embodiments, M can be any integer greater than or equal to 2, which is not specifically limited here). Fig.12 As shown, optionally, the latch circuit 125 includes an address latch signal generating circuit 126 and a third tri-state inverter 127. The address latch signal generating circuit 126 is used to merge multiple sampling signals into an address latch signal. The input end of the third tri-state inverter 127 is connected to the output end of the first NOT gate 121, the control end of the third tri-state inverter 127 is used to receive the address latch signal, and the output end of the third tri-state inverter 127 is connected to the input end of the first NOT gate 121.

[0102] Fig.13 for Fig.12 The circuit timing diagram corresponding to the synthetic signal output circuit shown in FIG. Fig.13As shown, if the inverted signal of the target address sub-signal currently sampled and output by the first tri-state inverter 122 is at a high level and the input of the first NOT gate 121 is at a high level, the output of the first NOT gate 121 and the input of the third tri-state inverter 127 are at a low level, and the output of the third tri-state inverter 127 is at a high level, the input of the first NOT gate 121 is thus maintained at a high level, the output of the first NOT gate 121 is maintained at a low level, the input of the third tri-state inverter 127 is also maintained at a low level, and the output of the third tri-state inverter 127 is maintained at a high level.

[0103] Similarly, if the inverted signal of the target address sub-signal currently sampled and output by the first three-state inverter 122 is at a low level, and if the input end of the first NOT gate 121 is at a low level, the output end of the first NOT gate 121 is at a high level, the input end of the third three-state inverter 127 is also at a high level, and the output end of the third three-state inverter 127 is at a low level. The input end of the first NOT gate 121 is thus maintained at a low level, the output end of the first NOT gate 121 is maintained at a high level, the input end of the third three-state inverter 127 is also maintained at a high level, and the output end of the third three-state inverter 127 is maintained at a low level.

[0104] In the above embodiment, the latch circuit 125 includes an address latch signal generating circuit 126 and a third three-state inverter 127. The address latch signal generating circuit 126 generates an address latch signal based on the sampling signal. The third three-state inverter 127 maintains the output of the first NOT gate 121 unchanged based on the address latch signal, thereby enabling the multiplexer 120 to continuously output the currently corresponding target address signal.

[0105] Fig.14 FIG. 1 is a schematic diagram of the structure of an address latch signal generating circuit according to an embodiment of the present invention. Fig.14 As shown, optionally, the address latch signal generating circuit 126 includes a NOR gate 128 and at least two first NAND gates 129. Each input end of the at least two first NAND gates 129 is used to receive each sampling signal. Each input end of the NOR gate 128 is connected to the output end of the at least two first NAND gates 129 in a one-to-one correspondence, and the output end of the NOR gate 128 is used to output the address latch signal.

[0106] Fig.15 for Fig.14 The circuit timing diagram corresponding to the address latch signal generating circuit shown in FIG. Fig.15 As shown, the input signals (ie, sampling signals) of the first NAND gates 129 are sequentially at a low level, and the output signals (ie, address latch signals) of the NOR gates 128 are correspondingly at a low level. Fig.12According to the output address latch signal, when each sampling signal is at a valid level (low level), the address latch signal is also at a low level, and the control output of the third three-state inverter 127 based on the low-level address latch signal is a high-impedance state, that is, the third three-state inverter 127 does not work at this time, and does not latch the target address sub-signal previously transmitted by the first NOT gate 121. At this time, the first NOT gate 121 inverts the inverted signal of the corresponding target address sub-signal sampled by the first three-state gate 122 and then outputs it, that is, when the address latch signal is at a low level, the synthetic signal sub-circuit selects one of the input multiple target address sub-signals and outputs it; when all sampling signals are at When it is at an invalid level (high level), the address latch signal is also at a high level. The third three-state inverter 127 inverts the output signal of the first NOT gate 121 and outputs it based on the control of the low-level address latch signal (the same as the input signal of the first NOT gate 121). That is, the third three-state inverter 127 performs a latching function at this time to latch the target address sub-signal previously transmitted by the first NOT gate 121. That is, when the address latch signal is at a high level, the synthetic signal output circuit outputs and latches one of the multiple target address sub-signals sampled previously until the next sampling signal is at a valid level, thereby selecting and outputting the next one of the multiple target address sub-signals.

[0107] In the above embodiment, the NOR gate 128 and at least two first NAND gates 129 cooperate to implement the address latch signal generating circuit 126, so that multiple sampling signals can be combined to generate an address latch signal.

[0108] Fig.16 FIG. 1 is a schematic diagram of a sampling signal generating circuit according to an embodiment of the present invention. Fig.16 As shown, in one embodiment, the sampling signal generating circuit 11 includes a delay circuit 111 and a pulse width adjustment circuit 112. The delay circuit 111 is used to receive a refresh pulse signal, perform multiple delay processes on the pulse refresh signal to generate multiple intermediate signals, and output the undelayed refresh pulse signal and the multiple intermediate signals together as multiple delayed pulse signals. Among them, the multiple delayed pulse signals have a first delay time in sequence. The pulse width adjustment circuit 112 is coupled to the delay circuit 111, and is used to receive the multiple delayed pulse signals respectively, and adjust the pulse widths of the multiple delayed pulse signals to generate multiple sampling signals, and the multiple sampling signals also have a first delay time in sequence.

[0109] Fig.17 for Fig.16 The circuit timing diagram corresponding to the sampling signal generating circuit shown in FIG. Fig.17 As shown, the pulse refresh signal is delayed multiple times to generate multiple intermediate signals, and the undelayed refresh pulse signal and the multiple intermediate signals are used together as multiple delayed pulse signals to adjust the pulse width to generate multiple sampling signals.

[0110] In the above embodiment, the sampling signal generating circuit 11 includes a delay circuit 111 and a pulse width adjustment circuit 112. The delay circuit 111 performs multiple delay processing on the pulse refresh signal to generate multiple intermediate signals. The pulse width adjustment circuit 112 adjusts the pulse widths of the undelayed refresh pulse signal and the multiple intermediate signals to generate multiple sampling signals, thereby obtaining multiple sampling signals having a first delay time in sequence.

[0111] Fig.18 FIG. 1 is a schematic diagram of the structure of a pulse width adjustment subcircuit according to an embodiment of the present invention. Fig.18 As shown, in one embodiment, the pulse width adjustment circuit 112 includes a plurality of pulse width adjustment sub-circuits 113, each of which includes a delayer 114, a second NOT gate 115, and a second NAND gate 116. The input end of the delayer 114 is used to receive a corresponding delayed pulse signal. The input end of the second NOT gate 115 is connected to the output end of the delayer 114. The first input end of the second NAND gate 116 is connected to the input end of the delayer 114, the second input end of the second NAND gate 116 is connected to the output end of the second NOT gate 115, and the output end of the second NAND gate 116 is used to output a corresponding sampling signal.

[0112] Fig.19 for Fig.18 The circuit timing diagram corresponding to the pulse width adjustment subcircuit shown in FIG. Fig.19 As shown, the input signal of the delay device 114 is delayed to obtain the output signal of the delay device 114, the output signal of the delay device 114 is inverted to obtain the output signal of the second NOT gate 115, and the output signal of the second NOT gate 115 and the input signal of the delay device 114 are ANDed to obtain the output signal of the second NAND gate 116 (i.e., the sampling signal).

[0113] In the above embodiment, the delay device 114, the second NOT gate 115 and the second NAND gate 116 cooperate to implement a pulse width adjustment subcircuit, which can adjust the pulse width of a delayed pulse signal to generate a sampling signal.

[0114] Fig. 20 FIG. 1 is a schematic diagram of a refresh circuit according to an embodiment of the present invention. Fig. 20 As shown, in one embodiment, the refresh circuit further includes a refresh pulse generator 40. The refresh pulse generator 40 is used to receive a refresh instruction; based on the refresh instruction, sequentially generate and output a first refresh pulse and a second refresh pulse, so that each storage array 30 performs a first refresh operation based on the first refresh pulse, and performs a second refresh operation based on the second refresh pulse and the corresponding target address signal; and output the first refresh pulse as a refresh pulse signal to the signal synthesis circuit 10.

[0115] Exemplarily, the first refresh pulse includes a plurality of first refresh pulse sub-signals, and the first first refresh pulse sub-signal may be used as the refresh pulse signal.

[0116] Optionally, the second refresh pulse has a second delay time with the first refresh pulse, so that the time of generating the second refresh pulse is no earlier than the time when the target address signal is last received in each storage array sharing the same address transmission bus, thereby ensuring the refresh operation.

[0117] Fig.21 : is a timing diagram of a refresh pulse of an embodiment, and here, eight storage arrays 30 share one address transmission line 21 as an example for explanation (M=8, in other embodiments, M can be any integer greater than or equal to 2, and is not specifically limited here). Fig.21 As shown, in one embodiment, the first refresh pulse includes four first refresh pulse sub-signals, each of the first refresh pulse sub-signals is in a different time period, and the four first refresh pulse sub-signals are sequentially separated by a third delay time T3, and each first refresh pulse sub-signal corresponds to at least one (two) of the eight storage arrays 30 that share the same address transmission bus 20, and each storage array 30 performs a first refresh operation based on the corresponding first refresh pulse sub-signal.

[0118] Specifically, the first refresh pulse sub-signal 1 corresponds to storage array 1 (bank1) and storage array 5 (bank5), and storage array 1 (bank1) and storage array 5 (bank5) perform a first refresh operation based on the first refresh pulse sub-signal 1; the first refresh pulse sub-signal 2 corresponds to storage array 2 (bank2) and storage array 6 (bank6), and storage array 2 (bank2) and storage array 6 (bank6) perform a first refresh operation based on the first refresh pulse sub-signal 2; the first refresh pulse sub-signal 3 corresponds to storage array 3 (bank3) and storage array 7 (bank7), and storage array 3 (bank3) and storage array 7 (bank7) perform a first refresh operation based on the first refresh pulse sub-signal 3; the first refresh pulse sub-signal 4 corresponds to storage array 4 (bank4) and storage array 8 (bank8), and storage array 4 (bank4) and storage array 8 (bank8) perform a first refresh operation based on the first refresh pulse sub-signal 4.

[0119] Optionally, each target address signal includes an N-bit target address sub-signal, and the N-bit target address sub-signal of the same storage array 30 corresponds to the first refresh pulse sub-signal corresponding to the same storage array 30. Specifically, the N-bit target address sub-signal of storage array 1 (bank1) and storage array 5 (bank5) corresponds to the first refresh pulse sub-signal 1; the N-bit target address sub-signal of storage array 2 (bank2) and storage array 6 (bank6) corresponds to the first refresh pulse sub-signal 2; the N-bit target address sub-signal of storage array 3 (bank3) and storage array 7 (bank7) corresponds to the first refresh pulse sub-signal 3; the N-bit target address sub-signal of storage array 4 (bank4) and storage array 8 (bank8) corresponds to the first refresh pulse sub-signal 4.

[0120] Similarly, the second refresh pulse includes four second refresh pulse sub-signals corresponding to the four first refresh pulse sub-signals one by one, and each second refresh pulse sub-signal has a second delay time T2 with a corresponding first refresh pulse sub-signal. Each second refresh pulse sub-signal is in a different time period, and a plurality of second refresh pulse sub-signals have a third delay time T3 in sequence, and each second refresh pulse sub-signal corresponds to at least one (two) of the eight memory arrays 30 that share the same address transmission bus 20, and each memory array performs a second refresh operation based on the corresponding second refresh pulse sub-signal.

[0121] Specifically, the second refresh pulse sub-signal 1 corresponds to storage array 1 (bank1) and storage array 5 (bank5), and storage array 1 (bank1) and storage array 5 (bank5) perform a second refresh operation based on the second refresh pulse sub-signal 1; the second refresh pulse sub-signal 2 corresponds to storage array 2 (bank2) and storage array 6 (bank6), and storage array 2 (bank2) and storage array 6 (bank6) perform a first refresh operation based on the second refresh pulse sub-signal 2; the second refresh pulse sub-signal 3 corresponds to storage array 3 (bank3) and storage array 7 (bank7), and storage array 3 (bank3) and storage array 7 (bank7) perform a second refresh operation based on the second refresh pulse sub-signal 3; the second refresh pulse sub-signal 4 corresponds to storage array 4 (bank4) and storage array 8 (bank8), and storage array 4 (bank4) and storage array 8 (bank8) perform a second refresh operation based on the second refresh pulse sub-signal 4.

[0122] Combination Fig.17 and Fig.21As shown, the first refresh pulse sub-signal 1 is used as the refresh pulse signal, and a delay operation is performed on the refresh pulse signal to generate 7 intermediate signals with a first delay time T1, and based on the refresh pulse signal and the 7 intermediate signals, 8 corresponding sampling signals (sampling signal 1, sampling signal 2...sampling signal 8) are generated, and the 8 sampling signals are also sequentially spaced by the first delay time T1. The target address signals of the eight storage arrays are sampled in sequence based on the eight sampling signals and then sent to the common address transmission bus 20 for transmission; specifically, firstly, the target address signal of the storage array 1 is sampled based on the sampling signal 1 and then sent to the common address transmission bus 20; after the first first delay time T1, the target address signal of the storage array 2 is sampled based on the sampling signal 2 and then sent to the common address transmission bus 20; and so on; after the fourth first delay time T1 (i.e., time t5), the target address signal of the storage array 5 is sampled based on the sampling signal 5 and then sent to the common address transmission bus 20; and after the eighth first delay time T1 (i.e., time t5), the target address signal of the storage array 8 is sampled based on the sampling signal 8 and then sent to the common address transmission bus 20.

[0123] In addition, the sampling time of the target address signals of the 8 storage arrays by the 8 sampling signals needs to meet certain timing requirements. Therefore, the sampled target address signals need to be sent to the storage array for performing the second refresh operation (which may be a row hammer refresh operation), and the second refresh operation of each storage array is performed based on the corresponding second refresh pulse sub-signal. Therefore, before each second refresh pulse sub-signal is generated, it is necessary to sample the target address signal of the storage array corresponding to the second refresh pulse sub-signal based on the corresponding sampling signal and transmit it to the common address transmission bus 20. For example, for storage array 1 (bank1) and storage array 5 (bank5), Since the same second refresh pulse sub-signal 1 is shared, the same timing sequence needs to be met. Before the second refresh pulse sub-signal 1 is generated (i.e., before the time t_pulse2), the target address signals corresponding to the storage array 1 (bank1) and the storage array 5 (bank5) need to be sampled based on the sampling signal 1 and the sampling signal 5 respectively and then sent to the shared address transmission bus 20, that is, the sampling time of the storage array 5 (bank5) by the sampling signal 5 (i.e., the time t5) is earlier than the time when the second refresh pulse sub-signal 1 is generated (i.e., the time t_pulse2). Since the sampling signal 5 is later than the sampling signal 1, only the sampling time of the sampling signal 5 needs to be paid attention to. Of course, it is also possible to choose to complete the sampling operation of the target address signals of the 8 storage arrays based on the 8 sampling signals before the first second refresh pulse sub-signal 1 is generated (i.e., before the time t_pulse2), that is, the sampling time of the storage array 8 (bank8) by the sampling signal 8 (i.e., the time t8) is earlier than the time when the second refresh pulse sub-signal 1 is generated (i.e., the time t_pulse2).

[0124] In one embodiment, Figure 2 As shown, the storage arrays 30 corresponding to the same first refresh pulse sub-signal are arranged adjacent to each other in pairs, or the storage arrays 30 corresponding to the same first refresh pulse sub-signal are evenly distributed in the corresponding memory.

[0125] In one embodiment, Figure 2 As shown, the storage arrays 30 that share the same address transmission bus 20 are arranged adjacent to each other in the first direction or the second direction, and the first direction and the second direction intersect vertically.

[0126] Fig. 22 is a timing diagram of a refresh pulse of an embodiment, such as Fig. 22As shown, in one embodiment, the refresh circuit includes a signal synthesis circuit 10 and at least two storage arrays 30 sharing the same address transmission bus 20. The signal synthesis circuit 10 is used to receive a refresh pulse signal and a target address signal of each storage array 30 sharing the same address transmission bus 20, synthesize the target address signal of each storage array 30 sharing the same address transmission bus 20 into an address synthesis signal based on the refresh pulse signal, and transmit the address synthesis signal to each storage array 30 through the common address transmission bus 20. Each storage array 30 is used to obtain a corresponding target address signal from the address synthesis signal.

[0127] The signal synthesis circuit 10 includes a sampling signal generation circuit 11 and a synthesis signal output circuit 12. The sampling signal generation circuit 11 is used to receive a refresh pulse signal and generate a plurality of sampling signals based on the refresh pulse signal. The plurality of sampling signals correspond to each storage array 30 sharing the same address transmission bus 20, and the time periods in which the plurality of sampling signals are at an effective level do not overlap. The synthesis signal output circuit 12 is coupled to the sampling signal generation circuit 11, and is used to receive a plurality of sampling signals and target address signals of the storage arrays 30 corresponding to each other, and output the target address signals of the corresponding storage arrays 30 when each sampling signal is at an effective level, so as to merge the target address signals of the plurality of storage arrays 30 sharing the same address transmission bus 20 into an address synthesis signal.

[0128] Each target address signal includes an N-bit target address sub-signal, the address synthesis signal includes an N-bit address synthesis sub-signal, and the address transmission bus 20 includes N address transmission lines 21 corresponding to the N-bit address synthesis sub-signals, where N is a positive integer. The synthesis signal output circuit 12 includes an address selector, and the address selector includes N multiplexers 120 corresponding to the N-bit target address sub-signals. The multiple input terminals of each multiplexer 120 are used to respectively receive a target address sub-signal corresponding to each storage array 30 sharing the same address transmission bus 20, and the multiple control terminals of the multiplexer 120 are used to respectively receive a plurality of sampling signals. The output terminal of the multiplexer 120 is connected to each storage array 30 through a shared address transmission line 21.

[0129] The synthesized signal output circuit 12 further includes a plurality of latch circuits 125, which are connected one-to-one with the multiplexers 120. Each latch circuit 125 is used to enable the multiplexer 120 to keep outputting the currently corresponding target address signal when each sampling signal is at an invalid level.

[0130] Based on the same inventive concept, a memory is also provided, and the memory includes the refresh circuit provided by any of the above embodiments.

[0131] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0132] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0133] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A refresh circuit, characterized in that: The refresh circuit comprises: At least two storage arrays share the same address transmission bus; A signal synthesis circuit, used for receiving a refresh pulse signal and target address signals of the storage arrays sharing the same address transmission bus, merging the target address signals of the storage arrays sharing the same address transmission bus into an address synthesis signal based on the refresh pulse signal, and transmitting the address synthesis signal to the storage arrays through the shared address transmission bus; Each of the storage arrays is used to obtain the corresponding target address signal from the address synthesis signal.

2. The refresh circuit according to claim 1, characterized in that: The signal synthesis circuit comprises: A sampling signal generating circuit, configured to receive a refresh pulse signal and generate a plurality of sampling signals based on the refresh pulse signal, wherein the plurality of sampling signals correspond one-to-one to each of the storage arrays sharing the same address transmission bus, and time periods in which the plurality of sampling signals are at valid levels do not overlap; The synthetic signal output circuit is coupled to the sampling signal generating circuit, and is used to receive the multiple sampling signals and the target address signals of the corresponding storage arrays, and output the corresponding target address signals of the storage array when each of the sampling signals is at a valid level, so as to merge the target address signals of the multiple storage arrays that share the same address transmission bus into an address synthetic signal.

3. The refresh circuit according to claim 2, characterized in that: Each of the target address signals includes an N-bit target address sub-signal, the address synthesis signal includes an N-bit address synthesis sub-signal, the address transmission bus includes N address transmission lines corresponding to the N-bit address synthesis sub-signals, N is a positive integer; the synthesis signal output circuit includes: The address selector comprises N multiplexers corresponding one to one with the N-bit target address sub-signals, the multiple input terminals of each multiplexer are used to respectively receive one-bit target address sub-signal corresponding to each storage array sharing the same address transmission bus, the multiple control terminals of the multiplexer are used to respectively receive the multiple sampling signals, and the output terminals of the multiplexer are connected to each storage array via a shared address transmission line.

4. The refresh circuit according to claim 3, characterized in that: The multiplexer comprises: A plurality of first tri-state inverters corresponding one to each of the storage arrays sharing the same address transmission line; an input terminal of each of the first tri-state inverters is used to receive a target address sub-signal of the corresponding storage array, and a control terminal of each of the first tri-state inverters is used to receive an inverted signal of the corresponding sampling signal; A first NOT gate, wherein the input end of the first NOT gate is respectively connected to the output ends of the plurality of first three-state inverters, and the output end of the first NOT gate is used to output the address synthesis sub-signal.

5. The refresh circuit according to claim 4, characterized in that: The synthesized signal output circuit also includes: The latch circuit is used to enable the multiplexer to keep outputting the currently corresponding target address sub-signal when each of the sampling signals is at an invalid level.

6. The refresh circuit according to claim 5, characterized in that: The latch circuit comprises: An address latch signal generating circuit, used for combining a plurality of the sampling signals to generate an address latch signal; A second three-state inverter, wherein the input end of the second three-state inverter is connected to the output end of the first NOT gate, the control end of the second three-state inverter is used to receive the address latch signal, and the output end of the second three-state inverter is connected to the input end of the first NOT gate.

7. The refresh circuit according to claim 6, characterized in that: The address latch signal generating circuit comprises: At least two first NAND gates, each input end of the at least two first NAND gates is used to receive each of the sampling signals respectively; NOR gate, each input end of the NOR gate is connected to the output ends of the at least two first NAND gates in a one-to-one correspondence, and the output end of the NOR gate is used to output the address latch signal.

8. The refresh circuit according to any one of claims 2 to 7, characterized in that: The sampling signal generating circuit comprises: A delay circuit is used to receive the refresh pulse signal, perform multiple delay processing on the pulse refresh signal to generate multiple intermediate signals, and output the undelayed refresh pulse signal and the multiple intermediate signals together as multiple delayed pulse signals; wherein the multiple delayed pulse signals have a first delay time in sequence; The pulse width adjustment circuit is coupled to the delay circuit, and is used to receive the multiple delayed pulse signals respectively, and adjust the pulse widths of the multiple delayed pulse signals to generate the multiple sampling signals, and the multiple sampling signals also have the first delay time in sequence.

9. The refresh circuit according to claim 8, characterized in that: The pulse width adjustment circuit includes a plurality of pulse width adjustment sub-circuits, each of which includes: A delay device, wherein the input end of the delay device is used to receive a corresponding delayed pulse signal; A second NOT gate, wherein an input end of the second NOT gate is connected to an output end of the delay device; A second NAND gate, wherein the first input terminal of the second NAND gate is connected to the input terminal of the delay device, the second input terminal of the second NAND gate is connected to the output terminal of the second NAND gate, and the output terminal of the second NAND gate is used to output a corresponding sampling signal.

10. The refresh circuit according to any one of claims 1 to 7, characterized in that: The refresh circuit also includes: A refresh pulse generator is used to receive a refresh instruction; based on the refresh instruction, generate and output a first refresh pulse and a second refresh pulse in sequence, so that each of the storage arrays performs a first refresh operation based on the first refresh pulse, and performs a second refresh operation based on the second refresh pulse and the corresponding target address signal; and output the first refresh pulse as the refresh pulse signal to the signal synthesis circuit.

11. The refresh circuit according to claim 10, characterized in that: The second refresh pulse has a second delay time with the first refresh pulse, so that the time of generating the second refresh pulse is not earlier than the time when the target address signal is finally received in each of the storage arrays sharing the same address transmission bus.

12. The refresh circuit according to claim 11, characterized in that: The first refresh pulse includes a plurality of first refresh pulse sub-signals, each of which is in a different time period, and each of which has a third delay time in sequence, each of which corresponds to at least one of the memory arrays sharing the same address transmission bus, and each of which performs a first refresh operation based on the corresponding first refresh pulse sub-signal; The second refresh pulse comprises a plurality of second refresh pulse sub-signals corresponding to the plurality of first refresh pulse sub-signals one by one, and each of the second refresh pulse sub-signals has the second delay time with a corresponding one of the first refresh pulse sub-signals; Each of the second refresh pulse sub-signals is in a different time period, and the third delay time is sequentially provided between multiple second refresh pulse sub-signals. Each of the second refresh pulse sub-signals corresponds to at least one of the storage arrays sharing the same address transmission bus, and each of the storage arrays performs a second refresh operation based on the corresponding second refresh pulse sub-signal.

13. The refresh circuit according to claim 12, characterized in that: The storage arrays corresponding to the same first refresh pulse sub-signal are arranged adjacent to each other in pairs, or the storage arrays corresponding to the same first refresh pulse sub-signal are evenly distributed in the corresponding memory.

14. The refresh circuit according to any one of claims 1 to 7, characterized in that: The storage arrays that share the same address transmission bus are arranged adjacent to each other in a first direction or a second direction, and the first direction and the second direction intersect vertically.

15. A memory, characterized in that: The memory comprises the refresh circuit as claimed in any one of claims 1 to 14.

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