DDR3 self-test circuit based on FPGA in core particle system and method thereof

Abstract

The invention belongs to the technical field of integrated circuits, and particularly relates to a DDR3 self-test circuit based on an FPGA in a core particle system and a method of the DDR3 self-test circuit. Comprising a power supply module, a reset module, a clock module, an FPGA chip, a JTAG downloading module, a PC upper computer and a DDR3 memory. The FPGA chip is respectively connected with the power supply module, the reset module, the clock module, the JTAG downloading module and the DDR3 memory, and the PC upper computer is connected with the JTAG downloading module; wherein the FPGA chip comprises a BIST circuit, a hardware analyzer ILA and a memory interface generator MIG; wherein the BIST circuit is connected with the hardware analyzer ILA and the memory interface generator MIG; the BIST circuit comprises a BIST controller, an address generator, a vector generator, a control signal generator, a comparator and a selector MUX; switching of various test algorithms can be realized through the dynamic test circuit module, so that the flexibility is improved, the test efficiency is improved, and the test cost is reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a DDR3 self-test circuit based on FPGA in a core particle system and a method thereof. Background Art

[0002] With the advancement of semiconductor technology, the market size of the integrated circuit industry continues to expand, and the status of memory chips in the market is getting higher and higher. As the size of transistors continues to shrink and the complexity of circuit structures increases, memory chips are more likely to have many faults during the manufacturing process, such as fixed faults, bridge faults, transmission faults, coupling faults, and address faults. Therefore, the test method of memory chips represented by DDRSDRAM has become an important topic.

[0003] Since there are few I / O pins connected to the outside of DDR SDRAM in the chiplet system, the testing of DDR SDRAM becomes more difficult. However, the difficulty and complexity of testing DDR SDRAM by traditional scanning method are relatively high and the common fault coverage is not high. Therefore, it is necessary to design a DDR3 self-test circuit that can improve flexibility and have high fault coverage. Summary of the invention

[0004] The purpose of the present invention is to overcome the above-mentioned shortcomings of the prior art. The present invention provides a DDR3 self-test circuit and method based on FPGA in a core particle system to solve the problem that the above-mentioned traditional scanning method for testing DDR SDRAM has relatively high difficulty and complexity and low coverage of common faults.

[0005] In order to solve the above technical problems, the present invention provides a DDR3 self-test circuit based on FPGA in a core particle system, comprising: a power module, a reset module, a clock module, an FPGA chip, a JTAG download module, a PC host computer and a DDR3 memory; the FPGA chip is respectively connected to the power module, the reset module, the clock module, the JTAG download module and the DDR3 memory, and the PC host computer is connected to the JTAG download module;

[0006] The FPGA chip includes: a BIST circuit, a hardware analyzer ILA and a memory interface generator MIG; wherein the BIST circuit is interconnected with the hardware analyzer ILA and the memory interface generator MIG;

[0007] The BIST circuit comprises: a BIST controller, an address generator, a vector generator, a control signal generator, a comparator and a selector MUX; wherein the address generator, the vector generator and the control signal generator are respectively connected between the BIST controller and the selector MUX, the selector MUX is respectively connected to the memory interface generator MIG through an IO port and a control signal, the BIST controller is connected to the memory interface generator MIG, and the memory interface generator MIG is connected to the DDR3 memory through a DDR physical interface;

[0008] The BIST circuit receives the algorithm command input by the user end of the PC host computer to complete the test algorithm selection, generate the test vector, address and control signal, transmits the signal generated by the BIST circuit to the DDR3 memory for testing through the memory interface generator MIG, the memory interface generator MIG receives the output data of the DDR3 memory after the test and sends it to the BIST circuit, and the comparator analyzes whether a fault occurs;

[0009] The BIST controller also includes a bist_on signal, a bist_done signal, a bist_error signal, a CLK signal, a RST signal, a Switch signal and an R_time signal which are input respectively, and the bist_on signal is simultaneously input to the selector MUX.

[0010] Preferably, the BIST controller adopts a finite state machine.

[0011] Preferably, the address generator uses an adder to generate a test address and complete the increment and decrement of the address in the test algorithm.

[0012] Preferably, the vector generator provides the vectors required for the test according to the test algorithm.

[0013] Preferably, the comparator compares the vector read from the DDR3 memory with the vector generated by the vector generator to determine whether there is a fault in the DDR3 memory.

[0014] Preferably, the bist_on signal controls the start of the test, the bist_done signal is high indicating that the test is completed, the bist_error is high indicating that a failure occurred during the test, and the R_time signal is used to set the number of read operations. The R_time signal value is reduced by one each time the read operation is repeated until the R_time signal becomes 0 to jump to the next finite state machine.

[0015] Preferably, the user-defined test algorithm is selected through the Switch signal, and the Switch signal adopts a binary Switch[1:0] signal; the test algorithms include: MSCAN, Interconnect, March C+ and Checkerboard algorithms; that is:

[0016] When the highest bit is low, the MSCAN algorithm or the Interconnect algorithm is executed according to the second bit signal of the Switch[1:0] signal; when the second bit signal is low, the MSCAN algorithm is executed, otherwise the Interconnect algorithm is executed;

[0017] When the highest bit signal is at a high level, the March C+ algorithm or the Checkerboard algorithm is executed according to the second bit signal of the Switch[1:0] signal. When the second bit signal is at a low level, the March C+ algorithm is executed, otherwise the Checkerboard algorithm is executed.

[0018] The present invention also provides a DDR3 self-test method based on FPGA in a chiplet system, using a DDR3 self-test circuit based on FPGA in a chiplet system as described above, comprising the following steps:

[0019] Step 1: Build the test platform and initialize the system. First, complete the PCB design of the hardware, build the hardware circuit, power the FPGA chip and the DDR3 memory to be tested, and complete the reset operation of the FPGA chip.

[0020] Step 2: Test circuit loading. On the user side of the PC host computer, use Vivado software to burn the bit stream file of the designed BIST circuit into the FPGA chip through the JTAG download module port, so that the FPGA chip has the function of functional testing of the BIST circuit. The bist_on signal in the BIST circuit is configured by FPGA to control the start of testing the DDR3 memory.

[0021] Step 3: Output data acquisition: The hardware analyzer ILA in the FPGA chip is used to collect the signals that need to be observed during the test;

[0022] Step 4: Result analysis: compare the collected output results with the expected output results to analyze whether the designed BIST circuit can work as expected and whether there is any fault in the DDR3 memory.

[0023] Compared with the prior art, the present invention has the following beneficial effects:

[0024] The present invention improves the controller module of the BIST circuit and proposes a dynamic test circuit module to realize the selection of the algorithm in the built-in self-test circuit, thereby improving flexibility and fault coverage at the same time. The present invention provides a new FPGA-based DDR3 self-test method, which replaces the conventional test method. When the test algorithm needs to be replaced, the proposed test method does not need to reset the BIST circuit, effectively reducing manpower and configuration time, thereby reducing test costs. By integrating multiple data backgrounds in the BIST circuit and realizing the selection of multiple test algorithms, the problem of low fault coverage of a single algorithm can be solved. At the same time, the dynamic test circuit module can realize the switching of multiple test algorithms, thereby improving flexibility, improving test efficiency, and reducing test costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 The present invention provides a structural block diagram of a DDR3 self-test circuit and method based on FPGA in a core particle system.

[0026] Figure 2 It is a flow chart of the steps of a configurable volume accumulation processing method provided by the present invention. Figure 3 The present invention provides a flow chart of a DDR3 self-test method based on FPGA in a core particle system. DETAILED DESCRIPTION

[0027] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0028] like Figure 1 The figure shows a block diagram of the DDR3 self-test hardware test structure. The embodiment of the present invention provides a new DDR3 self-test circuit based on the FPGA in the core-grain system, wherein the circuit is composed of a power supply module, a reset module, a clock module, a JTAG download module, a hardware analyzer ILA, a PC, an FPGA and a DDR3; wherein the PC burns the designed BIST circuit into the FPGA in the core-grain system, and the waveform sampled by the hardware analyzer ILA can be observed and analyzed on the PC; the FPGA is used to design a built-in self-test circuit, generate test vectors, addresses, and control signals, and send stimulus to the DDR3 through the MIG and perform testing.

[0029] The present invention aims at the problem that the difficulty and complexity of testing DDR SDRAM in a traditional scanning mode are relatively high and the common fault coverage is not high. A new DDR3 self-test method based on FPGA in a core particle system is provided. The test method comprises the following steps: a user downloads a designed BIST circuit to FPGA through a JTAG interface on a PC and can analyze the waveform during the test; a BIST circuit module receives an algorithm command input by a user to complete algorithm selection, generates a test vector, an address and a control signal, transmits the signal generated by the BIST circuit to DDR3 for testing through MIG, MIG receives the output data of DDR3 after the test and sends it to the BIST circuit, and a comparison and analysis module in the BIST circuit analyzes whether a fault occurs.

[0030] The present invention implements the BIST circuit and signal transmission function in FPGA. The BIST circuit module includes a test address generator, a test vector generator, a control signal generator, a BIST controller and a comparator, etc. The BIST circuit diagram is shown in FIG. Figure 2 As shown. The BIST controller is mainly implemented in the form of a finite state machine, which can coordinate and control each module. The address generator is used to generate test addresses and complete the increment and decrement of addresses in the test algorithm. It is mainly implemented by an adder. The vector generator provides the vector required for the test according to the test algorithm. The comparator compares the vector read from the memory with the vector generated by the vector generator to determine whether the memory has a fault. The bist_on signal controls the start of the test. When the bist_done signal is high, it indicates that the test is completed. When the bist_error signal is high, it indicates that a fault occurred during the test.

[0031] In the improved dynamic test algorithm module, the custom test algorithm is selected through the Switch signal. The Switch[1:0] signal is used as input. Its state determines the test algorithm that the BIST controller needs to select. The BIST controller (finite state machine) jumps to the corresponding state according to the state of the Switch signal. In each state, the BIST controller generates specific control signals, which are used to indicate which test algorithm the selector MUX selects. The selector MUX receives the control signal of the BIST controller. According to the control signal, the MUX selects one from multiple test algorithms and outputs it to the test circuit. The corresponding relationship is shown in Table 1. When the highest bit is low, the MSCAN test algorithm or the Interconnect algorithm is executed according to the second bit signal of the Switch. When the second bit signal is low, the MSCAN test algorithm is executed, otherwise the Interconnect algorithm is executed. When the highest bit signal is high, the March C+ test algorithm or the Checkerboard algorithm is executed according to the second bit signal of the Switch. When the second bit signal is low, the March C+ test algorithm is executed, otherwise the Checkerboard algorithm is executed. The R_time signal is used to set the number of read operations. Each time the read operation is repeated, the R_time signal value decreases by one until the R_time signal becomes 0 and jumps to the next state machine. Specifically, when Switch[1:0] is 00, the BIST controller jumps to state 0 and generates a control signal to instruct the MUX to select the MSCAN test algorithm for execution. When Switch[1:0] is 01, the BIST controller jumps to state 1 and generates a control signal to instruct the MUX to select the Interconnect test algorithm for execution. When Switch[1:0] is 10 and 11, the BIST controller jumps to state 2 and state 3 respectively, and generates corresponding control signals to instruct the MUX to select the March C+ test algorithm and the Checkerboard test algorithm for execution.

[0032] Table 1

[0033]

[0034] The test process of the embodiment of the present invention is as follows Figure 3As shown in the figure, the test platform and system initialization are built. First, after completing the hardware circuit board PCB design, the hardware circuit is built, the FPGA and the memory to be tested are powered, and the chip is reset. Test circuit loading: On the PC side, the bit stream file of the designed BIST circuit is burned into the FPGA through the JTAG port through the Vivado software, so that the FPGA has the function of functional testing of the BIST circuit. The bist_on signal in the BIST circuit is configured by the FPGA to control the start of the memory test. Output data acquisition: The signals that need to be observed during the test are collected through the hardware analyzer ILA in the FPGA. Result analysis: Compare the collected output results with the expected output results to analyze whether the designed BIST circuit can work as expected and whether there is a fault in DDR3.

[0035] In summary, the present invention uses FPGA resources to design a built-in self-test (BIST) circuit, and transmits the address, data, and control signals generated by the circuit to DDR3 through MIG to complete the test of DDR3. The method improves the controller module of the BIST circuit and proposes a dynamic test circuit module to realize the selection of algorithms in the built-in self-test circuit, thereby improving fault coverage and flexibility.

[0036] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A DDR3 self-test circuit based on FPGA in a chiplet system, characterized in that: include: A power module, a reset module, a clock module, an FPGA chip, a JTAG download module, a PC host computer and a DDR3 memory; the FPGA chip is respectively connected to the power module, the reset module, the clock module, the JTAG download module and the DDR3 memory, and the PC host computer is connected to the JTAG download module; The FPGA chip includes: a BIST circuit, a hardware analyzer ILA and a memory interface generator MIG; wherein the BIST circuit is interconnected with the hardware analyzer ILA and the memory interface generator MIG; The BIST circuit comprises: a BIST controller, an address generator, a vector generator, a control signal generator, a comparator and a selector MUX; wherein the address generator, the vector generator and the control signal generator are respectively connected between the BIST controller and the selector MUX, the selector MUX is respectively connected to the memory interface generator MIG through an IO port and a control signal, the BIST controller is connected to the memory interface generator MIG, and the memory interface generator MIG is connected to the DDR3 memory through a DDR physical interface; The BIST circuit receives the algorithm command input by the user end of the PC host computer to complete the test algorithm selection, generate the test vector, address and control signal, transmits the signal generated by the BIST circuit to the DDR3 memory for testing through the memory interface generator MIG, the memory interface generator MIG receives the output data of the DDR3 memory after the test and sends it to the BIST circuit, and the comparator analyzes whether a fault occurs; The BIST controller also includes a bist_on signal, a bist_done signal, a bist_error signal, a CLK signal, a RST signal, a Switch signal and an R_time signal which are input / output respectively, and the bist_on signal is simultaneously input to the selector MUX.

2. A DDR3 self-test circuit based on FPGA in a chiplet system as claimed in claim 1, characterized in that: The BIST controller adopts a finite state machine.

3. A DDR3 self-test circuit based on FPGA in a chiplet system as claimed in claim 1, characterized in that: The address generator uses an adder to generate a test address and complete the increment and decrement of the address in the test algorithm.

4. A DDR3 self-test circuit based on FPGA in a chiplet system as claimed in claim 1, characterized in that: The vector generator provides vectors required for testing according to a testing algorithm.

5. A DDR3 self-test circuit based on FPGA in a chiplet system as claimed in claim 1, characterized in that: The comparator compares the vector read from the DDR3 memory with the vector generated by the vector generator to determine whether there is a fault in the DDR3 memory.

6. A DDR3 self-test circuit based on FPGA in a chiplet system as claimed in claim 1, characterized in that: The bist_on signal controls the start of the test. When the bist_done signal is high, it indicates that the test is completed. When the bist_error signal is high, it indicates that a fault occurs during the test. The R_time signal is used to set the number of read operations of the finite state machine. Each time the read operation is repeated, the R_time signal value decreases by one until the R_time signal becomes 0 and jumps to the next finite state machine. The CLK signal is provided by the clock module and is used to synchronize the operations inside the BIST controller. The RST signal is used to reset the BIST controller to its initial state.

7. A DDR3 self-test circuit based on FPGA in a chiplet system as claimed in claim 1, characterized in that: The user-defined test algorithm is selected through the Switch signal, and the Switch signal adopts a binary Switch[1:0] signal; the test algorithms include: MSCAN, Interconnect, March C+ and Checkerboard algorithms; that is: When the highest bit is low, the MSCAN algorithm or the Interconnect algorithm is executed according to the second bit signal of the Switch[1:0] signal; when the second bit signal is low, the MSCAN algorithm is executed, otherwise the Interconnect algorithm is executed; When the highest bit signal is at a high level, the March C+ algorithm or the Checkerboard algorithm is executed according to the second bit signal of the Switch[1:0] signal. When the second bit signal is at a low level, the March C+ algorithm is executed, otherwise the Checkerboard algorithm is executed.

8. A DDR3 self-test method based on FPGA in a chiplet system, using a DDR3 self-test circuit based on FPGA in a chiplet system as claimed in any one of claims 1 to 7, characterized in that: The steps include: Step 1: Build the test platform and initialize the system. First, complete the PCB design of the hardware, build the hardware circuit, power the FPGA chip and the DDR3 memory to be tested, and complete the reset operation of the FPGA chip. Step 2: Test circuit loading. On the user side of the PC host computer, use Vivado software to burn the bit stream file of the designed BIST circuit into the FPGA chip through the JTAG download module port, so that the FPGA chip has the function of functional testing of the BIST circuit. The bist_on signal in the BIST circuit is configured by FPGA to control the start of testing the DDR3 memory. Step 3: Output data acquisition: The hardware analyzer ILA in the FPGA chip is used to collect the signals that need to be observed during the test; Step 4: Result analysis: compare the collected output results with the expected output results to analyze whether the designed BIST circuit can work as expected and whether there is any fault in the DDR3 memory.

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