Bootstrap output stage driving circuit, chip and device for direct current motor

Abstract

The invention discloses a bootstrap output stage drive circuit, chip and device for a direct current motor, and the circuit comprises a power supply, a first diode, an undervoltage locking circuit, a detection circuit, a logic circuit, a level conversion circuit, a first drive circuit, a second drive circuit, a first capacitor, a first NMOS tube, a second NMOS tube and a first PMOS tube. The circuit is an improved bootstrap circuit, circuit driving can be achieved without using a charge pump or an oscillator, the problem that in the prior art, a direct current motor driving circuit is large in driving voltage swing can be solved, cost can be reduced, the circuit area can be reduced, circuit power consumption can be reduced, and chip miniaturization can be achieved.

Description

Technical Field

[0001] The present application belongs to the field of electronic products, and in particular, relates to a bootstrap output stage drive circuit, chip and device for a DC motor. Background Art

[0002] In recent years, the application fields of DC motors have become more and more extensive. With the increasing application of electric toys, electric toothbrushes, smart door locks, etc., the market has put forward higher requirements for the small size, low energy consumption, and longer service life of DC motor drive circuits. Based on this demand, reducing the swing amplitude of the internal drive voltage of the DC motor, reducing the use of high-voltage tubes, and simplifying the circuit structure are common solutions.

[0003] In the prior art, a common method is to generate the logic level of the high-side drive by using a charge pump, but this method makes the gate voltage swing amplitude of the MOS tube driving the high-side voltage larger, resulting in a large consumption of energy; in order to cope with this large swing process, more high-voltage tubes have to be used, resulting in a larger circuit area. In order to improve this situation, a bootstrap drive circuit is used, which can make the relative swing amplitude of the signal in most circuits of the high-side drive within a relatively small range, so that the energy consumed is only used for the change within the range of the driving voltage swing, and there is no need to adapt to the huge swing of the output voltage of the power tube. However, the traditional bootstrap drive circuit usually requires an oscillator and an auxiliary charge pump to cooperate with the drive circuit, resulting in the circuit having the problems of high cost, large circuit area, and difficulty in realizing chip miniaturization.

[0004] Therefore, how to solve the problems of large driving voltage swing, high power consumption and cost, large circuit area and difficulty in chip miniaturization in existing DC motor driving circuits is an important issue currently being studied. Summary of the invention

[0005] The main technical problem solved by the present invention is to provide a bootstrap output stage drive circuit, chip and device for a DC motor, which solves the problems existing in the prior art of large drive voltage swing, high power consumption and cost, large circuit area and difficulty in chip miniaturization.

[0006] In order to solve the above technical problems, a technical solution adopted by the present invention is to provide a bootstrap output stage drive circuit, chip and device for a DC motor, wherein the circuit comprises:

[0007] In some embodiments, it includes a power supply, a first diode, an undervoltage lockout circuit, a detection circuit, a logic circuit, a level conversion circuit, a first drive circuit, a second drive circuit, a first capacitor, a first NMOS tube, a second NMOS tube and a first PMOS tube.

[0008] The positive electrode of the power supply is electrically connected to the anode of the first diode, the first connection terminal of the detection circuit, the first connection terminal of the logic circuit and the first connection terminal of the second drive circuit; the negative electrode of the power supply is grounded and is respectively electrically connected to the fourth connection terminal of the detection circuit, the second connection terminal of the logic circuit, the second connection terminal of the second drive circuit and the source of the second NMOS tube.

[0009] The cathode of the first diode is electrically connected to the source of the first PMOS tube, the first connection end of the undervoltage lockout circuit, the first connection end of the level conversion circuit, the first connection end of the first drive circuit and the first connection end of the first capacitor.

[0010] The second connection end of the undervoltage lockout circuit is electrically connected to the gate of the first PMOS tube, and the third connection end of the undervoltage lockout circuit is electrically connected to the second connection end of the level conversion circuit, the second connection end of the first drive circuit, the source of the first NMOS tube, the drain of the second NMOS tube and the second connection end of the first capacitor.

[0011] The source of the first NMOS tube also serves as an output terminal for supplying power to the load.

[0012] The second connection end of the detection circuit is electrically connected to the drain of the first PMOS tube, and the third connection end of the detection circuit is electrically connected to the third connection end of the logic circuit.

[0013] The fourth connection terminal of the logic circuit is electrically connected to the third connection terminal of the second driving circuit, the fifth connection terminal of the logic circuit is used to input a reset signal, and the sixth connection terminal of the logic circuit is electrically connected to the third connection terminal of the level conversion circuit.

[0014] The fourth connection terminal of the level conversion circuit is electrically connected to the third connection terminal of the first driving circuit, the fourth connection terminal of the first driving circuit is electrically connected to the gate of the first NMOS tube, and the drain of the first NMOS tube is connected to the first voltage.

[0015] The fourth connection terminal of the second driving circuit is electrically connected to the gate of the second NMOS tube.

[0016] In some embodiments, the detection circuit includes a third NMOS transistor, a fourth NMOS transistor, a first resistor, and a first NOT gate.

[0017] The first connection end of the first resistor serves as the first connection end of the detection circuit and is electrically connected to the first connection end of the first NOT gate.

[0018] The drain of the third NMOS tube serves as the second connection terminal of the detection circuit and is electrically connected to the gate of the third NMOS tube and the gate of the fourth NMOS tube respectively.

[0019] The source of the third NMOS tube serves as the fourth connection terminal of the detection circuit and is electrically connected to the source of the fourth NMOS tube and the second connection terminal of the first NOT gate respectively.

[0020] The drain of the fourth NMOS tube is electrically connected to the first connection end of the first resistor and the third connection end of the first NOT gate respectively.

[0021] The fourth connection terminal of the first NOT gate serves as the third connection terminal of the detection circuit and is electrically connected to the third connection terminal of the logic circuit.

[0022] In some embodiments, the logic circuit includes a second NOT gate, a third NOT gate, and a first NAND gate.

[0023] The first connection end of the second NOT gate serves as the fifth connection end of the logic circuit; the second connection end of the second NOT gate serves as the sixth connection end of the logic circuit, and is respectively electrically connected to the third connection end of the level conversion circuit and the first connection end of the third NOT gate; the third connection end of the second NOT gate is respectively electrically connected to the third connection end of the third NOT gate and the third connection end of the first NAND gate, and serves as the first connection end of the logic circuit; the fourth connection end of the second NOT gate is respectively electrically connected to the fourth connection end of the third NOT gate and the fourth connection end of the first NAND gate, and serves as the second connection end of the logic circuit.

[0024] The second connection terminal of the third NOT gate is electrically connected to the first connection terminal of the first NAND gate.

[0025] The second connection terminal of the first NAND gate serves as the third connection terminal of the logic circuit and is electrically connected to the third connection terminal of the detection circuit.

[0026] The fifth connection terminal of the first NAND gate serves as the fourth connection terminal of the logic circuit.

[0027] In some embodiments, the first driving circuit includes a first buffer, the first connection end of the first buffer serves as the first connection end of the first driving circuit, the second connection end of the first buffer serves as the second connection end of the first driving circuit, the third connection end of the first buffer serves as the third connection end of the first driving circuit, and the fourth connection end of the first buffer serves as the fourth connection end of the first driving circuit.

[0028] In some embodiments, the second driving circuit includes a second buffer, the first connection end of the second buffer serves as the first connection end of the second driving circuit, the second connection end of the second buffer serves as the second connection end of the second driving circuit, the third connection end of the second buffer serves as the third connection end of the second driving circuit, and the fourth connection end of the second buffer serves as the fourth connection end of the second driving circuit.

[0029] In some embodiments, the under-voltage lockout circuit includes a second resistor, a third resistor, a first amplifier, a second amplifier, a second NAND gate, a third NAND gate, and a fourth NOT gate.

[0030] The first connection end of the second resistor is connected to the second voltage, the second connection end of the second resistor is electrically connected to the first connection end of the third resistor, the inverting input end of the first amplifier and the non-inverting input end of the second amplifier respectively, and the second connection end of the third resistor is grounded.

[0031] The in-phase input terminal of the first amplifier serves as the first connection terminal of the undervoltage lockout circuit; the output terminal of the first amplifier is electrically connected to the first connection terminal of the second NAND gate.

[0032] The second connection end of the second NAND gate is electrically connected to the output end of the third NAND gate; the third connection end of the second NAND gate is electrically connected to the first connection end of the third NAND gate and the first connection end of the fourth NAND gate respectively, and the second connection end of the fourth NAND gate serves as the second connection end of the undervoltage lockout circuit.

[0033] The inverting input terminal of the second amplifier serves as the third connection terminal of the undervoltage lockout circuit, and the output terminal of the second amplifier is electrically connected to the second connection terminal of the third NAND gate.

[0034] In some embodiments, the level conversion circuit includes a fourth resistor, a second PMOS transistor, and a fifth NMOS transistor.

[0035] The first connection end of the fourth resistor serves as the first connection end of the level conversion circuit, and the second connection end of the fourth resistor is electrically connected to the source of the second PMOS tube and also serves as the fourth connection end of the level conversion circuit.

[0036] The gate of the second PMOS tube serves as the second connection terminal of the level conversion circuit, and the drain of the second PMOS tube is electrically connected to the drain of the fifth NMOS tube.

[0037] The source of the fifth NMOS tube is grounded, and the gate of the fifth NMOS tube serves as the third connection terminal of the level conversion circuit.

[0038] In some embodiments, the logic circuit includes a fifth NOT gate, a third buffer, and a fourth NAND gate.

[0039] The first connection terminal of the fifth NOT gate is electrically connected to the first connection terminal of the third buffer and serves as the fifth connection terminal of the logic circuit.

[0040] The second connection terminal of the fifth NOT gate serves as the sixth connection terminal of the logic circuit and is electrically connected to the third connection terminal of the level conversion circuit.

[0041] The second connection terminal of the third buffer is electrically connected to the first connection terminal of the fourth NAND gate.

[0042] The third connection terminal of the third buffer is electrically connected to the third connection terminal of the fourth NAND gate respectively and serves as the first connection terminal of the logic circuit.

[0043] The fourth connection terminal of the third buffer is electrically connected to the fourth connection terminal of the fourth NAND gate and serves as the second connection terminal of the logic circuit.

[0044] The second connection terminal of the fourth NAND gate serves as the third connection terminal of the logic circuit and is electrically connected to the third connection terminal of the detection circuit.

[0045] The fifth connection terminal of the fourth NAND gate serves as the fourth connection terminal of the logic circuit.

[0046] In order to solve the above technical problems, the present application also provides a bootstrap output stage driver chip for a DC motor, including any one of the above bootstrap output stage driver circuits for a DC motor.

[0047] In order to solve the above technical problems, the present application also provides a bootstrap output stage driving device for a DC motor, including the above bootstrap output stage driving chip for a DC motor.

[0048] Beneficial effects: The present application discloses a bootstrap output stage drive circuit, chip and device for a DC motor, wherein the circuit includes: a power supply, a first diode, an undervoltage lockout circuit, a detection circuit, a logic circuit, a level conversion circuit, a first drive circuit, a second drive circuit, a first capacitor, a first NMOS transistor, a second NMOS transistor and a first PMOS transistor. The circuit of the present application is an improved bootstrap circuit, which can realize circuit driving without using a charge pump or an oscillator, and can not only solve the problem of large driving voltage swing in the DC motor drive circuit in the prior art, but also reduce costs, circuit area, circuit power consumption, and realize chip miniaturization. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 A circuit diagram of an embodiment of a bootstrap output stage drive circuit for a DC motor of the present application is provided;

[0050] Figure 2 The timing diagram of the circuit of this application is given;

[0051] Figure 3 A circuit diagram of an embodiment of a detection circuit in the present application is provided;

[0052] Figure 4 A circuit diagram of an embodiment of a logic circuit in the present application is provided;

[0053] Figure 5 A circuit diagram of another embodiment of the logic circuit in the present application is provided;

[0054] Figure 6 A circuit diagram of an embodiment of a first driving circuit in the present application is provided;

[0055] Figure 7 A circuit diagram of an embodiment of a second driving circuit in the present application is provided;

[0056] Figure 8 A circuit diagram of an undervoltage lockout circuit in an embodiment of the present application is provided;

[0057] Fig. 9 A circuit diagram of an embodiment of a level conversion circuit in the present application is provided. DETAILED DESCRIPTION

[0058] In order to facilitate the understanding of the present invention, the present invention is described in more detail below in conjunction with the accompanying drawings and specific embodiments. Preferred embodiments of the present invention are provided in the accompanying drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described in this specification. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0059] It should be noted that, unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used in this specification includes any and all combinations of one or more related listed items.

[0060] Figure 1 A circuit diagram of a bootstrap output stage drive circuit for a DC motor of the present application is given. Figure 1 The circuit includes: a power supply 100, a first diode 110, an under-voltage lockout circuit 101, a detection circuit 104, a logic circuit 105, a level conversion circuit 102, a first drive circuit 103, a second drive circuit 106, a first capacitor 109, a first NMOS tube 107, a second NMOS tube 108, and a first PMOS tube 111.

[0061] The positive electrode of the power supply 100 is electrically connected to the anode of the first diode 110, the first connection terminal of the detection circuit 104, the first connection terminal of the logic circuit 105, and the first connection terminal of the second drive circuit 106; the negative electrode of the power supply 100 is grounded and is electrically connected to the fourth connection terminal of the detection circuit 104, the second connection terminal of the logic circuit 105, the second connection terminal of the second drive circuit 106, and the source of the second NMOS tube 108.

[0062] The cathode of the first diode 110 is electrically connected to the source of the first PMOS transistor 111 , the first connection end of the undervoltage lockout circuit 101 , the first connection end of the level conversion circuit 102 , the first connection end of the first driving circuit 103 and the first connection end of the first capacitor 109 .

[0063] The second connection end of the under-voltage lockout circuit 101 is electrically connected to the gate of the first PMOS tube 111, and the third connection end of the under-voltage lockout circuit 101 is electrically connected to the second connection end of the level conversion circuit 102, the second connection end of the first drive circuit 103, the source of the first NMOS tube 107, the drain of the second NMOS tube 108 and the second connection end of the first capacitor 109 respectively.

[0064] The source of the first NMOS tube 107 also serves as an output end for powering a load (for example, a DC motor); the second connection end of the detection circuit 104 is electrically connected to the drain of the first PMOS tube 111, and the third connection end of the detection circuit 104 is electrically connected to the third connection end of the logic circuit 105; the fourth connection end of the logic circuit 105 is electrically connected to the third connection end of the second drive circuit 106, and the fifth connection end of the logic circuit 105 is used to input a reset signal, and the sixth connection end of the logic circuit 105 is electrically connected to the third connection end of the level conversion circuit 102.

[0065] The fourth connection terminal of the level conversion circuit 102 is electrically connected to the third connection terminal of the first drive circuit 103, the fourth connection terminal of the first drive circuit 103 is electrically connected to the gate of the first NMOS tube 107, the drain of the first NMOS tube 107 is connected to the first voltage, the first voltage is the power supply voltage, and is used to power the load; the fourth connection terminal of the second drive circuit 106 is electrically connected to the gate of the second NMOS tube 108.

[0066] Specific, combined Figure 2 To explain, Figure 2 IN represents the reset signal input by the logic circuit 105, and also represents the start signal input from outside the circuit; UVLO represents the signal output by the undervoltage lockout circuit 101, which is used to control the on and off of the first PMOS tube 111; Vc represents the voltage across the first capacitor 109, AH represents the high voltage threshold, and VL represents the low voltage threshold; t0, t1, T+t0, T+t1 represent different moments respectively, and T represents the oscillation period.

[0067] Specifically, when the reset signal IN is at a low level, it indicates that there is no input signal to the circuit, the undervoltage lockout circuit 101 outputs a high voltage, that is, UVLO is at a high level, the first PMOS tube 111 is turned off, and the circuit is in a shutdown state, and the voltage Vc across the first capacitor 109 is 0. At time t0, the reset signal IN changes from a low level to a high level, indicating that the circuit starts to work, but since the circuit is still in a low voltage state, the undervoltage lockout circuit 101 still outputs a high level, that is, UVLO is at a high level, the first PMOS tube 111 is turned off, the detection circuit 104 outputs a low level, the logic circuit 105 outputs a high level to the second drive circuit 106, and the second drive circuit 106 controls the second NMOS tube 108 to turn on; the logic circuit 105 outputs a low level to the level conversion circuit 102, and at this time, the first drive circuit 103 controls the first NMOS tube 107 to turn off, and at this time, the power supply 100 starts to charge the first capacitor 109.

[0068] Further, when the circuit is operating normally, the undervoltage lockout circuit 101 outputs a low level, the first PMOS tube 111 is turned on, the detection circuit 104 outputs a high level, the logic circuit 105 outputs a low level to the second drive circuit 106, and the second drive circuit 106 outputs a low level to control the second NMOS tube 108 to be turned off; the logic circuit 105 outputs a high level to the level conversion circuit 102, and at this time the first drive circuit 103 controls the first NMOS tube 107 to be turned on, and at this time the voltage at the second connection end of the first capacitor 109 increases. Since the voltage across the capacitor cannot change suddenly, the voltage at the first connection end of the first capacitor 109 also increases accordingly. At time t1, when the voltage Vc across the first capacitor 109 reaches the high voltage threshold VH, the first capacitor 109 starts to discharge, and supplies power to the undervoltage lockout circuit 101, the level conversion circuit and the first drive circuit 103. The first diode 110 can play a role of cutting off to prevent the first capacitor 109 from reversely charging the power supply 100. During the discharge of the first capacitor 109, the voltage across the first capacitor 109 continues to decrease.

[0069] Further, at time T+t0, when the voltage Vc across the first capacitor 109 drops to the low voltage threshold VL, the undervoltage lockout circuit 101 outputs a high level, the first PMOS tube 111 is turned off, the detection circuit 104 outputs a low level, the logic circuit 105 outputs a high level to the second drive circuit 106, and the second drive circuit 106 controls the second NMOS tube 108 to turn on; the logic circuit 105 outputs a low level to the level conversion circuit 102, and at this time, the first drive circuit 103 outputs a low level to control the first NMOS tube 107 to turn off. Since the second connection end of the first capacitor 109 is grounded, the first connection end of the first capacitor 109 is lower than the voltage of the power supply 100, and the power supply 100 charges the first capacitor 109. In this way, the circuit enters the normal working mode, forming an adaptive circuit with an oscillation period of T.

[0070] The circuit of the present application eliminates the use of an oscillator and forms an adaptive periodic signal. This adaptation is achieved based on the gap between the high-voltage threshold and the low-voltage threshold. The frequency of the periodic signal can be adjusted by adjusting the gap between the two. The discharge speed of the first capacitor 109 depends entirely on the size of the leakage current of the first NMOS tube 107. Therefore, it can be well adapted to the continuous steady-state drive of the DC brushed motor, so that the time occupied by charging is a smaller proportion in an oscillation cycle, and the impact on the final drive current is smaller. Since the circuit of the present application does not need to use a charge pump, the use of high-voltage tubes is correspondingly reduced, thereby reducing costs and circuit area; and the circuit of the present application is an improved bootstrap circuit, which can make the driving circuit work without using a charge pump and an oscillator, so that the circuit can achieve an adaptive oscillation period, further saving costs and power consumption, and realizing chip miniaturization; in addition, since the swing range of the driving voltage of the present application depends on the gap between the high-voltage threshold and the low-voltage threshold, and the driving voltage swing range in the prior art is 0~Vm, Vm is the power supply voltage, and the voltage value of the power supply voltage may be tens of volts or even larger, and the swing range is large, so the present application can also solve the problem of large driving voltage swing in the prior art.

[0071] In some embodiments, in combination Figure 1 and Figure 3 The detection circuit 104 includes a third NMOS transistor 1040 , a fourth NMOS transistor 1042 , a first resistor 1041 and a first NOT gate 1043 .

[0072] The first connection end of the first resistor 1041 serves as the first connection end 1044 of the detection circuit 104 and is electrically connected to the first connection end of the first NOT gate 1043 .

[0073] The drain of the third NMOS transistor 1040 serves as the second connection terminal 1047 of the detection circuit 104 and is electrically connected to the gate of the third NMOS transistor 1040 and the gate of the fourth NMOS transistor 1042 .

[0074] The source of the third NMOS transistor 1040 serves as the fourth connection terminal 1046 of the detection circuit 104 and is electrically connected to the source of the fourth NMOS transistor 1042 and the second connection terminal of the first NOT gate 1043 .

[0075] The drain of the fourth NMOS tube 1042 is electrically connected to the first connection terminal of the first resistor 1041 and the third connection terminal of the first NOT gate 1043 respectively; the fourth connection terminal of the first NOT gate 1043 serves as the third connection terminal 1045 of the detection circuit 104 and is electrically connected to the third connection terminal of the logic circuit 105.

[0076] Specifically, since the first connection terminal 1044 of the detection circuit 104 is electrically connected to the positive electrode of the power supply 100, the first connection terminal of the detection circuit 104 is connected to the power supply voltage and is at a high level; the second connection terminal 1047 of the detection circuit 104 is electrically connected to the drain of the first PMOS tube 111, the drain and gate of the third NMOS tube 1040 and the gate of the fourth NMOS tube 1042 are connected together and serve as the second connection terminal 1047 of the detection circuit 104, so the conduction and shutdown of the first PMOS tube 111 affect the level of the input of the second connection terminal 1047 of the detection circuit 104.

[0077] When the first PMOS tube 111 is turned on, the second connection terminal 1047 of the detection circuit 104 inputs a high level, the third NMOS tube 1040 and the fourth NMOS tube 1042 are both turned on, the third connection terminal (i.e., the input terminal) of the first NOT gate 1043 inputs a low level due to grounding, and outputs a high level through the first NOT gate 1043, and the fourth connection terminal (i.e., the output terminal) of the first NOT gate 1043 serves as the third connection terminal 1045 of the detection circuit 104, so the detection circuit 104 outputs a high level to the logic circuit 105; when the first PMOS tube 111 is turned off, the second connection terminal 1047 of the detection circuit 104 inputs a low level, the third NMOS tube 1040 and the fourth NMOS tube 1042 are both turned off, and the third connection terminal (i.e., the input terminal) of the first NOT gate 1043 is connected to the power supply 100 through the first resistor 1041, so a high level is input, and a low level is output through the first NOT gate 1043, so the detection circuit 104 outputs a low level to the logic circuit 105. Therefore, the detection circuit 104 is used to detect whether there is a voltage input. When a voltage is input to the detection circuit 104 (that is, when a high level is input to the detection circuit 104), the detection circuit 104 outputs a high level to the logic circuit 105; otherwise, a low level is output; the level output by the detection circuit 104 to the logic circuit 105 depends on the conduction and shutdown of the first PMOS tube 111.

[0078] In some embodiments, in combination Figure 1 and Figure 4 , the logic circuit 105 includes a second NOT gate 1050 , a third NOT gate 1051 and a first NAND gate 1052 .

[0079] The first connection terminal of the second NOT gate 1050 serves as the fifth connection terminal 1058 of the logic circuit 105 for inputting a reset signal; the second connection terminal of the second NOT gate 1050 serves as the sixth connection terminal 1053 of the logic circuit 105 and is electrically connected to the third connection terminal of the level conversion circuit 102 and the first connection terminal of the third NOT gate 1051, respectively; the third connection terminal of the second NOT gate 1050 is electrically connected to the third connection terminal of the third NOT gate 1051 and the third connection terminal of the first NAND gate 1052, respectively, and serves as the first connection terminal 1055 of the logic circuit 105 for connecting to the positive electrode of the power supply 100; the fourth connection terminal of the second NOT gate 1050 is electrically connected to the fourth connection terminal of the third NOT gate 1051 and the fourth connection terminal of the first NAND gate 1052, respectively, and serves as the second connection terminal 1057 of the logic circuit 105 for connecting to the negative electrode of the power supply 100, i.e., grounding.

[0080] The second connection terminal of the third NOT gate 1051 is electrically connected to the first connection terminal of the first NAND gate 1052; the second connection terminal of the first NAND gate 1052 serves as the third connection terminal 1054 of the logic circuit 105 and is electrically connected to the third connection terminal of the detection circuit 104; the fifth connection terminal of the first NAND gate 1052 serves as the fourth connection terminal 1056 of the logic circuit 105 and is used to connect to the third connection terminal of the second drive circuit 106.

[0081] Specifically, since the first connection terminal of the second NOT gate 1050 serves as the fifth connection terminal 1058 of the logic circuit 105 and is used to input the reset signal IN; and the second connection terminal of the second NOT gate 1050 serves as the sixth connection terminal 1053 of the logic circuit 105 and is electrically connected to the third connection terminal of the level conversion circuit 102, the reset signal IN is inverted by the second NOT gate 1050 and output to the level conversion circuit 102.

[0082] Specifically, when the reset signal IN is at a low level, the second NOT gate 1050 outputs a high level to the level conversion circuit 102 and the third NOT gate 1051; the third NOT gate 1051 inverts the input high level and outputs a low level to the first NAND gate 1052. At this time, no matter whether the signal input by the third connection terminal 1054 of the logic circuit 105 (i.e., the signal input by the detection circuit 104) is a high level or a low level, after the first NAND gate 1052 performs a NAND logic operation, it outputs a high level to the second drive circuit 106.

[0083] Furthermore, when the reset signal IN is at a high level, the second NOT gate 1050 outputs a low level to the level conversion circuit 102 and the third NOT gate 1051; the third NOT gate 1051 inverts the input low level and outputs a high level to the first NAND gate 1052. If the signal input by the third connection terminal 1054 of the logic circuit 105 (i.e., the signal input by the detection circuit 104) is at a high level, after the first NAND gate 1052 performs a NAND logic operation, a low level is output to the second drive circuit 106; if the signal input by the third connection terminal 1054 of the logic circuit 105 (i.e., the signal input by the detection circuit 104) is at a low level, after the first NAND gate 1052 performs a NAND logic operation, a high level is output to the second drive circuit 106. Therefore, the logic circuit 105 performs logic operations according to the input reset signal IN and the signal input by the detection circuit 104, and outputs different logic signals to the level conversion circuit 102 and the second driving circuit 106, respectively, so that the first NMOS transistor 107 and the second NMOS transistor 108 are in different working states, thereby affecting the charging and discharging state of the first capacitor 109 when the entire circuit is working.

[0084] In some embodiments, in combination Figure 1 and Figure 5 , the logic circuit 105 includes a fifth NOT gate 1500 , a third buffer 1510 , and a fourth NAND gate 1511 .

[0085] The first connection end of the fifth NOT gate 1500 is electrically connected to the first connection end of the third buffer 1510, and serves as the fifth connection end 1058 of the logic circuit 105, for inputting a reset signal; the second connection end of the fifth NOT gate 1500 serves as the sixth connection end 1053 of the logic circuit 105, and is electrically connected to the third connection end of the level conversion circuit 102; the second connection end of the third buffer 1510 is electrically connected to the first connection end of the fourth NAND gate 1511; the third connection end of the third buffer 1510 is electrically connected to the third connection end of the fourth NAND gate 1511, and serves as the first connection end of the logic circuit 105. The connection terminal 1055 is used to connect the positive electrode of the power supply 100; the fourth connection terminal of the third buffer 1510 is electrically connected to the fourth connection terminal of the fourth NAND gate 1511, and serves as the second connection terminal 1057 of the logic circuit 105, which is used to connect the negative electrode of the power supply 100, that is, ground; the second connection terminal of the fourth NAND gate 1511 serves as the third connection terminal 1054 of the logic circuit 105, and is electrically connected to the third connection terminal of the detection circuit 104; the fifth connection terminal of the fourth NAND gate 1511 serves as the fourth connection terminal 1056 of the logic circuit 105, which is used to connect the third connection terminal of the second drive circuit 106.

[0086] Specifically, since the first connection terminal of the fifth NOT gate 1500 is electrically connected to the first connection terminal of the third buffer 1510, they together serve as the fifth connection terminal 1058 of the logic circuit 105, which is used to input the reset signal IN; and the second connection terminal of the fifth NOT gate 1500 serves as the sixth connection terminal 1053 of the logic circuit 105, which is electrically connected to the third connection terminal of the level conversion circuit 102; therefore, the reset signal IN is inverted by the fifth NOT gate 1500 and output to the level conversion circuit 102.

[0087] Specifically, when the reset signal IN is at a low level, the fifth NOT gate 1500 outputs a high level to the level conversion circuit 102 and the third buffer 1510; the third buffer 1510 outputs the input low level to the fourth NAND gate 1511. At this time, no matter whether the signal input by the third connection terminal 1054 of the logic circuit 105 (that is, the signal input by the detection circuit 104) is a high level or a low level, after the fourth NAND gate 1511 performs a NAND logic operation, a high level is output to the third connection terminal of the second drive circuit 106.

[0088] Furthermore, when the reset signal IN is at a high level, the fifth NOT gate 1500 outputs a low level to the level conversion circuit 102 and the third buffer 1510; the third buffer 1510 outputs the input high level to the fourth NAND gate 1511. If the signal input by the third connection terminal 1054 of the logic circuit 105 (i.e., the signal input by the detection circuit 104) is at a high level, after the fourth NAND gate 1511 performs a NAND logic operation, a low level is output to the second drive circuit 106; if the signal input by the third connection terminal 1054 of the logic circuit 105 (i.e., the signal input by the detection circuit 104) is at a low level, after the fourth NAND gate 1511 performs a NAND logic operation, a high level is output to the second drive circuit.

[0089] In some embodiments, in combination Figure 1 and Figure 6 The first driving circuit 103 includes a first buffer 1030, a first connection end of the first buffer 1030 serves as a first connection end 1031 of the first driving circuit 103, a second connection end of the first buffer 1030 serves as a second connection end 1033 of the first driving circuit 103, a third connection end of the first buffer 1030 serves as a third connection end 1034 of the first driving circuit 103, and a fourth connection end of the first buffer 1030 serves as a fourth connection end 1032 of the first driving circuit 103.

[0090] Specifically, the third connection terminal 1034 of the first driving circuit 103 is electrically connected to the fourth connection terminal of the level conversion circuit 102, and is used to input the signal output by the level conversion circuit 102; the fourth connection terminal 1032 of the first driving circuit 103 is electrically connected to the gate of the first NMOS tube 107, and is used to output the driving signal to the first NMOS tube 107. The first buffer 1030 can improve the driving capability of the driving signal and will not change the logical values ​​of the input signal and the output signal, that is, the input signal is the same as the output signal.

[0091] In some embodiments, in combination Figure 1 and Figure 7 The second driving circuit 106 includes a second buffer 1060, a first connection end of the second buffer 1060 serves as a first connection end 1061 of the second driving circuit 106, a second connection end of the second buffer 1060 serves as a second connection end 1063 of the second driving circuit 106, a third connection end of the second buffer 1060 serves as a third connection end 1064 of the second driving circuit 106, and a fourth connection end of the second buffer 1060 serves as a fourth connection end 1062 of the second driving circuit 106.

[0092] Specifically, the third connection terminal 1064 of the second driving circuit 106 is electrically connected to the fourth connection terminal of the logic circuit 105, and is used to input the signal output by the logic circuit 105; the fourth connection terminal 1062 of the second driving circuit 106 is electrically connected to the gate of the second NMOS tube 108, and is used to output the driving signal to the second NMOS tube 108. The second buffer 1060 can improve the driving capability of the driving signal and will not change the logical values ​​of the input signal and the output signal, that is, the input signal is the same as the output signal.

[0093] In some embodiments, in combination Figure 1 and Figure 8 The undervoltage lockout circuit 101 includes a second resistor 1010, a third resistor 1011, a first amplifier 1012, a second amplifier 1013, a second NAND gate 1014, a third NAND gate 1015, and a fourth NAND gate 1016. The undervoltage lockout circuit 101 is used to detect the voltage of the circuit and output a control signal to control the on and off of the first PMOS tube 111; when the circuit voltage is low, the undervoltage lockout circuit 101 outputs a high level to turn off the first PMOS tube 111, thereby reducing the current consumption of the circuit.

[0094] The first connection end of the second resistor 1010 is connected to the second voltage, and the second connection end of the second resistor 1010 is electrically connected to the first connection end of the third resistor 1011, the inverting input end of the first amplifier 1012 and the non-inverting input end of the second amplifier 1013 respectively, and the second connection end of the third resistor 1011 is grounded; the non-inverting input end of the first amplifier 1012 serves as the first connection end 1018 of the under-voltage lockout circuit 101; the output end of the first amplifier 1012 is electrically connected to the first connection end of the second NAND gate 1014.

[0095] The second connection end of the second NAND gate 1014 is electrically connected to the output end of the third NAND gate 1015; the third connection end (i.e., the output end) of the second NAND gate 1014 is electrically connected to the first connection end of the third NAND gate 1015 and the first connection end of the fourth NAND gate 1016, respectively, and the second connection end of the fourth NAND gate 1016 serves as the second connection end 1017 of the under-voltage lockout circuit 101; the inverting input end of the second amplifier 1013 serves as the third connection end 1019 of the under-voltage lockout circuit 101, and the output end of the second amplifier 1013 is electrically connected to the second connection end of the third NAND gate 1015.

[0096] Specifically, the second voltage connected to the first connection end of the second resistor 1010 is the voltage Vc across the first capacitor 109. When the circuit does not start working, since the voltage across the first capacitor 109 is 0, the inputs of the inverting input end of the first amplifier 1012 and the non-inverting input end of the second amplifier 1013 are both 0; the non-inverting input end of the first amplifier 1012 is electrically connected to the positive electrode of the power supply 100 through the first diode 110, so the output of the first amplifier 1012 is high level, and the output of the second amplifier 1013 is low level. At this time, the third NAND gate 1015 performs a NAND logic and outputs a high level to the other input end of the second NAND gate 1014, and the second NAND gate 1014 performs a NAND logic and outputs a low level to the fourth NAND gate 1016. The fourth NAND gate 1016 inverts the input low level and outputs a high level, so that the first PMOS tube 111 is turned off, and the circuit is in a shutdown protection state.

[0097] When the circuit starts to work at the beginning, since the first capacitor 109 is in a charging state, the voltage across the first capacitor 109 continues to increase, so the voltage input to the inverting input terminal of the first amplifier 1012 and the non-inverting input terminal of the second amplifier 1013 also continues to increase. However, since it is in the initial charging stage, the voltage difference between the non-inverting input terminal and the inverting input terminal of the first amplifier 1012 is still large, so the first amplifier 1012 outputs a high voltage; the voltage difference between the non-inverting input terminal and the inverting input terminal of the second amplifier 1013 is not much, so the output of the second amplifier 1013 is a low level. At this time, the third NAND gate 1015 performs a NAND logic and outputs a high level to the other input terminal of the second NAND gate 1014. The second NAND gate 1014 performs a NAND logic and outputs a low level to the fourth NAND gate 1016. The fourth NAND gate 1016 inverts the input low level and outputs a high level, so that the first PMOS tube 111 is turned off.

[0098] When the voltage across the first capacitor 109 reaches the high voltage threshold value VH, the voltage input to the inverting input terminal of the first amplifier 1012 and the non-inverting input terminal of the second amplifier 1013 is also high, and the voltage input to the non-inverting input terminal of the first amplifier 1012 is not much different from the voltage input to the inverting input terminal, so the first amplifier 1012 outputs a low voltage; at this time, the second NAND gate 1014 performs a NAND logic and outputs a high level to the fourth NOT gate 1016, and the fourth NOT gate 1016 inverts the input high level and outputs a low level, so that the first PMOS tube 111 is turned on, and the circuit is in a stable working state.

[0099] As the first capacitor 109 is discharged, the voltage across the first capacitor 109 is continuously reduced. When the voltage is as low as the low voltage threshold VL, the voltages inputted to the in-phase input terminal and the inverting input terminal of the first amplifier 1012 differ greatly, so the first amplifier 1012 outputs a high level to one input terminal of the second NAND gate 1014; the voltages inputted to the in-phase input terminal and the inverting input terminal of the second amplifier 1013 differ little, so the output of the second amplifier 1013 is a low level. At this time, the third NAND gate 1015 performs a NAND logic and outputs a high level to the other input terminal of the second NAND gate 1014; the second NAND gate 1014 performs a NAND logic and outputs a low level to the fourth NAND gate 1016. The fourth NAND gate 1016 inverts the input low level and outputs a high level, so that the first PMOS tube 111 is turned off. Therefore, when the circuit voltage is low, the undervoltage lockout circuit 101 outputs a high level, and the first PMOS tube 111 is turned off, thereby reducing the current consumption of the circuit.

[0100] In some embodiments, in combination Figure 1 and Fig. 9The level conversion circuit 102 includes a fourth resistor 1021, a second PMOS transistor 1022 and a fifth NMOS transistor 1023; the first connection end of the fourth resistor 1021 serves as the first connection end 1024 of the level conversion circuit 102, and the second connection end of the fourth resistor 1021 is electrically connected to the source of the second PMOS transistor 1022 and also serves as the fourth connection end 1027 of the level conversion circuit 102.

[0101] The gate of the second PMOS transistor 1022 serves as the second connection terminal 1025 of the level conversion circuit 102 , and the drain of the second PMOS transistor 1022 is electrically connected to the drain of the fifth NMOS transistor 1023 ; the source of the fifth NMOS transistor 1023 is grounded, and the gate of the fifth NMOS transistor 1023 serves as the third connection terminal 1026 of the level conversion circuit 102 .

[0102] Specifically, the third connection terminal 1026 of the level conversion circuit 102 is electrically connected to the sixth connection terminal of the logic circuit 105, and is used to input the signal input by the logic circuit 105; the fourth connection terminal 1027 of the level conversion circuit 102 is electrically connected to the third connection terminal of the first drive circuit 103, and is used to output the signal to the first drive circuit 103; the first connection terminal 1024 of the level conversion circuit 102 is electrically connected to the positive electrode of the power supply 100 through the first diode 110, and is also electrically connected to the first connection terminal of the first capacitor 109; the second connection terminal 1025 of the level conversion circuit 102 is electrically connected to the drain of the second NMOS tube 108 and the second connection terminal of the first capacitor 109 respectively.

[0103] Specifically, when the logic circuit 105 inputs a low level to the level conversion circuit 102, the fifth NMOS tube 1023 is turned off, the second NMOS tube 108 is turned on, and the second connection end of the first capacitor 109 is grounded, that is, the second connection end 1025 of the level conversion circuit 102 is a low voltage, and the second PMOS tube 1022 is turned on. At this time, the fourth connection end 1027 of the level conversion circuit 102 is grounded through the second PMOS tube 1022 and the fifth NMOS tube 1023, so the fourth connection end 1027 of the level conversion circuit 102 outputs a low voltage to the first drive circuit 103.

[0104] Further, when the logic circuit 105 inputs a high level to the level conversion circuit 102, the fifth NMOS tube 1023 is turned on, and the second NMOS tube 108 is turned off. At this time, the second PMOS tube 1022 is turned off, and the fourth connection terminal 1027 of the level conversion circuit 102 outputs a high voltage to the first drive circuit 103. Therefore, the level of the voltage input to the level conversion circuit 102 is related to the level of the output voltage, and the voltage input by the logic circuit 105 can be converted into a suitable voltage to the first drive circuit 103 through the fourth resistor 1021. Therefore, the level conversion circuit is used for voltage conversion.

[0105] The above description of various embodiments tends to emphasize the differences between the various embodiments. The same or similar aspects can be referenced to each other, and for the sake of brevity, they will not be repeated herein.

[0106] Based on the same inventive concept, the present application also provides a bootstrap output stage driver chip for a DC motor, including any one of the above-mentioned bootstrap output stage driver circuits for a DC motor.

[0107] The circuit composition inside the chip has been described with reference to the above-mentioned embodiments and will not be described in detail here.

[0108] Based on the same inventive concept, the present application also provides a bootstrap output stage driving device for a DC motor, including the above-mentioned bootstrap output stage driving chip for a DC motor.

[0109] In summary, the present application discloses a bootstrap output stage drive circuit, chip and device for a DC motor, wherein the circuit includes: a power supply, a first diode, an undervoltage lockout circuit, a detection circuit, a logic circuit, a level conversion circuit, a first drive circuit, a second drive circuit, a first capacitor, a first NMOS transistor, a second NMOS transistor and a first PMOS transistor. The circuit of the present application is an improved bootstrap circuit, which can realize circuit driving without using a charge pump or an oscillator, and can not only solve the problem of large driving voltage swing in the DC motor drive circuit in the prior art, but also reduce costs, circuit area, circuit power consumption, and realize chip miniaturization.

[0110] The above descriptions are merely embodiments of the present invention and are not intended to limit the protection scope of the present invention. Any equivalent structural transformations made using the contents of the present invention description and drawings, or directly or indirectly applied in other related technical fields, are also included in the protection scope of the present invention.

Claims

1. A bootstrap output stage drive circuit for a DC motor, characterized in that: include: A power supply, a first diode, an undervoltage lockout circuit, a detection circuit, a logic circuit, a level conversion circuit, a first drive circuit, a second drive circuit, a first capacitor, a first NMOS transistor, a second NMOS transistor, and a first PMOS transistor; The positive electrode of the power supply is electrically connected to the anode of the first diode, the first connection end of the detection circuit, the first connection end of the logic circuit, and the first connection end of the second drive circuit; the negative electrode of the power supply is grounded, and is electrically connected to the fourth connection end of the detection circuit, the second connection end of the logic circuit, the second connection end of the second drive circuit, and the source of the second NMOS tube respectively; The cathode of the first diode is electrically connected to the source of the first PMOS tube, the first connection end of the undervoltage lockout circuit, the first connection end of the level conversion circuit, the first connection end of the first driving circuit and the first connection end of the first capacitor respectively; The second connection end of the undervoltage lockout circuit is electrically connected to the gate of the first PMOS tube, and the third connection end of the undervoltage lockout circuit is electrically connected to the second connection end of the level conversion circuit, the second connection end of the first drive circuit, the source of the first NMOS tube, the drain of the second NMOS tube and the second connection end of the first capacitor respectively; The source of the first NMOS tube also serves as an output terminal for supplying power to a load; The second connection end of the detection circuit is electrically connected to the drain of the first PMOS tube, and the third connection end of the detection circuit is electrically connected to the third connection end of the logic circuit; The fourth connection terminal of the logic circuit is electrically connected to the third connection terminal of the second driving circuit, the fifth connection terminal of the logic circuit is used to input a reset signal, and the sixth connection terminal of the logic circuit is electrically connected to the third connection terminal of the level conversion circuit; The fourth connection terminal of the level conversion circuit is electrically connected to the third connection terminal of the first driving circuit, the fourth connection terminal of the first driving circuit is electrically connected to the gate of the first NMOS transistor, and the drain of the first NMOS transistor is connected to the first voltage; The fourth connection terminal of the second driving circuit is electrically connected to the gate of the second NMOS transistor.

2. The bootstrap output stage driving circuit for a DC motor according to claim 1, characterized in that: The detection circuit includes a third NMOS tube, a fourth NMOS tube, a first resistor and a first NOT gate; The first connection end of the first resistor serves as the first connection end of the detection circuit and is electrically connected to the first connection end of the first NOT gate; The drain of the third NMOS tube serves as the second connection terminal of the detection circuit and is electrically connected to the gate of the third NMOS tube and the gate of the fourth NMOS tube respectively; The source of the third NMOS transistor serves as the fourth connection terminal of the detection circuit and is electrically connected to the source of the fourth NMOS transistor and the second connection terminal of the first NOT gate respectively; The drain of the fourth NMOS tube is electrically connected to the first connection end of the first resistor and the third connection end of the first NOT gate respectively; The fourth connection terminal of the first NOT gate serves as the third connection terminal of the detection circuit and is electrically connected to the third connection terminal of the logic circuit.

3. The bootstrap output stage driving circuit for a DC motor according to claim 1, characterized in that: The logic circuit includes a second NOT gate, a third NOT gate and a first NAND gate; The first connection end of the second NOT gate serves as the fifth connection end of the logic circuit; the second connection end of the second NOT gate serves as the sixth connection end of the logic circuit and is electrically connected to the third connection end of the level conversion circuit and the first connection end of the third NOT gate respectively; the third connection end of the second NOT gate is electrically connected to the third connection end of the third NOT gate and the third connection end of the first NAND gate respectively, and serves as the first connection end of the logic circuit; the fourth connection end of the second NOT gate is electrically connected to the fourth connection end of the third NOT gate and the fourth connection end of the first NAND gate respectively, and serves as the second connection end of the logic circuit; The second connection terminal of the third NOT gate is electrically connected to the first connection terminal of the first NAND gate; The second connection terminal of the first NAND gate serves as the third connection terminal of the logic circuit and is electrically connected to the third connection terminal of the detection circuit; The fifth connection terminal of the first NAND gate serves as the fourth connection terminal of the logic circuit.

4. The bootstrap output stage driving circuit for a DC motor according to claim 1, characterized in that: The first driving circuit includes a first buffer, wherein the first connection end of the first buffer serves as the first connection end of the first driving circuit, the second connection end of the first buffer serves as the second connection end of the first driving circuit, the third connection end of the first buffer serves as the third connection end of the first driving circuit, and the fourth connection end of the first buffer serves as the fourth connection end of the first driving circuit.

5. The bootstrap output stage driving circuit for a DC motor according to claim 1, characterized in that: The second driving circuit includes a second buffer, wherein the first connection end of the second buffer serves as the first connection end of the second driving circuit, the second connection end of the second buffer serves as the second connection end of the second driving circuit, the third connection end of the second buffer serves as the third connection end of the second driving circuit, and the fourth connection end of the second buffer serves as the fourth connection end of the second driving circuit.

6. The bootstrap output stage driving circuit for a DC motor according to claim 1, characterized in that: The undervoltage lockout circuit comprises a second resistor, a third resistor, a first amplifier, a second amplifier, a second NAND gate, a third NAND gate and a fourth NAND gate; The first connection end of the second resistor is connected to the second voltage, the second connection end of the second resistor is electrically connected to the first connection end of the third resistor, the inverting input end of the first amplifier and the non-inverting input end of the second amplifier respectively, and the second connection end of the third resistor is grounded; The non-inverting input terminal of the first amplifier serves as the first connection terminal of the undervoltage lockout circuit; the output terminal of the first amplifier is electrically connected to the first connection terminal of the second NAND gate; The second connection end of the second NAND gate is electrically connected to the output end of the third NAND gate; the third connection end of the second NAND gate is electrically connected to the first connection end of the third NAND gate and the first connection end of the fourth NAND gate respectively, and the second connection end of the fourth NAND gate serves as the second connection end of the undervoltage lockout circuit; The inverting input terminal of the second amplifier serves as the third connection terminal of the undervoltage lockout circuit, and the output terminal of the second amplifier is electrically connected to the second connection terminal of the third NAND gate.

7. The bootstrap output stage driving circuit for a DC motor according to claim 1, characterized in that: The level conversion circuit includes a fourth resistor, a second PMOS transistor and a fifth NMOS transistor; The first connection end of the fourth resistor serves as the first connection end of the level conversion circuit, and the second connection end of the fourth resistor is electrically connected to the source of the second PMOS transistor and also serves as the fourth connection end of the level conversion circuit; The gate of the second PMOS tube serves as the second connection terminal of the level conversion circuit, and the drain of the second PMOS tube is electrically connected to the drain of the fifth NMOS tube; The source of the fifth NMOS tube is grounded, and the gate of the fifth NMOS tube serves as the third connection terminal of the level conversion circuit.

8. The bootstrap output stage driving circuit for a DC motor according to claim 1, characterized in that: The logic circuit includes a fifth NOT gate, a third buffer and a fourth NAND gate; The first connection terminal of the fifth NOT gate is electrically connected to the first connection terminal of the third buffer and serves as the fifth connection terminal of the logic circuit; The second connection terminal of the fifth NOT gate serves as the sixth connection terminal of the logic circuit and is electrically connected to the third connection terminal of the level conversion circuit; The second connection terminal of the third buffer is electrically connected to the first connection terminal of the fourth NAND gate; The third connection terminal of the third buffer is electrically connected to the third connection terminal of the fourth NAND gate respectively, and serves as the first connection terminal of the logic circuit; The fourth connection terminal of the third buffer is electrically connected to the fourth connection terminal of the fourth NAND gate and serves as the second connection terminal of the logic circuit; The second connection terminal of the fourth NAND gate serves as the third connection terminal of the logic circuit and is electrically connected to the third connection terminal of the detection circuit; The fifth connection terminal of the fourth NAND gate serves as the fourth connection terminal of the logic circuit.

9. A bootstrap output stage driver chip for a DC motor, characterized in that: A bootstrap output stage drive circuit for a DC motor comprising the method described in any one of claims 1 to 8.

10. A bootstrap output stage driving device for a DC motor, characterized in that: The invention comprises the bootstrap output stage driver chip for a DC motor as claimed in claim 9.

Images