Configurable degenerate readout circuit and detection method for detecting multiple types of biological signals

Abstract

The invention relates to a configurable degenerate readout circuit and a detection method, in particular to a configurable degenerate readout circuit and a detection method for detecting various biological signals. The problems that an existing sensor reading circuit is large in power consumption and poor in universality are solved. The circuit comprises a data selector, a configurable degenerate reading circuit and an analog-to-digital converter, the data selector is provided with an input interface, adapts to various sensors and processes four sensing signals from the corresponding sensors, so that the whole circuit measures the outputs of the four sensors at the same time, and the input end and the output end of the data selector are connected with the output end of the front-end sensor; the configurable degenerate reading circuit is provided with an output end and an input end, and is reconstructed into four measuring circuits through the control of a switch; and the analog-to-digital converter converts the analog voltage output by the front-end circuit into digital codes and outputs the digital codes to finish detection. The invention belongs to the technical field of biological signal reading circuits.

Description

Technical Field

[0001] The invention relates to a configurable degenerate readout circuit and a detection method, belonging to the technical field of biological signal readout circuits. Background Art

[0002] In recent years, with the continuous development of the Internet of Things industry, the sensor industry has also developed rapidly. As an indispensable part of the big data information age, sensors have become an emerging high-tech industry with huge development potential. In the sensor application system, the sensor readout circuit is an indispensable part. The function of the sensor is to convert the physical quantity to be measured in the environment into an electrical signal, and the readout circuit is responsible for converting the electrical signal output by the front-end sensor into an analog signal, including the analog front-end circuit (Analog-Front-End, AFE) and the analog-to-digital converter (ADC). The converted analog voltage signal is sent to the analog-to-digital converter and the microprocessor, and finally the corresponding digital signal is output.

[0003] In the design of sensors, the chip area occupied by AFE is very small, but its power consumption accounts for half of the overall chip power consumption. At present, with the continuous development of CMOS technology, the size of transistors is shrinking year by year, but the threshold voltage of MOS tubes cannot decrease in proportion. As the feature size decreases, due to low voltage power supply, hot carrier injection, leakage current and speed saturation of short channel devices are becoming more and more serious. Therefore, a better way should be found to solve the above problems in AFE circuits.

[0004] Nowadays, our daily lives are increasingly dependent on sensing technology. Sensor-enabled devices are ubiquitous and widely used, from environmental monitoring and building safety to personal biomedicine, such as molecular detection and health monitoring. Sensing technology has been continuously developed over the years and has greatly improved the quality of life, but there is still a lot of room for improvement. Current commercial sensing devices for health monitoring are usually bulky, expensive, and power-consuming, making them inconvenient for daily use. However, with the widespread introduction of micro-nanotechnology, various new types of compact physiological sensor systems have emerged one after another, such as small DNA and protein detection chips, implantable blood pressure monitoring microsystems, and continuous glucose sensors. However, most of them can only effectively detect a single health indicator. In addition, they may be manufactured by different technologies and produce incompatible output signals, and their data collection process is more complicated. In many real-life applications, such as treating patients with severe heart disease or lung failure, it is necessary to monitor several biomedical signals simultaneously. Therefore, doctors must deal with different types of monitoring systems in parallel, wasting a lot of valuable time and increasing the possibility of medical errors.

[0005] Most analog front-end circuits can only convert a single type of target sensor, and their functions and uses are relatively simple. At the same time, developing signal processing readout circuits for dedicated sensors will consume a lot of time and cost, and the flexibility and scalability of its system are also greatly limited. In order to meet current needs, a configurable degenerate analog front-end circuit suitable for a general sensor platform should be designed. The configurable degenerate analog front-end can accept different sensor output types and connection configurations, thereby improving the efficiency of circuit design, reducing costs, and improving system flexibility. Summary of the invention

[0006] The present invention aims to solve the problems of high power consumption and poor versatility of existing sensor readout circuits, and further proposes a configurable degenerate readout circuit and a detection method for detecting multiple types of biological signals.

[0007] The technical solution adopted by the present invention to solve the above problems is: the circuit of the present invention includes a data selector, a configurable degenerate readout circuit and an analog-to-digital converter;

[0008] The data selector is configured with an input interface, adapted to various sensors, and processes four sensing signals from corresponding sensors, so that the overall circuit measures the outputs of the four sensors simultaneously, and the input and output ends of the data selector are connected to the output ends of the front-end sensors;

[0009] The configurable degenerate readout circuit is provided with an output terminal and an input terminal, and is reconfigured into four measurement circuits through the control of switches;

[0010] The analog-to-digital converter converts the analog voltage output by the front-end circuit into a digital code output to complete the detection.

[0011] Furthermore, there are four front-end sensors, which are used to measure glucose concentration, protein concentration, pH value and temperature, respectively, and have four independent outputs;

[0012] The data selector also includes four clocks, which control four switches respectively. The four switches are reconfigured every 500ms, and the time-division multiplexing cyclic operation enables the overall circuit to measure the outputs of four front-end sensors simultaneously.

[0013] Further, the configurable degenerate readout circuit includes an amplifier, noise storage capacitors CCDS, CCDSC, feedback capacitors CVC, CF, feedback resistors Rf, Rfi and switch arrays S1-S32;

[0014] The non-inverting input terminal of the amplifier is connected to the reference voltage VAMP through switches S22-S26, and the non-inverting input terminal of the amplifier is also connected to the feedback capacitor CVC through switches S14 and S15. The feedback capacitor CVC is connected to the output of the front-end data selector through switches S3 and S7. The inverting input terminal of the amplifier is connected to the noise storage capacitors CCDS, CCDSC and five parallel branches.

[0015] Furthermore, the configurable degenerate readout circuit includes four measurement circuits, and the four measurement circuits are: glucose mode, protein mode, pH mode and temperature mode.

[0016] Further, the temperature mode circuit includes an amplifier, a feedback capacitor CVC, CCDS, switches S3, S7, S10, S11, S14, S15, S16, S17, S19, S25, S26, S27, S29. In the storage phase, the noise is stored in the noise storage capacitor CCDS. In the acquisition phase, the configurable degenerate readout circuit is configured as a voltage follower with a high input impedance characteristic, and the output voltage is calculated by the formula V out =IN sense get.

[0017] Further, the pH mode circuit includes an amplifier, a feedback capacitor CCDS, a feedback resistor RFi, switches S3, S4, S16, S17, S18, S22, S27, S28, S29, and S31. In the storage phase, the noise is stored in the noise storage capacitor CCDS. In the acquisition phase, the configurable degenerate readout circuit is configured as a transimpedance amplifier with a low input impedance characteristic, and the output voltage is calculated by the formula V out =V ref +R fi IN sense get.

[0018] Further, the protein mode circuit includes an amplifier, a feedback capacitor CCDS, a feedback resistor RF, switches S3, S6, S16, S17, S20, S24, S27, S28, and S30. In the storage phase, the noise is stored in the noise storage capacitor CCDS. In the acquisition phase, the configurable degenerate readout circuit is configured as a transimpedance amplifier with a low input impedance characteristic, and the output voltage is calculated by the formula get.

[0019] Further, the glucose mode circuit includes an amplifier, a feedback capacitor CCDSC, a feedback capacitor Cf, switches S1, S2, S3, S5, S16, S17, S21, S23, S27, S28, and S32. In the storage phase, the noise is stored in the noise storage capacitor CCDSC. In the acquisition phase, the configurable degenerate readout circuit is configured as a charge amplifier having the same negative feedback structure as the transimpedance amplifier, and the output voltage is calculated by the formula get.

[0020] The steps of the method of the present invention include:

[0021] At time 1, that is, when the data selector clock SWM is at a high level and the other clocks are at a low level, the configurable degenerate readout circuit is configured to a glucose mode through the control of the switch, that is, a charge amplifier with the same negative feedback structure as the transimpedance amplifier. The circuit detects the glucose concentration, and the analog voltage output by the front-end circuit is converted into a digital code output;

[0022] At time 2, that is, when the data selector clock SWF is at a high level and the other clocks are at a low level, the degenerate readout circuit can be configured to a protein mode through the control of the switch, that is, a transimpedance amplifier with a low input impedance characteristic, and the circuit detects the protein concentration, and the analog voltage output by the front-end circuit will be converted into a digital code output;

[0023] At time 3, that is, when the data selector clock SWI is at a high level and the other clocks are at a low level, the degenerate readout circuit can be configured to a pH value mode through the control of the switch, that is, a transimpedance amplifier with a low input impedance characteristic, and the circuit detects the pH value, and the analog voltage output by the front-end circuit will be converted into a digital code output;

[0024] At time 4, that is, when the data selector clock SWB is at a high level and the other clocks are at a low level, the degenerate readout circuit can be configured to a temperature mode through the control of the switch, that is, a voltage follower with a high input impedance characteristic, and the circuit detects the temperature, and the analog voltage output by the front-end circuit will be converted into a digital code output;

[0025] At the next moment, the data selector clock returns to moment 1 and continues the above operation to complete the function of simultaneously processing the four sensing signals from the corresponding sensors.

[0026] The beneficial effects of the present invention are:

[0027] Compared with other sensor readout circuits, the present invention can process the output parameters of the four sensors at the same time, effectively reducing the chip area and power consumption, and can be applied to various sensor application systems. It has versatility. When the front-end sensor outputs different modal signals, it can directly switch the mode, realizing the intelligence and adaptability of the readout circuit, and has convenience and flexibility.

[0028] The present invention can process the output parameters of the four sensors at the same time, realize the intelligence and self-adaptation of the interface circuit, and has convenience and flexibility;

[0029] The present invention effectively reduces the chip area and power consumption by multiplexing the same amplifier;

[0030] The present invention solves the problem that different types of sensors cannot directly reuse the same micro-sensor readout circuit, can be applied to various sensor systems, and has universality. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a schematic diagram of the overall circuit structure of the present invention;

[0032] Figure 2 This is the timing diagram of the four clocks of the data selector;

[0033] Figure 3 is a schematic diagram of a circuit structure of a configurable degenerate readout circuit;

[0034] Figure 4 It is a schematic diagram of the circuit structure of the analog-to-digital converter;

[0035] Figure 5 This is a comparison chart of chip test results, where: Figure 5 (a) is a comparison chart of chip test results when the front end is a temperature sensor. Figure 5 (b) is a comparison chart of chip test results when the front end is a protein concentration sensor. Figure 5 (c) is a comparison chart of chip test results when the front end is a glucose concentration sensor. Figure 5 (d) is a comparison chart of chip test results when the front end is a pH sensor. DETAILED DESCRIPTION

[0036] Specific implementation method 1: Figure 1 As shown, a configurable degenerate readout circuit for detecting multiple types of biological signals includes three modules: a data selector, a configurable degenerate readout circuit, and a Sigma-Delta analog-to-digital converter;

[0037] At the same time, the circuit also includes two types of switches, one is the switch of the data selector, each conversion mode corresponds to a switch, a total of four modes, namely glucose mode, protein mode, pH mode and temperature mode, the other is the switch that controls the storage mode and the sampling mode, which is switched by two sets of complementary clocks, and the clocks are set to sw1 and sw2. When clock 1 (sw1) is closed and clock 2 (sw2) is disconnected, it is in storage mode; when clock 1 (sw1) is disconnected and clock 2 (sw2) is closed, it is in sampling mode. The duty cycle of the two clock signals is set to 50%. Compared with the traditional sensor readout circuit, the present invention can be applied to various sensor systems, has universality, solves the problem that different types of sensors cannot directly reuse the same microsensor readout circuit, effectively reduces the chip area and reduces power consumption.

[0038] Specific implementation method 2: Figure 2 As shown, the data selector 101 controls four switches, namely SWM, SWF, SWI and SWB, respectively. The interface of the data selector is reconfigured every 500ms, and the four sensing signals from the corresponding sensors are processed in turn, providing a time-division multiplexing cyclic operation, so that the overall circuit can measure the outputs of the four sensors at the same time. At the same time, the input end of the data selector is connected to the output of the front-end sensor. The four sensors at the front end are used to measure glucose concentration, protein concentration, pH value and temperature, respectively, and have four independent outputs.

[0039] Specific implementation method three: Figure 3As shown, the configurable degenerate readout circuit 102 includes an amplifier, noise storage capacitors CCDS, CCDSC, feedback capacitors CVC, CF, feedback resistors Rf, Rfi, and switch arrays S1-S32. The in-phase input of the amplifier is connected to a reference voltage VAMP through switches S22-S26, and the reference voltage VAMP is used to ensure that the amplifier can work normally. The in-phase input of the amplifier is also connected to the feedback capacitor CVC through switches S14 and S15. The feedback capacitor CVC is controlled by switches S8-S13 and configured in different circuits. It is connected to the output of the front-end data selector through switches S3 and S7. The inverting input of the amplifier is connected to the noise storage capacitors CCDS, CCDSC and five parallel branches. The reference voltage VREF is also connected to this branch through switch S16. The output of the end data selector is connected to this branch through switches S3-S6. The feedback capacitors CCDS and CCDSC are controlled by switches S18-S21 and configured in different circuits. The five parallel branches are switch S28, switch S29, switch S30 and feedback resistor Rf in series, switch S31 and feedback resistor Rfi in series, switch S32 and feedback capacitor Cf in series. Switches S17 and S27 are used to control the way in which the noise storage capacitors CCDS and CCDSC are connected to the circuit in different modes. Switches S1 and S2 are used to ground the output capacitor of the front-end data selector to release the charge.

[0040] The noise storage capacitor CCDSC is a capacitor with a fixed capacitance at one end connected to the inverting input terminal of the amplifier and the other end connected to the switch S21. The feedback capacitor CF is a capacitor with a fixed capacitance at one end connected to the output terminal of the amplifier and the other end connected to the switch S32. The feedback resistor Rfi is a resistor with a fixed resistance at one end connected to the output terminal of the amplifier and the other end connected to the switch S31.

[0041] Specific implementation method four: Figure 3 As shown, the configurable degenerate readout circuit (102) includes two working modes, namely storage mode and sampling mode. It is controlled by two-phase non-overlapping clocks SW1 and SW2. In the storage mode, the noise is stored in the noise storage capacitors CCDS and CCDSC. In the sampling mode, the noise storage capacitors are connected to the circuit without a charge flow path, thereby achieving the purpose of reducing noise.

[0042] The configurable degenerate readout circuit (102) includes four measurement circuits, which can be configured into different types of circuits, namely, glucose mode, protein mode, pH mode and temperature mode, through the control of switches according to the type of the front-end sensor.

[0043] like Figure 3As shown, when the clock SWM output of the front-end data selector is high, the configurable degenerate readout circuit is configured as a glucose mode, and the circuit includes an amplifier, a feedback capacitor CCDSC, a feedback capacitor Cf, switches S1, S2, S3, S5, S16, S17, S21, S23, S27, S28, and S32. At this time, the configurable degenerate readout circuit is configured as a charge amplifier with the same negative feedback structure as the transimpedance amplifier. In the storage stage, the noise storage capacitor CCDSC is connected to the reference voltage VREF through switches S16 and S21, and the other end is directly connected to the amplifier output end, and is connected to the amplifier inverting end through switches S27 and S28. The amplifier inverting end is connected to the reference voltage VAMP through switch S23. The reference voltage ensures the normal operation of the amplifier. At this time, the DC offset and low-frequency noise are stored in the noise storage capacitor CCDSC. In the sampling phase, the output of the data selector is connected to the inverting input of the amplifier through switches S3, S5, S21 and the noise storage capacitor CCDSC, and is connected to the output of the amplifier through switches S3, S5, S17, S32 and the feedback capacitor Cf. The non-inverting input of the amplifier is connected to the reference voltage VAMP through switch S23. The change in charge quantity causes the change in output voltage. The configurable degenerate readout circuit is configured as a charge amplifier with the same negative feedback structure as the transimpedance amplifier, and the output voltage is given by the formula get.

[0044] like Figure 3 As shown, when the clock SWF output of the front-end data selector is high, the configurable degenerate readout circuit is configured as a protein mode, and the circuit includes an amplifier, a feedback capacitor CCDS, a feedback resistor RF, switches S3, S6, S16, S17, S20, S24, S27, S28, and S30. At this time, the configurable degenerate readout circuit is configured as a transimpedance amplifier with low input impedance characteristics. In the storage stage, the noise storage capacitor CCDS is connected to the reference voltage VREF through switches S16 and S20, and the other end is directly connected to the amplifier output end, and is connected to the amplifier inverting end through switches S27 and S28. The amplifier in-phase end is connected to the reference voltage VAMP through switch S24. The reference voltage ensures the normal operation of the amplifier. At this time, the DC offset and low-frequency noise are stored in the noise storage capacitor CCDS. In the sampling phase, the output of the data selector is connected to the inverting input of the amplifier through switches S3, S6, S20 and the noise storage capacitor CCDS, and is connected to the output of the amplifier through switches S3, S6, S17, S30 and the feedback resistor Rf. The non-inverting input of the amplifier is connected to the reference voltage VAMP through switch S24. The current generated in the circuit loop will cause the output voltage to change. The configurable degenerate readout circuit is configured as a transimpedance amplifier with low input impedance characteristics. The output voltage is calculated by the formula get.

[0045] like Figure 3 As shown, when the clock SWI output of the front-end data selector is high, the configurable degenerate readout circuit is configured as a pH value mode, and the circuit includes an amplifier, a feedback capacitor CCDS, a feedback resistor RFi, switches S3, S4, S16, S17, S18, S22, S27, S28, S29, and S31. At this time, the configurable degenerate readout circuit is configured as a transimpedance amplifier with a low input impedance characteristic. In the storage stage, the noise storage capacitor CCDS is connected to the reference voltage VREF through switches S16 and S18, and the other end is directly connected to the inverting end of the amplifier, and is connected to the output end of the amplifier through switches S27 and S28. The in-phase end of the amplifier is connected to the reference voltage VAMP through switch S22. The reference voltage ensures that the amplifier works normally. At this time, the DC offset and low-frequency noise are stored in the noise storage capacitor CCDS. In the sampling phase, the output of the data selector is connected to the inverting input of the amplifier through switches S3, S4, S18 and the noise storage capacitor CCDS, and is connected to the output of the amplifier through switches S3, S4, S17, S31 and the feedback resistor Rfi. The in-phase input of the amplifier is connected to the reference voltage VAMP through switch S22. At this time, a closed loop is formed from the power supply, the feedback resistor to the output of the op amp. The change in the voltage drop across the feedback resistor will cause the change in the output voltage. The configurable degenerate readout circuit is configured as a transimpedance amplifier with a low input impedance characteristic. The output voltage is calculated by the formula V out =V ref +R fi IN sense get.

[0046] like Figure 3As shown, when the clock SWB output of the front-end data selector is high, the configurable degenerate readout circuit is configured as a temperature mode, and the circuit includes an amplifier, a feedback capacitor CVC, CCDS, switches S3, S7, S10, S11, S14, S15, S16, S17, S19, S25, S26, S27, S29. At this time, the configurable degenerate readout circuit is configured as a voltage follower with a high input impedance characteristic. In the storage stage, the feedback capacitor CVC is grounded through switches S10 and S11 to release all the original charges, and the noise storage capacitor CCDS is connected to the reference voltage VREF through switches S16 and S19, and the other end is directly connected to the inverting end of the amplifier, and is connected to the output end of the amplifier through switches S27 and S29. The in-phase end of the amplifier is connected to the reference voltage VAMP through switches S25 and S26. The reference voltage ensures the normal operation of the amplifier. At this time, the DC offset and low-frequency noise are stored in the noise storage capacitor CCDS. In the sampling phase, the output of the data selector is connected to the amplifier's in-phase input through switches S3, S7, feedback capacitor CVC, switches S14, S15, and the amplifier's inverting input is connected to the amplifier's output through noise storage capacitor CCDS, switches S19, S17, and S29. At this point, the configurable degenerate readout circuit is configured as a voltage follower with high input impedance characteristics, and the output voltage is given by the formula V out =IN sense get.

[0047] Specific implementation method five: Figure 4 As shown, the circuit of the analog-to-digital converter 103 includes a two-stage integrator, a comparator, a D flip-flop, a timing generation circuit and a switch, and the circuit operation includes two clocks, clk1 and clk2. The function of the D flip-flop is to determine the feedback voltage size as Vrefp or Vrefn, which is determined by the AND gate logic. Its specific working timing is: when clk1 rises, the first stage takes the value of Vref for integration, and when clk2 rises, the first stage performs sampling; when clk1 rises, the second stage performs sampling, and when clk2 rises, the second stage takes the value of Vref for integration, when clk1 rises, the comparator compares, when clk2 phase, the comparator latches, and when clk1 falls, the D flip-flop updates the value of the D flip-flop output. The feedback signal is delayed for two cycles and then operated with the first stage input. The reason why the D flip-flop works at the falling edge of clk1 is to obtain the stable result after the comparison of the comparator, and at the same time to ensure that the second stage obtains the correct feedback signal. The Sigma-Delta analog-to-digital converter completes the function of converting the analog voltage output by the front-end circuit into a digital code output.

[0048] Specific implementation method six: Figures 1 to 4 As shown, the detection method of the configurable degenerate readout circuit for detecting multiple types of biological signals comprises the following steps:

[0049] At time 1, that is, when the data selector clock SWM is at a high level and the other clocks are at a low level, the configurable degenerate readout circuit is configured to a glucose mode through the control of the switch, that is, a charge amplifier with the same negative feedback structure as the transimpedance amplifier. The circuit detects the glucose concentration, and the analog voltage output by the front-end circuit is converted into a digital code output;

[0050] At time 2, that is, when the data selector clock SWF is at a high level and the other clocks are at a low level, the degenerate readout circuit can be configured to a protein mode through the control of the switch, that is, a transimpedance amplifier with a low input impedance characteristic, and the circuit detects the protein concentration, and the analog voltage output by the front-end circuit will be converted into a digital code output;

[0051] At time 3, that is, when the data selector clock SWI is at a high level and the other clocks are at a low level, the degenerate readout circuit can be configured to a pH value mode through the control of the switch, that is, a transimpedance amplifier with a low input impedance characteristic, and the circuit detects the pH value, and the analog voltage output by the front-end circuit will be converted into a digital code output;

[0052] At time 4, that is, when the data selector clock SWB is at a high level and the other clocks are at a low level, the degenerate readout circuit can be configured to a temperature mode through the control of the switch, that is, a voltage follower with a high input impedance characteristic, and the circuit detects the temperature, and the analog voltage output by the front-end circuit will be converted into a digital code output;

[0053] At the next moment, the data selector clock returns to moment 1 and continues the above operation to complete the function of simultaneously processing the four sensing signals from the corresponding sensors.

[0054] like Figure 5 As shown in (a), (b), (c), and (d), the figure shows the comparison between the actual test value of the chip, the circuit simulation value, and the theoretical output value of the configurable degenerate readout circuit. It can be seen that the chip works normally and can simultaneously receive the output of the four sensors at the front end. The error between the processed results and the theoretical value is no more than 3%. This configurable degenerate readout circuit for detecting multiple types of biological signals can simultaneously complete the processing of the data transmitted by the four biosensors and has universality.

[0055] The above is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement made to the above embodiments without departing from the content of the technical solution of the present invention, based on the technical essence of the present invention, within the spirit and principles of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims

1. A configurable degenerate readout circuit for detecting multiple types of biological signals, characterized in that: It includes a data selector (101), a configurable degenerate readout circuit (102) and an analog-to-digital converter (103); The data selector (101) is configured with an input interface, adapted to various sensors, and processes four sensing signals from corresponding sensors, so that the overall circuit measures the outputs of the four sensors simultaneously, and the input and output ends of the data selector (101) are connected to the output ends of the front-end sensors; The configurable degenerate readout circuit (102) is provided with an output terminal and an input terminal, and is reconfigured into four measurement circuits through the control of switches; The analog-to-digital converter (103) converts the analog voltage output by the front-end circuit into a digital code output to complete the detection.

2. The configurable degenerate readout circuit for detecting multiple types of biological signals according to claim 1, characterized in that: There are four front-end sensors, which are used to measure glucose concentration, protein concentration, pH value and temperature, and have four independent outputs; The data selector (101) also includes four clocks, which respectively control the four switches and are reconfigured every 500 ms. The time-division multiplexing cyclic operation enables the overall circuit to measure the outputs of the four front-end sensors simultaneously.

3. The configurable degenerate readout circuit for detecting multiple types of biological signals according to claim 1, characterized in that: The configurable degenerate readout circuit (102) includes an amplifier, noise storage capacitors CCDS, CCDSC, feedback capacitors CVC, CF, feedback resistors Rf, Rfi and switch arrays S1-S32; The non-inverting input terminal of the amplifier is connected to the reference voltage VAMP through switches S22-S26, and the non-inverting input terminal of the amplifier is also connected to the feedback capacitor CVC through switches S14 and S15. The feedback capacitor CVC is connected to the output of the front-end data selector through switches S3 and S7. The inverting input terminal of the amplifier is connected to the noise storage capacitors CCDS, CCDSC and five parallel branches.

4. The configurable degenerate readout circuit for detecting multiple types of biological signals according to claim 1, characterized in that: The configurable degenerate readout circuit (102) comprises four measurement circuits, which are respectively: glucose mode, protein mode, pH value mode and temperature mode.

5. The configurable degenerate readout circuit for detecting multiple types of biological signals according to claim 4, characterized in that: The temperature mode circuit includes an amplifier, a feedback capacitor CVC, CCDS, switches S3, S7, S10, S11, S14, S15, S16, S17, S19, S25, S26, S27, and S29. In the storage phase, the noise is stored in the noise storage capacitor CCDS. In the acquisition phase, the configurable degenerate readout circuit is configured as a voltage follower with a high input impedance characteristic. The output voltage is calculated by the formula V out =IN sense get.

6. The configurable degenerate readout circuit for detecting multiple types of biological signals according to claim 4, characterized in that: The pH mode circuit includes an amplifier, a feedback capacitor CCDS, a feedback resistor RFi, switches S3, S4, S16, S17, S18, S22, S27, S28, S29, and S31. In the storage phase, the noise is stored in the noise storage capacitor CCDS. In the acquisition phase, the configurable degenerate readout circuit is configured as a transimpedance amplifier with a low input impedance characteristic. The output voltage is calculated by the formula V out =V ref +R fi IN sense get.

7. The configurable degenerate readout circuit for detecting multiple types of biological signals according to claim 4, characterized in that: The protein mode circuit includes an amplifier, a feedback capacitor CCDS, a feedback resistor RF, switches S3, S6, S16, S17, S20, S24, S27, S28, and S30. In the storage phase, the noise is stored in the noise storage capacitor CCDS. In the acquisition phase, the configurable degenerate readout circuit is configured as a transimpedance amplifier with a low input impedance characteristic. The output voltage is calculated by the formula get.

8. The configurable degenerate readout circuit for detecting multiple types of biological signals according to claim 4, characterized in that: The glucose mode circuit includes an amplifier, a feedback capacitor CCDSC, a feedback capacitor Cf, switches S1, S2, S3, S5, S16, S17, S21, S23, S27, S28, and S32. In the storage phase, the noise is stored in the noise storage capacitor CCDSC. In the acquisition phase, the configurable degenerate readout circuit is configured as a charge amplifier with the same negative feedback structure as the transimpedance amplifier. The output voltage is expressed by the formula get.

9. A detection method for a configurable degenerate readout circuit for detecting multiple types of biological signals, characterized in that: Specifically include: At time 1, that is, when the data selector clock SWM is at a high level and the other clocks are at a low level, the configurable degenerate readout circuit is configured to a glucose mode through the control of the switch, that is, a charge amplifier with the same negative feedback structure as the transimpedance amplifier. The circuit detects the glucose concentration, and the analog voltage output by the front-end circuit is converted into a digital code output; At time 2, that is, when the data selector clock SWF is at a high level and the other clocks are at a low level, the degenerate readout circuit can be configured to a protein mode through the control of the switch, that is, a transimpedance amplifier with a low input impedance characteristic, and the circuit detects the protein concentration, and the analog voltage output by the front-end circuit will be converted into a digital code output; At time 3, that is, when the data selector clock SWI is at a high level and the other clocks are at a low level, the degenerate readout circuit can be configured to a pH value mode through the control of the switch, that is, a transimpedance amplifier with a low input impedance characteristic, and the circuit detects the pH value, and the analog voltage output by the front-end circuit will be converted into a digital code output; At time 4, that is, when the data selector clock SWB is at a high level and the other clocks are at a low level, the degenerate readout circuit can be configured to a temperature mode through the control of the switch, that is, a voltage follower with a high input impedance characteristic, and the circuit detects the temperature, and the analog voltage output by the front-end circuit will be converted into a digital code output; At the next moment, the data selector clock returns to moment 1 and continues the above operation to complete the function of simultaneously processing the four sensing signals from the corresponding sensors.

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