High-speed backboard system and method for realizing LVDS communication based on FPGA

Abstract

The invention discloses a high-speed backboard system and method for achieving LVDS communication based on an FPGA, the high-speed backboard system comprises a controller and a communication assembly, the communication assembly comprises a plurality of communication modules, the communication assembly specifically comprises a master station module and at least one slave station module, the controller is connected with the master station module, and the slave station module is connected with the controller. An FPGA chip is arranged in each of the master station module and the slave station module, and the FPGA chip in the master station module is electrically connected with an MCU; each of the master station module and the slave station module at least comprises a sending interface and a receiving interface, and data frame interaction is carried out between the master station module and the slave station module through an interface assembly composed of the sending interface and the receiving interface. The master station module and the slave station module achieve data exchange through the interface assembly, the purpose that the master station module controls the slave station module and obtains information of the slave station module is achieved, the structure is simple, connection between the modules is stable and reliable, the use efficiency of the system on site is improved, and cost is reduced.

Description

Technical Field

[0001] The present application relates to the field of industrial automation control, and in particular to a high-speed backplane system and method for implementing LVDS communication based on FPGA. Background Art

[0002] At present, in the field of gateway communication, 485 communication and CAN communication are two commonly used communication protocols. However, these two communication protocols have the problem of slow communication speed, which limits the data exchange between the master station and the slave station and cannot meet the growing demand for high-speed data transmission. 485 communication or CAN communication protocol is usually used in the expansion module of gateway products. In order to achieve data transmission, it may be necessary to install terminal resistors on the end module to ensure signal stability. However, this method is not only cumbersome to install and debug, but once a node has a problem, the stability and reliability of the entire communication system will be affected.

[0003] Obviously, due to the limitation of communication speed and the cumbersome installation and debugging of modules during on-site use, traditional communication technology can no longer meet the demand for high-speed data transmission in modern industries, vehicles and other fields. Therefore, how to improve the data exchange speed of gateway expansion modules, simplify the installation and debugging process, and improve work efficiency and system stability are urgent problems to be solved by technicians in this field. Summary of the invention

[0004] In order to solve the above problems, the present application provides a high-speed backplane system and method for implementing LVDS communication based on FPGA, which realizes high-speed full-duplex communication, reduces the system data exchange cycle, and improves operating efficiency.

[0005] In the first aspect, the present application provides a high-speed backplane system for implementing LVDS communication based on FPGA, which adopts the following technical solutions: A high-speed backplane system for implementing LVDS communication based on FPGA, comprising a controller and a communication component, wherein the communication component comprises a plurality of communication modules, wherein the communication component specifically comprises a master station module and at least one slave station module, wherein the controller is connected to the master station module, wherein the master station module and the slave station module are each provided with an FPGA chip, and the FPGA chip in the master station module is also electrically connected to an MCU; The master station module and the slave station module each include at least one sending interface and one receiving interface, and the master station module and the slave station module interact with each other via an interface component composed of the sending interface and the receiving interface.

[0006] By adopting the above technical means, the master station module and the slave station module realize data exchange through the interface component, so that the master station module controls the slave station module and obtains the information of the slave station module. The structure is simple, the connection between the modules is stable and reliable, the efficiency of the system on site is improved, and the cost is reduced.

[0007] Preferably, all the communication modules are connected in series, each of the communication modules has at least one corresponding lower-level module or one upper-level module, and the communication module sends and receives the data frames through the interface component, and the data frames include continuous data frames and non-continuous data frames; When the master station module continues to send the continuous data frames to all the slave station modules, all the slave station modules enter a continuous reception and transmission state. When one of the slave station modules has a subordinate module, the slave station module establishes a hardware-triggered forwarding channel to forward the continuous data frames to its own subordinate module without delay.

[0008] By adopting the above-mentioned technical means, the system establishes a hardware-triggered forwarding channel when the communication module communicates continuous data frames, realizes the delay-free forwarding of continuous data frames, and the sending and receiving of all modules are independent of each other, realizing high-speed full-duplex communication of the system, reducing the cycle of data exchange and improving operation efficiency.

[0009] In the second aspect, the present application provides a method for implementing LVDS communication based on FPGA, which adopts the following technical solution: A method for implementing LVDS communication based on FPGA, based on the above-mentioned high-speed backplane system for implementing LVDS communication based on FPGA, comprises the following steps: All communication modules are started, and all lower-level modules continuously send their own existence data frames to the corresponding upper-level modules, and each of the communication modules determines whether it exists in the lower-level module according to the own existence data frames; Determine all existing slave modules according to all existing subordinate modules, and the master module performs module scanning on all existing slave modules to obtain attribute setting data of all slave modules; The master station module obtains configuration setting data from the controller of the high-speed backplane system, performs data comparison between the configuration setting data and the attribute setting data and obtains a comparison result; When the data comparison of all the lower-level modules is completed, the master station module sends continuous data frames to all the slave station modules for data communication based on the comparison results.

[0010] By adopting the above technical means, the master station module sends data frames to the slave station module to confirm, connect and scan the slave station module, and exchange data with the slave station module, so as to achieve the purpose of controlling the slave station module and obtaining the slave station module information through the master station module.

[0011] Preferably, each of the communication modules determines whether it has the lower-level module according to the data frame it has, which specifically includes the following steps: After each of the upper-level modules receives the self-existing data frame sent by the corresponding lower-level module, the upper-level module generates a lower-level module existence flag according to the self-existing data frame and stores it in its own FPGA chip; When the upper module is the master module, the MCU of the master module sends a lower-level existence confirmation data frame to the FPGA chip of the master module, inquiring whether there is a lower-level module existence mark in the FPGA chip. If so, the master module determines that the lower-level module exists in itself; if not, the master module determines that the lower-level module does not exist in itself; When the upper module is the slave module, the master module sends the lower existence confirmation data frame to the current slave module to inquire whether there is a lower module existence mark. If yes, the master module determines that the lower module exists in the current slave module; if no, the master module determines that the lower module does not exist in the current slave module. All the existing lower-level modules are aggregated to obtain all the slave station modules.

[0012] By adopting the above-mentioned technical means, each module can confirm whether it has a subordinate module through its own existence confirmation data frame. The master station module and the slave station module know whether they have a subordinate module through different confirmation methods. The master station module can determine all the existing slave station modules by inquiring all the subordinate modules.

[0013] Preferably, the determining of all existing slave modules based on all existing subordinate modules, the master module performing module scanning on all existing slave modules to obtain attribute setting data of all slave modules, specifically comprises the following steps: The master station module sends an allocation ID data frame to the corresponding subordinate slave station module. After the slave station module obtains and records the allocated ID number according to the allocation ID data frame, the slave station module sends an allocation success data frame to the master station module through its own sending interface. When the master station module receives the allocation success data frame, it is determined that the ID allocation of the current slave station module is successful. After the ID of the current slave station module is successfully allocated, the master station module sends an attribute acquisition data frame to the current slave station module, and the current slave station module replies with its own attribute setting data to the master station module based on the attribute acquisition data frame. The master station module receives and stores the attribute setting data of the current slave station module, and the attribute setting data includes a first order number and a first PD data length.

[0014] By adopting the above technical means, the master module first allocates IDs to the existing slave modules, and then obtains the order numbers and PD data lengths of these slave modules. The method for the master module to obtain slave module data is described in detail.

[0015] Preferably, after the master station module receives and stores the property setting data of the current slave station module, the method further comprises the following steps: After the master module assigns an ID to the slave module as its own subordinate module and obtains the attribute setting data of the slave module, the master module sends the subordinate existence confirmation data frame to the slave module; When the slave module replies to the master module that there is a slave module at the next level, the master module allocates an ID to the slave module currently confirmed to exist according to a preset allocation rule, wherein the allocation rule includes increasing the ID number of the slave module currently confirmed to exist relative to the ID number of the corresponding upper-level module by one, and after allocating the ID number of the slave module currently confirmed to exist, the master module obtains the attribute setting data of the slave module currently confirmed to exist; The master station module stops allocating IDs until the master station module receives a reply from the slave station module that the next-level slave station module does not exist.

[0016] By adopting the above technical means, the method of allocating slave module ID by the master module is described in detail. Each time the master module allocates an ID to a slave module, it obtains the attribute setting data of the slave module. In this way, IDs are allocated to all slave modules one by one, and the attribute setting data of all slave modules are obtained.

[0017] Preferably, the master station module obtains configuration setting data from the controller of the high-speed backplane system, performs data comparison between the configuration setting data and the attribute setting data and obtains the comparison result, which specifically includes the following steps: The master station module receives configuration setting data sent by the controller of the high-speed backplane system, wherein the configuration setting data includes the second order number and the second PD data length of the slave station module; After the master station module obtains the property setting data of all the slave station modules, the master station module compares the configuration setting data with the property setting data and obtains a comparison result, wherein the data comparison includes determining whether the first order number and the second order number of the same slave station module are consistent, and whether the lengths of the first PD data and the second PD data match; After the data comparison is completed, the master station module obtains the comparison result corresponding to each slave station module.

[0018] By adopting the above technical means, the configuration setting data in the controller is compared with the attribute setting data of the scanned slave module, so as to confirm whether the data in the slave module is correct, and ensure the data accuracy and security of subsequent communication between modules.

[0019] Preferably, after the data comparison of all the lower level modules is completed, the master station module sends continuous data frames to all the slave station modules for data communication in combination with the comparison result, including the following steps: When the comparison result is successful, judging whether the master station module needs to send the configuration parameters of the current slave station module to the slave station module according to the preset data sending rules, the configuration parameters are determined according to the configuration setting data, and the command type of the segment data frame of the current slave station module is determined according to the judgment result, and the command type includes sending configuration parameters, sending slave station output data and abnormal communication display; When the comparison result is failure, the command type in the segment data frame of the current slave module is abnormal communication display; After obtaining the segment data frames of all the slave station modules, the master station module sends the continuous data frames to the slave station modules, where the continuous data frames are composed of the segment data frames of all the slave station modules.

[0020] By adopting the above technical means, the command type of the segment data frame of each slave module is determined by comparing the attribute setting data of the slave module with the configuration setting data in the controller, thereby determining the continuous data frame sent by the master module to ensure normal communication between the master and slaves.

[0021] Preferably, the step of determining the command type of the segment data frame of the current slave module according to the judgment result specifically comprises the following steps: If the result of the judgment is that it is necessary, the command type of the current slave module is the sending configuration parameters, and the master module sends the configuration parameters to the slave module. After the configuration parameters are sent, the command type of the current slave module is modified to the sending slave output data, and the slave output data is obtained by the master module from the controller and is used to send to the slave module and control the slave module; If the result of the judgment is that it is not necessary, the command type of the current slave station module is the sending slave station output data.

[0022] By adopting the above technical means, the confirmation process of the command type of the segment data frame of the slave module that has been successfully compared is described in detail, so as to determine the specific content of the continuous data frame transmission.

[0023] Preferably, when the master station module sends the continuous data frames to the slave station module, the following steps are also included: When the data frame received by the slave module is not any one of the allocation ID data frame, the attribute acquisition data frame and the self-existence confirmation data frame, the slave module currently enters a continuous receiving and continuous sending state; After the slave station module enters the continuous reception and continuous transmission state, the slave station module continuously sends slave station input data to its own upper module. The slave station input data is the data generated by the slave station module itself. If the current slave station module has a lower-level slave station module, the slave station input data received from the lower-level slave station module will be attached to its own slave station input data and combined and sent to its own upper module until the slave station input data is sent to the master station module.

[0024] By adopting the above technical means, the master station module sends continuous data frames and the slave station module continuously receives and sends data simultaneously. The sending and receiving channels of the master station module and the slave station module are independent of each other, realizing high-speed full-duplex communication, reducing the system data exchange cycle and improving operation efficiency.

[0025] In summary, this application has at least the following beneficial effects: 1. The method of the present application realizes the connection and data exchange between the master station module and the slave station module through the communication of various data frames between the master station module and the slave station module, so as to achieve the purpose of the master station module controlling the slave station module and obtaining the information of the slave station module, realizes high-speed full-duplex communication, reduces the cycle of system data exchange, improves the efficiency of use on site, and reduces the cost.

[0026] 2. The system structure of the present application is simple, which makes the connection between modules stable and reliable, improves the efficiency of on-site use and reduces costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is an architecture diagram of a high-speed backplane system for implementing LVDS communication based on FPGA in an embodiment of the present application; Figure 2 is a flow chart of a method for implementing LVDS communication based on FPGA in an embodiment of the present application; Figure 3 It is a flow chart of connecting a master station module with its subordinate slave station module in a method for realizing LVDS communication based on FPGA in an embodiment of the present application; Figure 4 It is a flow chart of the method for realizing LVDS communication based on FPGA in an embodiment of the present application, in which the master station module is connected to the remaining slave station modules through its subordinate slave station module. DETAILED DESCRIPTION

[0028] The present application provides a high-speed backplane system and method for implementing LVDS communication based on FPGA. In order to make the purpose, technical solution and advantages of the present application clearer, the implementation method of the present application will be further described in detail below.

[0029] The following is a further detailed description of an embodiment of a high-speed backplane system for implementing LVDS communication based on FPGA of the present application in conjunction with the drawings of the specification.

[0030] A high-speed backplane system for implementing LVDS communication based on FPGA, comprising a controller and a communication component. In this embodiment, the controller is a PLC, the communication component comprises a plurality of communication modules, the communication component specifically comprises a master module and at least one slave module, the controller is connected to the master module, the master module and the slave module are both provided with an FPGA chip, and the FPGA chip in the master module is also electrically connected to an MCU; The FPGA chip in the slave module is necessary, and the MCU can decide whether to set it according to the complexity of the slave module function. The MCU and FPGA chip of the master module are connected through SPI, QSPI or parallel port to exchange data.

[0031] The master station module and the slave station module each include at least one sending interface and one receiving interface. The master station module and the slave station module exchange data frames via an interface component composed of the sending interface and the receiving interface.

[0032] In a specific implementation method, Figure 1As shown, the master module and the slave modules, as well as the slave modules and the slave modules are connected through LVDS interfaces. The master module has one LVDS transmission interface and one LVDS reception interface. Most of the slave modules have two LVDS transmission interfaces and two LVDS reception interfaces, but the last slave module has one LVDS transmission interface and one LVDS reception interface. Figure 1 The first slave module and the second slave module have two LVDS transmission interfaces and two LVDS reception interfaces, and the third slave module has one LVDS transmission interface and one LVDS reception interface.

[0033] All communication modules are connected in series with each other, each communication module has at least one corresponding lower-level module or one upper-level module, and the communication modules send and receive data frames through the interface components.

[0034] like Figure 1 As shown, in this embodiment, the lower level module of the master station module is the first slave station module, and the corresponding upper level module of the first slave station module is the master station module. In this embodiment, the LVDS interface in the interface component is named according to the output direction of the data.

[0035] For example, for the master module, two LVDS interfaces are defined as a downstream transmission interface and an upstream reception interface; for the slave module, four LVDS interfaces are defined as a downstream reception interface, a downstream transmission interface, an upstream reception interface, and an upstream transmission interface.

[0036] The data frame includes continuous data frames and non-continuous data frames. The continuous data frame is composed of the segment data frame of each slave module. Assuming there is 1 master module and 3 slave modules, the continuous data frame is composed of the segment data frame of the first slave module + the segment data frame of the second slave module + the segment data frame of the third slave module.

[0037] In short, a non-continuous data frame is a data frame that contains data of only one communication module, and a continuous data frame is a data frame that contains data of multiple communication modules.

[0038] The segment data frame uses hexadecimal and consists of a frame interval byte (0xAA), ID number, segment data frame length, CMD (command type), data and CRC. For example, the segment data frame AA 01 00 07 06 11 22 CRC, where the 0x01 byte is the ID number, the 00 07 bytes are the segment data frame length (the length is expressed in two bytes, of which AA is an identifier and is not included in the data length), the 0x01 byte is the command type, and the 11 22 bytes are the data.

[0039] The master module uses non-continuous data to allocate IDs to all slave modules, obtain the slave module order number and the input and output PD data length information of the slave module, and inquire whether the slave module has the next-level slave module.

[0040] When a slave module has a subordinate module, the slave module establishes a hardware-triggered forwarding channel and forwards continuous data frames to its own subordinate module through the downlink transmission interface B without delay at the nanosecond level. Therefore, for the continuous data frames sent by the master module, all slave modules can be considered to have received the same continuous data frames synchronously.

[0041] The master module exchanges input and output data of all slave modules through continuous data frames. When the master module continuously sends continuous data frames to all slave modules, all slave modules enter a continuous receiving and sending state.

[0042] In another specific implementation, a method for implementing LVDS communication based on FPGA is disclosed, which adopts the following technical solution: A method for implementing LVDS communication based on FPGA, such as Figure 2 As shown, based on the above Figure 1 The high-speed backplane system shown includes the following steps: S1. All communication modules are started. All lower-level modules continuously send their own existing data frames to the corresponding upper-level modules. Each communication module determines whether it has a lower-level module based on its own existing data frames. Specifically, the steps include: S11, connect all communication modules in series, connect the master module to the PLC controller, and start all communication modules; Combination Figure 3 As shown, after all slave modules are started, they actively start the uplink sending interface to continuously and uninterruptedly send their own existing data frames to their own superior modules, and start the uplink receiving interface to facilitate receiving the own existing data frames sent by the subordinate slave modules.

[0043] After the master station module is started, the FPGA chip starts the uplink receiving interface to receive the self-existing data frame sent by the slave station module using the uplink sending interface.

[0044] S12. After each upper-level module receives its own existence data frame sent by the corresponding lower-level module, the upper-level module generates a lower-level module existence flag based on its own existence data frame and stores it in its own FPGA chip.

[0045] S13. When the upper module is the master module, the MCU of the master module sends a lower-level existence confirmation data frame to its own FPGA chip, and uses the scan command to inquire whether there is a lower-level module existence mark in the FPGA chip. The FPGA chip replies to the MCU based on whether there is a lower-level module existence mark.

[0046] If it exists, the master module determines that it has a subordinate module; if it does not exist, the master module determines that it has no subordinate module.

[0047] If there is only a master module in the system, the FPGA chip of the master module cannot receive its own data frames from the subordinate slave modules, and the scan commands will be repeated between the MCU and the FPGA.

[0048] S14, when the upper module is a slave module, the master module sends a lower-level existence confirmation data frame to the current slave module to inquire whether there is a lower-level module existence mark. If yes, the master module determines that the current slave module has a lower-level module; if no, the master module determines that the current slave module does not have a lower-level module; S15. Summarize all existing lower-level modules to obtain all slave station modules.

[0049] For a system with multiple slave modules, the above steps can be considered to be performed synchronously after the system is powered on.

[0050] S2. Determine all existing slave modules based on all existing lower level modules, and the master module performs module scanning on all existing slave modules to obtain attribute setting data of all slave modules, including the following steps: S21. The master station module sends an allocation ID data frame to the corresponding subordinate slave station module.

[0051] In a specific implementable manner, the ID number sent by the master station module to its subordinate slave station module is 1.

[0052] S22, after the downlink receiving interface of the current slave module obtains the assigned ID number according to the assigned ID data frame, it stops the uplink sending interface from continuously sending its own existing data frame and records the assigned ID; The slave module sends a successful allocation data frame to the master module through its own uplink transmission interface, indicating that it has received the allocated ID; When the master module receives the allocation success data frame, it determines that the ID allocation of the current slave module is successful.

[0053] S23. After the ID of the current slave module is successfully allocated, the master module sends a property acquisition data frame to the current slave module to obtain the property setting data of the first slave module. In this embodiment, the property setting data includes the first order number and the first PD data length of the first slave module.

[0054] S24. The current first slave station module replies its own attribute setting data to the master station module according to the attribute acquisition data frame, and the master station module receives and stores the attribute setting data of the current slave station module.

[0055] In summary, when the subordinate module exists, the master station module assigns an ID to the existing subordinate module. When the ID of the subordinate module is successfully assigned, the master station module obtains the property setting data of the current subordinate module. Through the above steps, the subordinate module of the master station module, that is, the first slave station module, has successfully completed the connection with the master station module.

[0056] S25, the master station module sends a lower-level existence confirmation data frame to the first slave station module, and the first slave station module replies to the master station module according to whether it has stored a lower-level module existence flag. If there is a lower-level module existence flag, the lower-level module exists, otherwise the lower-level module does not exist.

[0057] S26, Combination Figure 4 As shown, when the first slave module replies to the master module that there is a slave module at the next level, the master module allocates an ID to the slave module currently confirmed to exist according to a preset allocation rule; In this embodiment, the allocation rule includes increasing the ID number of the currently confirmed existing slave module relative to the ID number of the corresponding upper module by one, so the ID number allocated to the lower module of the first slave module is 2.

[0058] S27. After allocating the ID number of the currently confirmed existing slave module, the master module obtains the property setting data of the currently confirmed existing slave module, that is, obtains the first order number and the first PD data length of the second slave module.

[0059] It should be noted that after the slave module assigns an ID, it does not process the assigned ID data frame whose ID is greater than its own ID internally, and directly forwards it to the downstream sending interface.

[0060] That is to say, when the slave module has not been assigned an ID, the assigned ID data frame received by the downstream interface needs to be processed, and the processing method is to reply with an allocation success data frame; if the slave module has been assigned an ID, the received assigned ID data frame is not processed, and is directly forwarded to the downstream sending interface and sent to the lower-level slave module.

[0061] This processing method is not only used for the allocation ID data frame, but also for the sending attribute acquisition data frame and the replied attribute setting data.

[0062] For example, in a specific implementable method, after the first slave station module is successfully connected to the master station module, when the downstream receiving interface receives an allocation ID data frame, an attribute acquisition data frame or a subordinate existence confirmation data frame, since the first slave station module has successfully allocated the ID, the first slave station module does not process the allocation ID data frame, the attribute acquisition data frame and the subordinate existence confirmation data frame of the second slave station module or other slave station modules internally, and directly forwards them to the downstream sending interface; similarly, the first slave station module does not process the allocation success data frame, the attribute setting data and the reply to the subordinate existence confirmation data frame received by the upstream receiving interface of the first slave station module internally, and directly forwards them to the upstream sending interface.

[0063] S28. Repeat the above steps until the master module receives a reply from the last slave module that there is no next-level slave module, and then the master module stops allocating IDs.

[0064] Here, when the master module receives the reply from the last slave module that there is no next-level slave module, it is not that the last slave module directly replies to the master module. The inquiry of the master module is forwarded by several intermediate slave modules to reach the last slave module, and the last slave module replies that there is no next-level slave module. The last slave module forwards this reply result to the master module through the uplink sending interface through several slave modules.

[0065] At this point, all slave modules have been successfully scanned by the master module, and the master module ends the system scanning action. During this period, all data frames are non-continuous data frames.

[0066] S3, the master station module obtains the configuration setting data from the controller of the high-speed backplane system, compares the configuration setting data with the attribute setting data and obtains the comparison result, including the following steps: S31. The master station module receives configuration setting data sent by the controller of the high-speed backplane system, where the configuration setting data includes the second order number and the second PD data length of the slave station module.

[0067] In a specific implementation method, the master station module acts as a coupler to receive information about the set slave station module in the PLC controller (or other types of programmable logic controller), referred to as configuration setting data, including the slave station module order number and PD length set in the order of the allocation rules, called the second order number and the second PD data length, and each group of the second order number and the second PD data length has an ID number in the order of the allocation rules.

[0068] S32. After the master station module obtains the property setting data of all the slave station modules, the master station module compares the configuration setting data with the property setting data and obtains the comparison result.

[0069] Data comparison includes determining whether the first order number and the second order number of the same slave module are consistent, and whether the lengths of the first PD data and the second PD data match. The comparison is based on comparing the configuration setting data and the attribute setting data with the same ID number.

[0070] The length of the PD data is downward compatible, that is, the length of the first PD data can be less than or equal to the length of the second PD data, and cannot be greater than the length of the second PD data.

[0071] After the data comparison is completed, the master module obtains the corresponding comparison results of each slave module.

[0072] S4. When the data comparison of all lower-level modules is completed, the master station module sends continuous data frames to all slave station modules for data communication based on the comparison results, which specifically includes the following steps: S41. When the comparison result is successful, the master module sets the definition of the slave module to normal, and determines whether the master module needs to send the configuration parameters of the current slave module to the slave module according to the preset data sending rules. The configuration parameters are determined according to the configuration setting data.

[0073] The data sending rule refers to determining whether to send configuration parameters based on the different connected PLC controllers. The master station module will connect to PLC controllers with different protocols. Some protocols can carry configuration parameters themselves, while some cannot. Therefore, whether to send configuration parameters is determined based on the protocol carried by the PLC controller.

[0074] For analog slave modules, the PLC controller can set the configuration parameters for measuring voltage or current.

[0075] S42, determining the command type of the segment data frame of the current slave module according to the result of the judgment, the command type includes sending configuration parameters, sending slave output data and abnormal communication display, and the method of determining the command type specifically includes the following steps: S421, if the result of the judgment is required, the current command type of the slave module is to send configuration parameters, and the master module sends the configuration parameters to the slave module. In a specific implementation method, when the command type is to send configuration parameters, the CMD field in the segment data frame is 0x0B.

[0076] S422, when the configuration parameters are sent, the command type of the current slave module is modified to send slave output data. The slave output data is obtained by the master module from the controller and is used to send to the slave module and control the slave module.

[0077] In a specific implementation method, when the command type is to send slave output data, the CMD field in the segment data frame is 0x06, that is, when the master station module completes sending the configuration parameters of the slave station module, CMD changes from 0x0B to 0x06, and the master station module starts to send slave output data to the slave station module.

[0078] S423: If the result of the judgment is that it is not necessary, the command type of the current slave module is to send slave output data. The master module directly sends the slave output data to the slave module.

[0079] S43. When the comparison result is failure, the master module sets the definition of the slave module as type error, and the command type in the segment data frame of the current slave module is displayed as abnormal communication.

[0080] The reason for the comparison failure is that the first order number and the second order number of the slave module are inconsistent, or the length of the first PD data does not match the length of the second PD data.

[0081] In a specific implementation method, when the command type is abnormal communication display, the CMD field in the segment data frame is 0x0C, indicating that the slave module comparison failed. For the slave module that failed the comparison, the master module will still send continuous data frames to it, and the slave module will control the control system indicator to flash red according to the command of the abnormal communication display, indicating that the slave module has a fault of the wrong type.

[0082] S44. After obtaining the segment data frames of all slave modules, the master module sends continuous data frames to the slave modules.

[0083] The continuous data frame is composed of the segment data frames of all the slave station modules. In a specific implementable embodiment, assuming that there is 1 master station module and 3 slave station modules, the continuous data frame is composed of the segment data frame of the first slave station module + the segment data frame of the second slave station module + the segment data frame of the third slave station module, for example: (AA 01 00 07 06 11 22 CRC AA02 00 07 06 33 44 CRC AA 03 00 07 06 55 66 CRC).

[0084] After receiving the continuous data frame, the slave module intercepts the segment data frame corresponding to its own ID number from the continuous data frame. The specific method of interception is: the slave module is triggered by 0xAA to receive data judgment, and judges whether the next byte of 0xAA is its own ID. After judging that it matches its own ID, it receives the segment data frame length defined by the subsequent two bytes, and receives its own segment data frame according to the segment data frame length.

[0085] After receiving the segment data frame according to the segment data frame length, the received segment data frame is verified to determine whether there is an error in the data transmission process. The specific method of data verification is: the received segment data frame has a given CRC value. At this time, the slave module calculates a new CRC value based on the data content in the segment data frame, and compares the CRC value of the received segment data frame with the calculated new CRC value to see if they are the same. If they are the same, it proves that the verification is passed, otherwise the verification fails. If the verification fails, the slave module returns a received frame CRC error, and the CMD field is 0x10.

[0086] When the master station module sends continuous data frames, it sends the next frame without interval after sending one frame, which can ensure high-speed communication. Even if the data frame changes, it can be sent out immediately, ensuring data update with the highest efficiency.

[0087] S5, while the master station module sends continuous data frames to the slave station module, it also includes the following steps: S51, when the data frame received by the slave module is not any of the allocation ID data frame, the attribute acquisition data frame and the self-existence confirmation data frame, the current slave module enters the continuous receiving and continuous sending state; The allocation ID data frame, the attribute acquisition data frame and the self-existence confirmation data frame are all non-continuous data frames.

[0088] S52, after the slave module enters the continuous receiving and continuous sending state, the slave module continuously sends slave input data to its own superior module through the uplink sending interface. The slave input data is the data generated by the slave module itself.

[0089] It should be noted that the slave input data is different from the slave output data. In the present embodiment, the slave output data is the data sent by the PLC to the slave module through the master module, and the purpose is to control the slave module; while the slave input data is the data sent by the slave module to the master module, and the purpose is to feedback its own data status to the master module. For example, the slave input data can be some digital inputs. The slave module is connected to some sensors, and these sensors will return some values ​​to the PLC. These values ​​are the slave input data. The slave input data can also be some analog inputs such as voltage and current.

[0090] In this embodiment, if the master module sends configuration parameters to the slave module, the slave module will also send a parameter confirmation data frame to the master module, in order to indicate to the master module that it has received the configuration parameters.

[0091] S53, if the current slave module has a subordinate slave module, the slave input data received from the subordinate slave module through the uplink receiving interface is attached to the slave input data of the slave module itself, and after merging, it is sent to the superior module of the slave module through the uplink sending interface, until the slave input data of all the slave module uplink data is merged and sent to the master module. Uplink data is data sent to the master module.

[0092] Since the last slave module has no next-level slave module, it only sends its own data frames, including confirmation parameter data frames and slave input data, through the uplink transmission interface.

[0093] In this embodiment, when all slave modules are in the continuous transmission and continuous reception state, after sending their own data frames plus the uplink data of the lower slave modules received by the downlink receiving interface through the uplink transmission interface, they send their own data frames plus the uplink data of the lower slave modules received by the downlink receiving interface again without interval. The purpose is to ensure the update of data with the highest efficiency, and even if the data frame changes, the updated data frame can be sent out at the fastest speed, avoiding the delay of data update.

[0094] The uplink receiving interface and the uplink sending interface of the slave module work independently. When the uplink sending interface sends a data frame, it does not need to wait for the uplink receiving interface to finish receiving, which can also ensure the data update efficiency.

[0095] Through the above steps, a communication method based on a high-speed backplane system is implemented, so that the data exchange speed between communication modules reaches the fastest, and the communication efficiency between communication modules is improved.

[0096] The above are only optional embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A high-speed backplane system for implementing LVDS communication based on FPGA, comprising a controller and a communication component, wherein the communication component comprises a plurality of communication modules, characterized in that: The communication component specifically includes a master station module and at least one slave station module, the controller is connected to the master station module, the master station module and the slave station module are each provided with an FPGA chip, and the FPGA chip in the master station module is also electrically connected to an MCU; The master station module and the slave station module each include at least one sending interface and one receiving interface, and the master station module and the slave station module interact with each other via an interface component composed of the sending interface and the receiving interface.

2. The high-speed backplane system for implementing LVDS communication based on FPGA according to claim 1, characterized in that: All the communication modules are connected in series, each of the communication modules has at least one corresponding lower-level module or one upper-level module, and the communication modules send and receive the data frames through the interface component, and the data frames include continuous data frames and discontinuous data frames; When the master station module continues to send the continuous data frames to all the slave station modules, all the slave station modules enter a continuous reception and transmission state. When one of the slave station modules has a subordinate module, the slave station module establishes a hardware-triggered forwarding channel to forward the continuous data frames to its own subordinate module without delay.

3. A method for implementing LVDS communication based on FPGA, based on the high-speed backplane system for implementing LVDS communication based on FPGA according to any one of claims 1 or 2, characterized in that: The steps include: All communication modules are started, and all lower-level modules continuously send their own existence data frames to the corresponding upper-level modules, and each of the communication modules determines whether it exists in the lower-level module according to the own existence data frames; Determine all existing slave modules according to all existing subordinate modules, and the master module performs module scanning on all existing slave modules to obtain attribute setting data of all slave modules; The master station module obtains configuration setting data from the controller of the high-speed backplane system, performs data comparison between the configuration setting data and the attribute setting data and obtains a comparison result; When the data comparison of all the lower-level modules is completed, the master station module sends continuous data frames to all the slave station modules for data communication based on the comparison results.

4. The method for realizing LVDS communication based on FPGA according to claim 3, characterized in that: Each of the communication modules determines whether it has the lower-level module according to the data frame that exists in itself, specifically including the following steps: After each of the upper-level modules receives the self-existing data frame sent by the corresponding lower-level module, the upper-level module generates a lower-level module existence flag according to the self-existing data frame and stores it in its own FPGA chip; When the upper module is the master module, the MCU of the master module sends a lower-level existence confirmation data frame to the FPGA chip of the master module, inquiring whether there is a lower-level module existence mark in the FPGA chip. If so, the master module determines that the lower-level module exists in itself; if not, the master module determines that the lower-level module does not exist in itself; When the upper module is the slave module, the master module sends the lower existence confirmation data frame to the current slave module to inquire whether there is a lower module existence mark. If yes, the master module determines that the lower module exists in the current slave module. If not, the master station module determines that the slave station module does not have the lower-level module; All the existing lower-level modules are aggregated to obtain all the slave station modules.

5. The method for realizing LVDS communication based on FPGA according to claim 3, characterized in that: The method of determining all existing slave modules based on all existing subordinate modules, wherein the master module performs module scanning on all existing slave modules to obtain attribute setting data of all slave modules, specifically comprises the following steps: The master station module sends an allocation ID data frame to the corresponding subordinate slave station module. After the slave station module obtains and records the allocated ID number according to the allocation ID data frame, the slave station module sends an allocation success data frame to the master station module through its own sending interface. When the master station module receives the allocation success data frame, it is determined that the ID allocation of the current slave station module is successful. After the ID of the current slave station module is successfully allocated, the master station module sends an attribute acquisition data frame to the current slave station module, and the current slave station module replies with its own attribute setting data to the master station module based on the attribute acquisition data frame. The master station module receives and stores the attribute setting data of the current slave station module, and the attribute setting data includes a first order number and a first PD data length.

6. The method for realizing LVDS communication based on FPGA according to claim 5, characterized in that: After the master station module receives and stores the attribute setting data of the current slave station module, the following steps are also included: After the master module assigns an ID to the slave module as its own subordinate module and obtains the attribute setting data of the slave module, the master module sends the subordinate existence confirmation data frame to the slave module; When the slave module replies to the master module that there is a slave module at the next level, the master module allocates an ID to the slave module currently confirmed to exist according to a preset allocation rule, wherein the allocation rule includes increasing the ID number of the slave module currently confirmed to exist relative to the ID number of the corresponding upper-level module by one, and after allocating the ID number of the slave module currently confirmed to exist, the master module obtains the attribute setting data of the slave module currently confirmed to exist; The master station module stops allocating IDs until the master station module receives a reply from the slave station module that the next-level slave station module does not exist.

7. The method for realizing LVDS communication based on FPGA according to claim 5, characterized in that: The master station module obtains configuration setting data from the controller of the high-speed backplane system, compares the configuration setting data with the attribute setting data and obtains a comparison result, which specifically includes the following steps: The master station module receives configuration setting data sent by the controller of the high-speed backplane system, wherein the configuration setting data includes the second order number and the second PD data length of the slave station module; After the master station module obtains the property setting data of all the slave station modules, the master station module compares the configuration setting data with the property setting data and obtains a comparison result, wherein the data comparison includes determining whether the first order number and the second order number of the same slave station module are consistent, and whether the lengths of the first PD data and the second PD data match; After the data comparison is completed, the master station module obtains the comparison result corresponding to each slave station module.

8. The method for realizing LVDS communication based on FPGA according to claim 5, characterized in that: When the data comparison of all the lower level modules is completed, the master station module sends continuous data frames to all the slave station modules for data communication in combination with the comparison result, including the following steps: When the comparison result is successful, judging whether the master station module needs to send the configuration parameters of the current slave station module to the slave station module according to the preset data sending rules, the configuration parameters are determined according to the configuration setting data, and the command type of the segment data frame of the current slave station module is determined according to the judgment result, and the command type includes sending configuration parameters, sending slave station output data and abnormal communication display; When the comparison result is failure, the command type in the segment data frame of the current slave module is abnormal communication display; After obtaining the segment data frames of all the slave station modules, the master station module sends the continuous data frames to the slave station modules, where the continuous data frames are composed of the segment data frames of all the slave station modules.

9. The method for realizing LVDS communication based on FPGA according to claim 8, characterized in that: Determining the command type of the segment data frame of the current slave module according to the result of the judgment specifically comprises the following steps: If the result of the judgment is that it is necessary, the command type of the current slave module is the sending configuration parameters, and the master module sends the configuration parameters to the slave module. After the configuration parameters are sent, the command type of the current slave module is modified to the sending slave output data, and the slave output data is obtained by the master module from the controller and is used to send to the slave module and control the slave module; If the result of the judgment is that it is not necessary, the command type of the current slave station module is the sending slave station output data.

10. The method for realizing LVDS communication based on FPGA according to claim 8, characterized in that: When the master station module sends the continuous data frames to the slave station module, the following steps are also included: When the data frame received by the slave module is not any one of the allocation ID data frame, the attribute acquisition data frame and the self-existence confirmation data frame, the slave module currently enters a continuous receiving and continuous sending state; After the slave station module enters the continuous reception and continuous transmission state, the slave station module continuously sends slave station input data to its own upper module. The slave station input data is the data generated by the slave station module itself. If the current slave station module has a lower-level slave station module, the slave station input data received from the lower-level slave station module will be attached to its own slave station input data and combined and sent to its own upper module until the slave station input data is sent to the master station module.

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