Signal processing system and method, control device and readable storage medium

Abstract

The invention discloses a signal processing system and method, a control device and a readable storage medium. The system comprises an image sensor; the coding unit is used for acquiring original video stream data and a corresponding original clock frequency; determining a continuity state of the original video stream data, and dividing the original video stream data into continuous data and discontinuous data according to the continuity state; reducing the clock frequency corresponding to the continuous data to the target clock frequency, and keeping the clock frequency corresponding to the discontinuous data as the original clock frequency; packaging the original video stream data into target video stream data and outputting the target video stream data, outputting continuous data at a target clock frequency, and outputting non-continuous data at an original clock frequency; and the decoding unit is used for receiving the target video stream data transmitted remotely and decoding the target video stream data into original video stream data. According to the embodiment of the invention, the stability of video stream long-distance transmission of the ultra-thin wire rod can be improved, the requirements on the material and impedance specification of the transmission wire rod are low, and the cost is low.

Description

Technical Field

[0001] The present application relates to the technical field related to signal processing, and in particular to a signal processing system, method, control device and readable storage medium. Background Art

[0002] In the field of camera biomedicine and industrial detection, it is usually necessary to transmit the video stream detected by the image sensor with the output of the differential signal interface over long distances. The long-distance transmission of the camera video stream will lead to problems such as video stream signal attenuation and high bit error rate, so the requirements for transmission wires are relatively high. For industrial detection scenarios, the existing ordinary wires can already solve the problems of video stream signal attenuation and high bit error rate. However, in biomedical scenarios, such as devices such as human endoscopes, which require extremely fine wires with very large impedance, severe signal attenuation, and inability to transmit video, the material and impedance specifications of the transmission wires will be higher, and the research and development costs of the wires will also be higher. Summary of the invention

[0003] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a signal processing system that can improve the stability of long-distance transmission of video streams of very fine wires, and has low requirements on the material and impedance specifications of the transmission wires and low cost.

[0004] The present application also provides a signal processing method, a control device and a computer-readable storage medium.

[0005] According to the first aspect of the present application, a signal processing system includes: Image sensor for detecting raw video stream data; The encoding unit is used to obtain the original video stream data and the corresponding original clock frequency; determine the continuity state of the original video stream data, and divide the original video stream data into continuous data and discontinuous data according to the continuity state, wherein the continuous data includes at least two continuous data bits and one discontinuous data bit, and the discontinuous data includes two different data bits; reduce the clock frequency corresponding to the continuous data to a target clock frequency, and keep the clock frequency corresponding to the discontinuous data as the original clock frequency; package the original video stream data into target video stream data and output it, wherein the continuous data is output at the target clock frequency, and the discontinuous data is output at the original clock frequency; The decoding unit is used to receive the target video stream data transmitted over a long distance and decode it into the original video stream data.

[0006] The signal processing system according to the embodiment of the present application has at least the following beneficial effects: Since the signal differential potential will be greatly attenuated after the visible signal is transmitted over a long distance, when continuous data bits appear, the differential potential is enlarged, resulting in errors in subsequent data analysis. The embodiment of the present application re-encodes the original video stream data through the encoding unit, first confirms the continuity status of the original video stream data, and then adaptively adjusts the clock frequency to reduce the clock frequency corresponding to the continuous data, and keep the clock frequency corresponding to the discontinuous data unchanged, and then packages it for long-distance transmission to the decoding unit for decoding, which not only allows the mutation data to have more change time to ensure that it can be transmitted correctly, improves the stability of long-distance transmission of the video stream of the ultra-fine wire, but also can transmit data at a high frequency, which has a higher bandwidth than the traditional fixed low-frequency method, can meet the bandwidth requirements of long-distance transmission of ultra-fine wires, and has low requirements on the material and impedance specifications of the transmission wire, and low cost.

[0007] According to some embodiments of the present application, both the encoding unit and the decoding unit adopt FPGA.

[0008] According to a signal processing method of a second aspect of the present application, the method includes: Get the original video stream data and the corresponding original clock frequency; Determine the continuity state of the original video stream data, and divide the original video stream data into continuous data and non-continuous data according to the continuity state, wherein the continuous data includes at least two continuous data bits and one non-continuous data bit, and the non-continuous data includes two different data bits; The clock frequency corresponding to the continuous data is reduced to the target clock frequency, and the clock frequency corresponding to the non-continuous data is maintained at the original clock frequency; The original video stream data is packaged into target video stream data for long-distance transmission, wherein the continuous data is output at the target clock frequency and the non-continuous data is output at the original clock frequency.

[0009] The signal processing method according to the embodiment of the present application has at least the following beneficial effects: Since the signal differential potential will be greatly attenuated after the visible signal is transmitted over a long distance, when continuous data bits appear, the differential potential is enlarged, resulting in errors in subsequent data analysis. The embodiment of the present application re-encodes the original video stream data, first confirms the continuity status of the original video stream data, then adaptively adjusts the clock frequency, reduces the clock frequency corresponding to the continuous data, keeps the clock frequency corresponding to the discontinuous data unchanged, and then packages it for long-distance transmission. This not only allows the mutation data to have more change time to ensure correct transmission, improves the stability of long-distance transmission of the video stream of the ultra-fine wire, but also transmits data at a high frequency, which has a higher bandwidth than the traditional fixed low-frequency method, can meet the bandwidth requirements of long-distance transmission of ultra-fine wires, and has low requirements on the material and impedance specifications of the transmission wire, and low cost.

[0010] According to some embodiments of the present application, the target clock frequency is obtained by the following steps: Determining the number of consecutive data bits in the consecutive data; The target clock frequency is determined according to the number of continuous data bits in the continuous data and the original clock frequency, wherein the number of continuous data bits is negatively correlated with the target clock frequency.

[0011] According to some embodiments of the present application, the method further includes: Determining the number of consecutive data bits in the consecutive data; A plurality of different adjustment percentages are determined based on the number of consecutive data bits in the consecutive data, wherein the number of consecutive data bits is negatively correlated with the size of the adjustment percentage.

[0012] According to some embodiments of the present application, determining the target clock frequency according to the number of consecutive data bits in the consecutive data and the original clock frequency includes: Determining a corresponding target adjustment percentage from a plurality of different adjustment percentages according to the number of continuous data bits in the continuous data; The target clock frequency is determined based on the target adjustment percentage and the original clock frequency.

[0013] According to some embodiments of the present application, determining the target clock frequency based on the target adjustment percentage and the original clock frequency includes: The product of the target adjustment percentage and the original clock frequency is used as the target clock frequency.

[0014] According to some embodiments of the present application, the original clock frequency is the highest transmission clock frequency.

[0015] According to the control device of the third aspect embodiment of the present application, the control device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the signal processing method as described in the second aspect embodiment when executing the computer program. Since the control device adopts all the technical solutions of the signal processing method of the above embodiment, it has at least all the beneficial effects brought by the technical solutions of the above embodiment.

[0016] According to the computer-readable storage medium of the fourth aspect embodiment of the present application, computer-executable instructions are stored, and the computer-executable instructions are used to execute the signal processing method as described in the second aspect embodiment. Since the computer-readable storage medium adopts all the technical solutions of the signal processing method of the above embodiment, it at least has all the beneficial effects brought by the technical solutions of the above embodiment.

[0017] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent from the description, or may be understood by practicing the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which: Figure 1 is a structural block diagram of a signal processing system according to an embodiment of the present application; Figure 2 is a structural block diagram of a coding unit according to an embodiment of the present application; Figure 3 is a structural block diagram of a decoding unit according to an embodiment of the present application; Figure 4 is a flow chart of a signal processing method according to an embodiment of the present application; Figure 5 is a waveform diagram of an output terminal signal of a coding unit in the prior art; Figure 6 It is a waveform diagram of a receiving end signal of a decoding unit in the prior art; Figure 7 is a waveform diagram of an output signal of an encoding unit according to an embodiment of the present application; Figure 8 is a waveform diagram of a receiving end signal of a decoding unit in an embodiment of the present application; Fig. 9 is a waveform diagram of an output signal of the encoding unit corresponding to when the decoding unit of an embodiment of the present application can normally parse the signal; Fig.10 is a waveform diagram of a receiving-end signal of a decoding unit corresponding to when the decoding unit of an embodiment of the present application can normally parse the signal; Fig.11 is a waveform diagram of an output signal of the encoding unit corresponding to when the decoding unit of an embodiment of the present application cannot normally parse the signal; Fig.12 It is a waveform diagram of a receiving-end signal of a decoding unit corresponding to an embodiment of the present application when the decoding unit cannot normally parse the signal.

[0019] Reference numerals: Image sensor 100; The encoding unit 200, the first receiving data unit 210, the transmission protocol parsing unit 220, the effective transmission data processing unit 230, the first effective data buffer unit 240, the first buffer data packet unit 250, the data continuity determination processing unit 260, the clock frequency adaptive processing unit 270, the buffer data secondary packet processing unit 280, and the first output data unit 290; The decoding unit 300 , the second receiving data unit 310 , the data cache processing unit 320 , the high-speed clock parsing data unit 330 , the second valid data cache unit 340 , the second cache data packet unit 350 , the protocol packet unit 360 , and the second output data unit 370 . DETAILED DESCRIPTION

[0020] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0021] In the description of this application, if there is a description of first, second, etc., it is only for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0022] In the description of the present application, it should be understood that the descriptions involving orientation, such as the orientation or positional relationship indicated as up, down, etc., are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0023] In the description of this application, it should be noted that, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meaning of the above terms in this application based on the specific content of the technical solution.

[0024] To facilitate a better understanding of the solutions of the embodiments of the present application, the relevant technologies are first introduced below.

[0025] Differential signaling: An interface standard for high-speed data transmission. It reduces circuit noise and transmission loss by transmitting two opposite signals, positive and negative, simultaneously on the transmission line.

[0026] Camera Serial Interface (Mobile Industry Processor Interface, MIPI): is an interface standard for connecting the image sensor 100 and the image processor. It uses MIPI D-PHY as a physical layer, provides a high-speed image data transmission channel, and supports functions such as multi-channel and multiplexing.

[0027] Field-Programmable Gate Array (FPGA): is a programmable logic device that can configure and reconfigure its internal circuits in real time according to user needs to achieve a variety of different digital logic functions.

[0028] In the field of camera biomedicine and industrial detection, it is usually necessary to carry out long-distance transmission of video streams detected by image sensors 100 outputted with differential signal interfaces. Video stream transmission has high requirements and the frame rate needs to be stable. The traditional MIPI transmission does not exceed 0.3 meters in length, and the conventional video stream transmission based on differential signals does not exceed 1 meter. The long-distance transmission of camera video streams will lead to problems such as video stream signal attenuation and high bit error rate, so the requirements for transmission wires are relatively high. For industrial detection scenarios, existing ordinary wires can already solve problems such as video stream signal attenuation and high bit error rate. However, in biomedical scenarios, such as devices such as human endoscopes, extremely fine wires are required, the impedance is very large, and the signal attenuation is serious (that is, there are problems such as high impedance, high latency, and a significant slowdown in the rise and fall time of the signal edge). The signal no longer meets the differential standard protocol and cannot be parsed through the standard protocol. The video cannot be transmitted, so the material and impedance specifications of the transmission wire will be higher, and the research and development cost of the wire will be higher. In addition, the long-distance transmission bandwidth of wires with a diameter of less than 0.1 mm is extremely low, which cannot meet the scenarios with requirements for the transmission line diameter.

[0029] The following will be combined Figures 1 to 12 A clear and complete description is given of the signal processing system of the embodiment of the present application. Obviously, the embodiment described below is only a part of the embodiments of the present application, not all of the embodiments.

[0030] According to the first aspect of the present application, the signal processing system includes an image sensor 100 , an encoding unit 200 and a decoding unit 300 .

[0031] An image sensor 100 is used to detect raw video stream data; The encoding unit 200 is used to obtain original video stream data and the corresponding original clock frequency; determine the continuity state of the original video stream data, and divide the original video stream data into continuous data and discontinuous data according to the continuity state, wherein the continuous data includes at least two continuous data bits and one discontinuous data bit, and the discontinuous data includes two different data bits; reduce the clock frequency corresponding to the continuous data to a target clock frequency, and keep the clock frequency corresponding to the discontinuous data as the original clock frequency; package the original video stream data into target video stream data and output it, wherein the continuous data is output at the target clock frequency, and the discontinuous data is output at the original clock frequency; The decoding unit 300 is used to receive the target video stream data transmitted over a long distance and decode it into the original video stream data.

[0032] refer to Figure 1 , Figure 1 The structure block diagram of the signal processing system of an embodiment of the present application includes an image sensor 100, an encoding unit 200 and a decoding unit 300. The image sensor 100 is connected to the encoding unit 200 and is located at the detection end side; the encoding unit 200 is connected to the decoding unit 300 through a long-distance transmission line; the output end of the decoding unit 300 is connected to the back-end system platform, and the back-end system platform does not need to consider the limitation of the transmission distance and directly receives the original video stream data output by the decoding unit 300.

[0033] refer to Figure 2 and Figure 3 , Figure 2 is a structural block diagram of a coding unit 200 according to an embodiment of the present application. Figure 3 The structure block diagram of the decoding unit 300 of one embodiment of the present application. The encoding unit 200 includes a first receiving data unit 210, a transmission protocol parsing unit 220, a valid transmission data processing unit 230, a first valid data cache unit 240, a first cache data packet unit 250, a data continuity judgment processing unit 260, a clock frequency adaptive processing unit 270, a cache data secondary packet processing unit 280 and a first output data unit 290. Among them, the data continuity judgment processing unit 260 is used to determine the continuity state of the original video stream data, and divide the original video stream data into continuous data and non-continuous data according to the continuity state; the clock frequency adaptive processing unit 270 is used to reduce the clock frequency corresponding to the continuous data to the target clock frequency, and keep the clock frequency corresponding to the non-continuous data as the original clock frequency. The first receiving data unit 210 is used to receive the MIPI output of the image sensor 100, and the first output data unit 290 is used to output the target video stream data for long-distance transmission of differential signals.

[0034] It should be noted that the working principles and functions of the first receiving data unit 210, the transmission protocol parsing unit 220, the valid transmission data processing unit 230, the first valid data cache unit 240, the first cache data packet unit 250, the cache data secondary packet processing unit 280 and the first output data unit 290 are all existing technologies known to those skilled in the art and will not be elaborated here.

[0035] The decoding unit 300 includes a second receiving data unit 310, a data cache processing unit 320, a high-speed clock parsing data unit 330, a second valid data cache unit 340, a second cache data packet unit 350, a protocol packet unit 360 and a second output data unit 370. It should be noted that the specific structure, working principle and function of the decoding unit 300 are all prior arts known to those skilled in the art, and will not be described in detail here.

[0036] refer to Figure 5 and Figure 6 , Figure 5 is a waveform diagram of an output signal of the encoding unit 200 in the prior art; Figure 6 FIG. 3 is a waveform diagram of a signal at the receiving end of the decoding unit 300 in the prior art. Figure 5 and Figure 6 It can be seen that the signal differential potential will be greatly attenuated after long-distance transmission. When multiple "1" or multiple "0" are transmitted continuously, the differential potential is enlarged, resulting in errors in subsequent data analysis. In order to ensure the correct data transmission, the traditional method is to reduce the clock frequency as a whole, but the bandwidth will be severely limited.

[0037] refer to Figure 7 and Figure 8 , Figure 7 is a waveform diagram of an output signal of the encoding unit 200 according to an embodiment of the present application; Figure 8It is a waveform diagram of the receiving end signal of the decoding unit 300 of an embodiment of the present application. In the encoding unit 200, by determining the continuity state of the original video stream data, the original video stream data can be divided into continuous data and discontinuous data. Continuous data includes at least two continuous data bits and one discontinuous data bit, such as "001", "0001", "11110"; discontinuous data includes two different data bits, such as "01", "10". When multiple "0" or "1" are transmitted continuously, the corresponding clock frequency is dynamically adjusted, the clock frequency corresponding to the continuous data is reduced to the target clock frequency, and the clock frequency corresponding to the discontinuous data is kept at the original clock frequency, that is, when transmitting "001", "0001", "11110", the corresponding clock frequency is reduced, and when transmitting "01", "10", the corresponding clock frequency is kept at the original clock frequency, so that the mutation data has more change time to ensure that it can be transmitted correctly. Compared with the traditional fixed low-frequency method, the embodiment of the present application only reduces the clock frequency corresponding to some data bits, and can transmit data at a high frequency as a whole, with a higher bandwidth, which can meet the bandwidth requirements of long-distance transmission of ultra-thin wires, and has low requirements on the material and impedance specifications of the transmission wires, and low cost. The embodiment of the present application can achieve real-time and stable transmission of long-distance video streams of at least 5 meters to 30 meters.

[0038] In some embodiments of the present application, when determining the continuity state of the original video stream data, the number of continuous data bits in the continuous data is first determined, and then a plurality of different adjustment percentages are determined based on the number of continuous data bits in the continuous data, wherein the number of continuous data bits is negatively correlated with the size of the adjustment percentage. For example, when the continuous data is "001", there are two continuous data bits "00", and the corresponding adjustment percentage is 80%; when the continuous data is "0001", there are three continuous data bits "000", and the corresponding adjustment percentage is 70%; when the continuous data is "11110", there are four continuous data bits "1111", and the corresponding adjustment percentage is 60%. By analogy, the more the number of continuous data bits, the smaller the corresponding adjustment percentage. Then, the corresponding target adjustment percentage is determined from a plurality of different adjustment percentages according to the number of continuous data bits in the continuous data, and the product of the target adjustment percentage and the original clock frequency is used as the target clock frequency. For example, when the continuous data is "001", the transmission frequency is the original clock frequency * 80% for transmission.

[0039] In one embodiment, assuming that the original video stream data is "01011011110", it can be divided into "01", "10", "01", "110", "01", "11110". Accordingly, the clock frequency corresponding to "110" is set to 80% of the original clock frequency, and the clock frequency corresponding to "11110" is set to 60% of the original clock frequency. The clock frequencies corresponding to other non-continuous data remain unchanged at the original clock frequencies.

[0040] It should be noted that the original clock frequency and the target clock frequency are both less than or equal to the maximum transmission clock frequency, and greater than or equal to the minimum transmission clock frequency. The maximum transmission clock frequency can be obtained by continuously increasing the frequency of the differential clock signal until the decoding unit 300 cannot parse the fixed differential data signal, and the minimum transmission clock frequency is not less than the normal non-converting transmission frequency.

[0041] refer to Figures 9 to 12 , Fig. 9 is a waveform diagram of an output signal of the encoding unit 200 corresponding to when the decoding unit 300 of an embodiment of the present application can normally parse the signal; Fig.10 is a waveform diagram of a signal at the receiving end of the decoding unit 300 corresponding to when the decoding unit 300 of an embodiment of the present application can normally parse the signal; Fig.11 is a waveform diagram of an output signal of the encoding unit 200 corresponding to when the decoding unit 300 of an embodiment of the present application cannot normally parse the signal; Fig.12 300 is a waveform diagram of a signal at the receiving end of the decoding unit 300 corresponding to an embodiment of the present application when the decoding unit 300 cannot parse the signal normally. The encoding unit 200 outputs a fixed differential data signal "010101010", and the decoding unit 300 can parse the fixed differential data signal normally, and the parse output is "010101010"; when the decoding unit 300 cannot parse the fixed differential data signal normally, the parse output may be "0001010", such as Fig.12 As shown, two "1"s are missing.

[0042] In an embodiment of the present application, when multiple "1"s or multiple "0"s are transmitted continuously, the differential potential is enlarged, resulting in errors in subsequent data analysis. The more consecutive data bits there are, the higher the error rate. Multiple different adjustment percentages are determined by the number of consecutive data bits. The more consecutive data bits there are, the smaller the corresponding clock frequency is set, which can allow the mutant data to have more change time to ensure correct transmission, thereby further ensuring the correctness of data transmission.

[0043] It should be noted that the method of setting the adjustment percentage is only one embodiment. It can also be that for each additional continuous data bit, a fixed value is subtracted from the original clock frequency. The specific method of reducing the clock frequency cannot be regarded as a limitation of this application.

[0044] In one embodiment, the original clock frequency is the highest transmission clock frequency. When the original clock frequency is the highest transmission clock frequency, on the one hand, the adjustable range of the target clock frequency can be made larger, which means that the clock frequencies corresponding to continuous data with different numbers of continuous data bits can be divided more finely, which can improve the correctness of data transmission. On the other hand, the overall transmission frequency can be increased, thereby increasing the bandwidth.

[0045] According to the signal processing system of the embodiment of the present application, since the signal differential potential will be greatly attenuated after the visible signal is transmitted over a long distance, when continuous data bits appear, the differential potential is enlarged, resulting in errors in subsequent data analysis. The embodiment of the present application re-encodes the original video stream data through the encoding unit 200, first confirms the continuity status of the original video stream data, and then adaptively adjusts the clock frequency, reduces the clock frequency corresponding to the continuous data, keeps the clock frequency corresponding to the discontinuous data unchanged, and then packages it for long-distance transmission to the decoding unit 300 for decoding, which not only allows the mutation data to have more change time to ensure that it can be correctly transmitted, improves the stability of long-distance transmission of the video stream of the ultra-fine wire, but also can transmit data at a high frequency, which has a higher bandwidth than the traditional fixed low-frequency method, can meet the bandwidth requirements of long-distance transmission of ultra-fine wires, and has low requirements on the material and impedance specifications of the transmission wire, and low cost.

[0046] In some embodiments of the present application, both the encoding unit 200 and the decoding unit 300 use FPGA. Traditional network transmission can solve the problem of stable transmission of long-distance video streams, but the circuit module design cannot be very small in area, and the power consumption is also high, which cannot meet the requirements of product volume, and the power consumption and bandwidth of the wireless transceiver module cannot meet the requirements. The embodiment of the present application does not have a driver to increase the encoding and decoding driving capabilities, and directly optimizes the transmission scheme at the FPGA output and input ends. It can be applied to products that have requirements on the size of the device, such as medical endoscopes or industrial endoscopes, and other scenarios that have strict requirements on volume.

[0047] refer to Figure 4 , Figure 4 1 is a flow chart of a signal processing method according to an embodiment of the present application. According to a signal processing method according to an embodiment of the second aspect of the present application, the method includes: Get the original video stream data and the corresponding original clock frequency; Determine the continuity state of the original video stream data, and divide the original video stream data into continuous data and non-continuous data according to the continuity state, wherein the continuous data includes at least two continuous data bits and one non-continuous data bit, and the non-continuous data includes two different data bits; The clock frequency corresponding to the continuous data is reduced to the target clock frequency, and the clock frequency corresponding to the non-continuous data is kept at the original clock frequency; The original video stream data is packaged into target video stream data for long-distance transmission, wherein continuous data is output at the target clock frequency and non-continuous data is output at the original clock frequency.

[0048] from Figure 5 and Figure 6 It can be seen that the signal differential potential will be greatly attenuated after long-distance transmission. When multiple "1" or multiple "0" are transmitted continuously, the differential potential is enlarged, resulting in errors in subsequent data analysis. In order to ensure the correct data transmission, the traditional method is to reduce the clock frequency as a whole, but the bandwidth will be severely limited.

[0049] In an embodiment of the present application, after obtaining the original video stream data, the original video stream data is first re-encoded. By determining the continuity state of the original video stream data, the original video stream data can be divided into continuous data and discontinuous data. Continuous data includes at least two continuous data bits and one discontinuous data bit, such as "001", "0001", "11110"; discontinuous data includes two different data bits, such as "01", "10". When multiple "0" or "1" are transmitted continuously, the corresponding clock frequency is dynamically adjusted, and the clock frequency corresponding to the continuous data is reduced to the target clock frequency, and the clock frequency corresponding to the discontinuous data is kept at the original clock frequency, that is, when transmitting "001", "0001", "11110", the corresponding clock frequency is reduced, and when transmitting "01", "10", the corresponding clock frequency is kept at the original clock frequency, so that the mutation data has more change time to ensure that it can be transmitted correctly. Compared with the traditional fixed low-frequency method, the embodiment of the present application only reduces the clock frequency corresponding to some data bits, and can transmit data at a high frequency as a whole, with a higher bandwidth, which can meet the bandwidth requirements of long-distance transmission of extremely fine wires, and has low requirements on the material and impedance specifications of the transmission wire, and low cost.

[0050] According to the signal processing method of the embodiment of the present application, since the signal differential potential will be greatly attenuated after the visible signal is transmitted over a long distance, when continuous data bits appear, the differential potential is enlarged, resulting in errors in subsequent data analysis. The embodiment of the present application re-encodes the original video stream data, first confirms the continuity status of the original video stream data, then adaptively adjusts the clock frequency, reduces the clock frequency corresponding to the continuous data, keeps the clock frequency corresponding to the discontinuous data unchanged, and then packages it for long-distance transmission. This not only allows the mutation data to have more change time to ensure that it can be transmitted correctly, improves the stability of long-distance transmission of the video stream of the ultra-fine wire, but also can transmit data at a high frequency, which has a higher bandwidth than the traditional fixed low-frequency method, can meet the bandwidth requirements of long-distance transmission of ultra-fine wires, and has low requirements on the material and impedance specifications of the transmission wire, and low cost.

[0051] In some embodiments of the present application, the target clock frequency is obtained by the following steps: determining the number of consecutive data bits in the continuous data; The target clock frequency is determined according to the number of continuous data bits in the continuous data and the original clock frequency, wherein the number of continuous data bits is negatively correlated with the target clock frequency.

[0052] refer to Figure 5 and Figure 6 It can be seen that the signal differential potential will be greatly attenuated after long-distance transmission. When multiple "1" or multiple "0" are transmitted continuously, the differential potential is enlarged, resulting in errors in subsequent data analysis. The more consecutive data bits there are, the higher the error rate. Therefore, the more consecutive data bits there are, the smaller the corresponding target clock frequency is set, which can further ensure the correctness of data transmission.

[0053] In some embodiments of the present application, the method further comprises: determining the number of consecutive data bits in the continuous data; A plurality of different adjustment percentages are determined based on the number of consecutive data bits in the continuous data, wherein the number of consecutive data bits is negatively correlated with the size of the adjustment percentage.

[0054] In one embodiment, when the continuous data is "001", there are two continuous data bits "00", and the corresponding adjustment percentage can be set to 80%; when the continuous data is "0001", there are three continuous data bits "000", and the corresponding adjustment percentage can be set to 70%; when the continuous data is "11110", there are four continuous data bits "1111", and the corresponding adjustment percentage can be set to 60%. By analogy, the more continuous data bits there are, the smaller the corresponding adjustment percentage.

[0055] In one embodiment, assuming that the original video stream data is "01011011110", it can be divided into "01", "10", "01", "110", "01", "11110". Accordingly, the clock frequency corresponding to "110" is set to 80% of the original clock frequency, and the clock frequency corresponding to "11110" is set to 60% of the original clock frequency. The clock frequencies corresponding to other non-continuous data remain unchanged at the original clock frequencies.

[0056] In an embodiment of the present application, when multiple "1"s or multiple "0"s are transmitted continuously, the differential potential is enlarged, resulting in errors in subsequent data analysis. The more consecutive data bits there are, the higher the error rate. Multiple different adjustment percentages are determined by the number of consecutive data bits. The more consecutive data bits there are, the smaller the corresponding clock frequency is set, which can allow the mutant data to have more change time to ensure correct transmission, thereby further ensuring the correctness of data transmission.

[0057] It should be noted that the method of setting the adjustment percentage is only one embodiment. It can also be that for each additional continuous data bit, a fixed value is subtracted from the original clock frequency. The specific method of reducing the clock frequency cannot be regarded as a limitation of this application.

[0058] In some embodiments of the present application, determining the target clock frequency according to the number of consecutive data bits in the continuous data and the original clock frequency includes: Determining a corresponding target adjustment percentage from a plurality of different adjustment percentages according to the number of consecutive data bits in the continuous data; A target clock frequency is determined based on the target adjustment percentage and the original clock frequency.

[0059] In some embodiments of the present application, determining the target clock frequency based on the target adjustment percentage and the original clock frequency includes: taking the product of the target adjustment percentage and the original clock frequency as the target clock frequency.

[0060] In one embodiment, when the continuous data is "001", it is transmitted at a transmission frequency of 80% of the original clock frequency; when the continuous data is "0001", it is transmitted at a transmission frequency of 70% of the original clock frequency; when the continuous data is "00001", it is transmitted at a transmission frequency of 60% of the original clock frequency, and so on.

[0061] It should be noted that the target clock frequency can also be determined by other calculation methods based on the target adjustment percentage and the original clock frequency. As long as the target clock frequency is lower than the original clock frequency, it cannot be regarded as a limitation of the present application.

[0062] In some embodiments of the present application, the original clock frequency is the highest transmission clock frequency. When the original clock frequency is the highest transmission clock frequency, on the one hand, the adjustable range of the target clock frequency can be made larger, which means that the clock frequencies corresponding to continuous data with different numbers of continuous data bits can be divided more finely, which can improve the stability of data transmission. On the other hand, the overall transmission frequency can be increased, thereby increasing the bandwidth.

[0063] In addition, an embodiment of the present application further provides a control device, which includes: a memory, a processor, and a computer program stored in the memory and executable on the processor. The processor and the memory may be connected via a bus or other means.

[0064] The memory, as a non-transient computer-readable storage medium, can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory may optionally include a memory remotely disposed relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0065] The non-transitory software program and instructions required to implement the signal processing method of the above embodiment are stored in the memory, and when executed by the processor, the signal processing method of the above embodiment is executed.

[0066] The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0067] In addition, an embodiment of the present application also provides a computer-readable storage medium, which stores computer-executable instructions, and the computer-executable instructions are executed by a processor or controller, for example, by the above-mentioned processor, so that the above-mentioned processor can execute the signal processing method in the above-mentioned embodiment.

[0068] It will be appreciated by those skilled in the art that all or some of the steps and systems in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or transient medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0069] The embodiments of the present application are described in detail above in conjunction with the accompanying drawings, but the present application is not limited to the above embodiments. Various changes can be made within the knowledge scope of ordinary technicians in the relevant technical field without departing from the purpose of the present application.

Claims

1. A signal processing system, characterized in that: include: Image sensor for detecting raw video stream data; An encoding unit, used for obtaining the original video stream data and the corresponding original clock frequency; Determine the continuity state of the original video stream data, and divide the original video stream data into continuous data and discontinuous data according to the continuity state, wherein the continuous data includes at least two continuous data bits and one discontinuous data bit, and the discontinuous data includes two different data bits; reduce the clock frequency corresponding to the continuous data to a target clock frequency, and keep the clock frequency corresponding to the discontinuous data to the original clock frequency; pack the original video stream data into target video stream data and output them, wherein the continuous data is output at the target clock frequency, and the discontinuous data is output at the original clock frequency; The decoding unit is used to receive the target video stream data transmitted over a long distance and decode it into the original video stream data.

2. The signal processing system according to claim 1, characterized in that The encoding unit and the decoding unit both adopt FPGA.

3. A signal processing method, characterized in that: The method comprises: Get the original video stream data and the corresponding original clock frequency; Determine the continuity state of the original video stream data, and divide the original video stream data into continuous data and non-continuous data according to the continuity state, wherein the continuous data includes at least two continuous data bits and one non-continuous data bit, and the non-continuous data includes two different data bits; The clock frequency corresponding to the continuous data is reduced to the target clock frequency, and the clock frequency corresponding to the non-continuous data is maintained at the original clock frequency; The original video stream data is packaged into target video stream data for long-distance transmission, wherein the continuous data is output at the target clock frequency and the non-continuous data is output at the original clock frequency.

4. The signal processing method according to claim 3, characterized in that: The target clock frequency is obtained by the following steps: Determining the number of consecutive data bits in the consecutive data; The target clock frequency is determined according to the number of continuous data bits in the continuous data and the original clock frequency, wherein the number of continuous data bits is negatively correlated with the target clock frequency.

5. The signal processing method according to claim 4, characterized in that: The method further comprises: Determining the number of consecutive data bits in the consecutive data; A plurality of different adjustment percentages are determined based on the number of continuous data bits in the continuous data, wherein the number of continuous data bits is negatively correlated with the size of the adjustment percentage.

6. The signal processing method according to claim 5, characterized in that: The determining the target clock frequency according to the number of continuous data bits in the continuous data and the original clock frequency comprises: Determining a corresponding target adjustment percentage from a plurality of different adjustment percentages according to the number of continuous data bits in the continuous data; The target clock frequency is determined based on the target adjustment percentage and the original clock frequency.

7. The signal processing method according to claim 6, characterized in that: The determining the target clock frequency based on the target adjustment percentage and the original clock frequency comprises: The product of the target adjustment percentage and the original clock frequency is used as the target clock frequency.

8. The signal processing method according to any one of claims 3 to 7, characterized in that: The original clock frequency is the highest transmission clock frequency.

9. A control device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the signal processing method according to any one of claims 3 to 8 is implemented.

10. A computer-readable storage medium storing computer-executable instructions, characterized in that: The computer executable instructions are used to execute the signal processing method according to any one of claims 3 to 8.

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