Memory preparation method, memory, device and equipment

Abstract

The invention provides a memory preparation method, a memory, a device and equipment, and the method comprises the steps: forming a first active structure, a semiconductor structure and a second active structure which are sequentially stacked on a substrate, and enabling the doping concentration of the first active structure to be the same as the doping concentration of the second active structure, the doping concentration of the semiconductor structure is different from that of the first active structure; forming a first memory based on the first active structure; reversing the first memory and removing the substrate to expose the second active structure and the semiconductor structure; metal materials are deposited on the two sides of the semiconductor structure in the BL area to form a metal structure, and the semiconductor structure is communicated with the adjacent semiconductor structure through the metal structure; and forming a second memory based on the second active structure, the first source drain structure of the first memory and the second source drain structure of the second memory sharing the semiconductor structure and the metal structure. The integration level of the memory can be improved.

Description

Technical Field

[0001] The present application relates to the field of integrated semiconductors, and in particular to a method for preparing a memory, a memory, a device and an apparatus. Background Art

[0002] Dynamic random access memory (DRAM) usually uses a transistor and a capacitor (1T1C) structure as the chip's storage unit. Through the continuous evolution of the architecture, the area of ​​DRAM storage unit is 4F. 2 (F is the feature size.) However, as Moore's Law continues, the area shrinkage of traditional DRAM has encountered a bottleneck, so there is an urgent need for a method that can reduce the area of ​​DRAM storage cells and increase storage density. Summary of the invention

[0003] The present application provides a method for preparing a memory, a memory, a device and an apparatus, which can reduce the area of ​​a storage unit of the memory and improve the storage density and integration.

[0004] In a first aspect, an embodiment of the present application provides a method for preparing a memory, the method comprising: forming a stacked structure on a substrate, the stacked structure comprising: a first active structure, a semiconductor structure and a second active structure stacked in sequence in a first direction, the first active structure being farther away from the substrate than the second active structure, the first active structure, the semiconductor structure and the second active structure being self-aligned along the first direction, the doping concentration of the first active structure being the same as the doping concentration of the second active structure, and the doping concentration of the semiconductor structure being different from the doping concentration of the first active structure; forming a first memory based on the first active structure; flipping the first memory and removing the substrate to expose the second active structure and the semiconductor structure; depositing metal material on both sides of the semiconductor structure in the bit line BL region to form a metal structure, the metal structure connecting the semiconductor structure with an adjacent semiconductor structure; forming a second memory based on the second active structure, wherein a first source-drain structure in the first memory and a second source-drain structure in the second memory share the semiconductor structure and the metal structure.

[0005] In a possible implementation, metal material is deposited on both sides of the semiconductor structure in the bit line BL region to form a metal structure, including: depositing metal material on both sides of the semiconductor structure, the height of the metal material being the height of the semiconductor structure; etching the metal material in the WL region to form a metal structure.

[0006] In one possible implementation, a stacked structure is formed on a substrate, including: stacking a first material layer, a second material layer, and a third material layer in sequence on the substrate; and etching the third material layer, the second material layer, and the first material layer to form a first active structure, a semiconductor structure, and a second active structure.

[0007] In one possible implementation, a first memory is formed based on a first active structure, including: forming a first transistor based on the first active structure; forming a first capacitor structure on the first transistor; and a second memory is formed based on a second active structure, including: forming a second transistor based on the second active structure; and forming a second capacitor structure on the second transistor.

[0008] In one possible embodiment, a first transistor is formed based on a first active structure, including: forming a first gate structure based on the first active structure; removing the first gate structure in the BL region to form a first groove; depositing an insulating material on the first gate structure in the WL region and in the first groove to form a first insulating layer, wherein the upper surface of the first insulating layer is flush with the upper surface of the first mask, and the first mask is located on the first active structure; removing the first mask to form a second groove; and forming a first source-drain structure in the second groove.

[0009] In a possible embodiment, the first gate structure includes a first gate electrode layer and a first gate dielectric layer surrounding the first gate electrode layer, the height of the first gate electrode layer is lower than the height of the first gate dielectric layer; the first gate structure is removed in the BL region to form a first groove, including: forming a sacrificial layer on the first gate electrode layer located in the BL region, the upper surface of the sacrificial layer is flush with the upper surface of the first gate dielectric layer; anisotropically etching the bottom of the sacrificial layer and the first gate electrode layer located below the sacrificial layer to form a first groove.

[0010] In a possible implementation, forming a first capacitor structure on a first transistor includes: forming a first dielectric layer on a first source-drain structure; etching a first portion of the first dielectric layer to expose the first source-drain structure; and forming a first capacitor structure on the first source-drain structure.

[0011] In a second aspect, an embodiment of the present application provides a memory, which is manufactured using the preparation method described in the first aspect and any one of the embodiments thereof, and includes: a BL structure, the BL structure being composed of a semiconductor structure and a metal structure; a first memory; a second memory, the second memory being arranged opposite to the first memory, and the first source-drain structure in the second memory and the second source-drain structure in the first memory sharing the BL structure.

[0012] In a third aspect, an embodiment of the present application provides a semiconductor device, comprising: a memory as described in the second aspect above.

[0013] In a fourth aspect, an embodiment of the present application provides an electronic device, comprising: a circuit board and a semiconductor device as described in the third aspect above, wherein the semiconductor device is arranged on the circuit board.

[0014] In the present application, a stacked structure including a first active structure, a semiconductor structure and a second active structure is formed on a substrate, and then a first memory (front memory) can be prepared based on the front active structure (first active structure); the front memory is flipped and the substrate is removed to expose the first active structure and the semiconductor structure; then a metal material is deposited on both sides of the semiconductor structure in the BL region to form a metal structure, and the metal structure connects the semiconductor structure with the adjacent semiconductor structure; finally, based on the second active structure, a second memory (back memory) is prepared. The embodiment of the present application forms an active structure by etching the BL region and the WL region at one time, thereby ensuring self-alignment of the front and back BL and WL. Through wafer bonding and flipping, the front and back integrated 4F is realized. 2 The equivalent area of ​​the memory is 2F. 2 , which is equivalent to reducing the area of ​​the memory cell of the memory and improving the storage density and integration of the memory.

[0015] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0017] Figure 1 A schematic diagram of an implementation process of a method for preparing a memory in an embodiment of the present application;

[0018] Figure 2 A schematic top view of a memory in an embodiment of the present application;

[0019] Figures 3 to 21 This is a schematic diagram of the structure of the memory in the first preparation process in the embodiment of the present application;

[0020] Fig. 22 This is a schematic diagram of the first structure of the memory in the embodiment of the present application;

[0021] Fig.23 A schematic top view of another memory in an embodiment of the present application;

[0022] Figures 24 to 33 This is a schematic diagram of the structure of the memory in the second preparation process in the embodiment of the present application;

[0023] Fig.34 This is a schematic diagram of the second structure of the memory in the embodiment of the present application.

[0024] The above pictures:

[0025] 10. Memory; 11. First transistor (front transistor); 111. First active structure; 112. First source-drain structure; 113. First gate structure; 1131. First gate dielectric layer; 1132. First gate electrode layer; 12. Second transistor; 121. Second active structure; 122. Second source-drain structure; 123. Second gate structure; 1231. Second gate dielectric layer; 1232. Second gate electrode layer; 13. Third insulating layer; 14. Carrier wafer; 20. Substrate; 21. First material layer; 2 2. Second material layer; 23. Third material layer; 24. First mask; 25. Semiconductor structure; 26. First shallow trench isolation structure; 27. Isolation layer; 28. Sacrificial layer; 29. ​​First groove; 30. First oxide layer; 31. First insulating layer; 32. Second groove; 33. First dielectric layer; 34. First capacitor structure; 35. BL structure; 36. Active structure; 37. Second shallow trench isolation structure; 38. Second oxide layer; 39. Second insulating layer; 40. Second dielectric layer; 41. Second capacitor structure. DETAILED DESCRIPTION

[0026] Here, exemplary embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0027] As Moore's Law continues to deepen, continuing to promote the miniaturization of transistor size is a hot issue in the current industry research and development. Stacked transistors can achieve the integration of two or more layers of transistors in a vertical space through three-dimensional transistor stacking, which helps to further improve the integration density of transistors and improve circuit performance. It is considered to be one of the important technologies for continuing the miniaturization of integrated circuit size. With the continuous development of transistor technology, a flip-chip stacked transistor came into being. The active area of ​​the upper and lower layers of the same source transistors is formed by etching, and the flip-chip stacked transistor is made on the front and back of the wafer by flipping the wafer, which can overcome the shortcomings of the existing solution.

[0028] In DRAM, ferroelectric random access memory (FeRAM) or other memory, a memory cell may include a transistor and a capacitor structure, wherein the transistor is disposed on a substrate, the capacitor structure is located at an end of the transistor away from the substrate, and the transistor and the capacitor structure are electrically connected.

[0029] Take DRAM as an example. The basic structure of DRAM is 1T1C. Currently, there are three main types of DRAM. The first type of DRAM has an area of ​​8F. 2 , which is achieved by placing transistors and capacitors horizontally; the second type of DRAM has an area of ​​6F 2 By tilting the placement of transistors and capacitors, the arrangement density can be increased, thereby achieving a smaller integration area; the area of ​​the third DRAM is 4F 2 By placing transistors and capacitor structures vertically, the vertical volume is fully utilized to achieve smaller DRAM area scaling.

[0030] As integrated circuits continue to shrink in size, there is an urgent need for a method that can reduce the area of ​​a memory cell and increase storage density.

[0031] Based on this, an embodiment of the present application provides a method for preparing a memory, which can reduce the area of ​​a storage unit of the memory and improve the storage density and integration.

[0032] In some embodiments, the memory may include a plurality of memory cells, each of which may include a flip-stack transistor and a capacitance structure (capacitor), wherein the capacitance structure is electrically connected to the flip-stack transistor.

[0033] In some embodiments, the flip-stacked transistor may include a gate structure, a source structure, and a drain structure. The capacitor structure and the flip-stacked transistor may be electrically connected by the source structure of the flip-stacked transistor and the capacitor structure, or by the drain structure of the flip-stacked transistor and the capacitor structure. The flip-stacked transistor controls the writing, modification, or reading of information in the capacitor structure. That is, the flip-stacked transistor acts as a selection device (or a switching device) to control the writing, modification, or reading of information in the capacitor structure.

[0034] In some embodiments, the capacitor structure may include a first electrode, a second electrode, and a capacitor dielectric layer between the first electrode and the second electrode. Exemplarily, the first electrode may be electrically connected to the drain structure of the flip-chip stack transistor, and the second electrode may be grounded.

[0035] In some embodiments, the memory cell may further include a plurality of word line (WL) structures and a plurality of bit line (BL) structures, wherein the WL structure and the BL structure are arranged vertically. The WL structure may be connected to the gate structure of the flip-stacked transistor to control the on and off of the flip-stacked transistor. The BL structure may be connected to the source structure or the drain structure of the flip-stacked transistor to write data to the capacitor structure connected to the flip-stacked transistor when the flip-stacked transistor is turned on.

[0036] In some embodiments, a flip-chip stacked transistor may include at least two transistors. Taking a first transistor and a second transistor as an example, the first transistor and the second transistor are arranged back to back, and a first active structure of the first transistor and a second active structure of the second transistor are formed by the same process. Therefore, it can be understood that the first transistor and the second transistor share an active structure.

[0037] In the embodiment of the present application, the first transistor and the second transistor in the flip-chip stacked transistor are transistors of the same type, such as vertical channel transistors (VCT), which may also be referred to as vertical gate-all-around transistors.

[0038] Figure 1 FIG. 1 is a schematic diagram of an implementation process of a method for preparing a memory in an embodiment of the present application. Figure 1 As shown, the method for preparing the memory in the embodiment of the present application may include:

[0039] Step S110: forming a stacking structure on a substrate.

[0040] The stacked structure includes: a first active structure, a semiconductor structure and a second active structure stacked in sequence in a first direction, the first active structure is farther away from the substrate than the second active structure, and the first active structure, the semiconductor structure and the second active structure are self-aligned along the first direction.

[0041] In some embodiments, the implementation process of step S110 can be divided into the following two steps: step one: stacking a first material layer, a second material layer and a third material layer in sequence on a substrate; step two: etching the third material layer, the second material layer and the first material layer to form a first active structure, a semiconductor structure and a second active structure.

[0042] In step 1, the first material layer and the third material layer are doped in the same manner, and the doping concentration of the second material layer is different from the doping concentration of the first material layer.

[0043] By way of example, the substrate may be any semiconductor substrate such as a silicon substrate, a germanium substrate, a silicon-germanium substrate, or a silicon carbide substrate.

[0044] It can be understood that the first material layer and the third material layer have the same doping, and the doping concentration of the second material layer is different from the doping concentration of the first material layer. In this way, the first material layer and the third material layer with the same doping can be subsequently etched to serve as an active structure shared by the front transistor (first transistor) and the back transistor (second transistor) in the flip-chip stacked transistor, and the second material layer with a different doping can be used as the BL structure of the memory.

[0045] In some embodiments, the doping concentration of the second material layer may be higher than the doping concentration of the first material layer. As a channel for data transmission, the doping concentration of the BL structure mainly affects the efficiency and noise performance of data transmission. A higher doping concentration can improve the conductivity of the BL structure, reduce resistance, and thus speed up data transmission.

[0046] Since the memory cell of the memory includes the WL region and the BL region, after the first material layer, the second material layer and the third material layer are sequentially stacked on the substrate, the material layers in the WL region and the BL region can be etched to form an active structure.

[0047] In some embodiments, the implementation process of step 2 may be: forming a first mask on the third material layer, the first mask is used to locate the WL region and the BL region; based on the first mask, etching the third material layer, the second material layer and the first material layer to form a first active structure, a semiconductor structure and a second active structure. That is, after forming the mask by photolithography, etching is performed along the BL direction and the WL direction at the same time, so that self-alignment of the BL region and the WL region can be ensured.

[0048] It can be understood that a first mask is formed on the third material layer, and the first mask is used to locate the WL region and the BL region, so the first mask covers a portion of the third material layer in both the WL region and the BL region, and thus the third material layer, the second material layer and the first material layer are etched based on the first mask to form a first active structure, a semiconductor structure and a second active structure. The semiconductor structure is not connected in both the WL region and the BL region.

[0049] For example, the etching process may be at least one of dry etching, wet etching, reactive ion etching, etc.

[0050] In some embodiments, after forming the first active structure, the semiconductor structure, and the second active structure, an oxide material may be deposited on the substrate to form a first shallow trench isolation (STI) structure.

[0051] It is understandable that an oxide material can be deposited on the substrate and thinned to a preset height so that the upper surface of the formed first shallow trench isolation structure is higher than the upper surface of the semiconductor structure and the gate structure of the front transistor is exposed, so as to subsequently prepare the gate structure of the front transistor. Among them, the oxide material forming the shallow trench isolation structure can be exemplarily any of the following: silicon nitride (SiN, Si3N4), silicon dioxide (SiO2) or silicon oxycarbide (SiCO), etc. The thinning process can be exemplarily a process such as chemical-mechanical planarization (CMP).

[0052] Step S120: forming a first memory based on the first active structure.

[0053] In some embodiments, the implementation process of step S120 may include the following two steps: forming a first transistor based on the first active structure; and forming a first capacitor structure on the first transistor.

[0054] In some embodiments, based on the first active structure, the implementation process of forming the first transistor can be: based on the first active structure, forming a first gate structure; removing the first gate structure in the BL region to form a first groove; depositing an insulating material on the first gate structure in the WL region and in the first groove to form a first insulating layer, and the upper surface of the first insulating layer is flush with the upper surface of the first mask; removing the first mask to form a second groove; forming a first source-drain structure in the second groove.

[0055] It can be understood that after thinning the first shallow trench isolation structure to a preset height, the gate region of the front transistor is exposed, that is, a first gate groove is formed between the first active structure, so that an insulating material can be deposited at the first gate groove to form a first gate dielectric layer, and a metal material can be deposited on the first gate dielectric layer to form a first gate electrode layer. The first gate electrode layer and the first gate dielectric layer surrounding the first gate electrode layer together constitute a first gate structure. The height of the first gate dielectric layer can be higher than the height of the first gate electrode layer.

[0056] For example, the first gate dielectric layer may be composed of a silicon oxide layer and a hafnium oxide layer with a high K value, and the thicknesses of the silicon oxide layer and the hafnium oxide layer may be determined according to the polarity and performance of the transistor.

[0057] By way of example, the first gate electrode layer may be composed of multiple layers of electrode materials, and the electrode material of each layer includes but is not limited to hafnium, zirconium, titanium, tantalum, aluminum, and alloys of these metals.

[0058] Since the WL structure in the WL region is connected to the gate structure of the transistor, the first gate structure in the WL region is necessary, while the first gate structure in the BL region may not exist, and thus the first gate structure in the BL region may be selectively removed.

[0059] In some embodiments, the first gate structure is removed in the BL region to form a first groove by: forming a sacrificial layer on the first gate electrode layer in the BL region, wherein the upper surface of the sacrificial layer is flush with the upper surface of the first gate dielectric layer; and anisotropically etching the bottom of the sacrificial layer and the first gate electrode layer below the sacrificial layer to form a first groove.

[0060] It can be understood that a sacrificial layer attached to the bottom of the first gate electrode layer, the sidewall of the first gate dielectric layer, and the sidewall of the first mask can be deposited on the first gate electrode layer in the BL region, and the upper surface of the sacrificial layer is flush with the upper surface of the first gate dielectric layer, and then the bottom of the sacrificial layer and the first gate electrode layer below the sacrificial layer are anisotropically etched to obtain a first groove. Since the anisotropic etching is etched downward from the bottom of the sacrificial layer, and a portion of the first gate electrode layer still exists below the sidewall of the sacrificial layer, this portion of the first gate electrode layer is retained.

[0061] The insulating material may be, for example, oxide, nitride, etc. When depositing the sacrificial layer, a very thin film may be deposited on the surface of the substrate by atomic layer deposition (ALD).

[0062] In some embodiments, after the first recess is formed, the sacrificial layer may be removed.

[0063] It can be understood that after forming the first groove, an insulating material can be deposited on the first gate structure in the WL region and in the first groove to form a first insulating layer, and the upper surface of the first insulating layer is flush with the upper surface of the first mask. The first mask can then be removed to form a second groove, and a first source-drain structure of the front transistor is formed in the second groove. Among them, the first insulating layer is used to isolate the first source-drain structure of the front transistor. In the case where the transistor formed in the embodiment of the present application is a VCT, the source structure and drain structure of the VCT are approximately symmetrical. Therefore, for ease of explanation, the first source-drain structure mentioned in the embodiment of the present application is a short name, specifically referring to the first source structure and / or the first drain structure. In addition, the same is true for the second source-drain structure that appears later.

[0064] For example, ion implantation can be performed in the second groove to deposit metal material, and then annealing can be performed to form silicide, and the silicide can be used as the first source-drain structure. This is only an exemplary description, and can be determined as needed in actual operation. When the silicide is used as the first source structure, the BL structure can be used as the first drain structure. When the silicide is used as the first drain structure, the BL structure can be used as the first source structure.

[0065] In some embodiments, an insulating material may be deposited on the first gate structure in the WL region to form an isolation layer so that only the BL region is processed. In this way, after removing the sacrificial layer, the isolation layer above the WL region may be removed so that a first insulating layer is formed on both the WL region and the BL region.

[0066] In some embodiments, after removing the sacrificial layer, an oxide material may be deposited in the first groove in the BL region to form a first oxide layer. Then, a first insulating layer is formed on the first oxide layer in the BL region and the first gate structure in the WL region. The first oxide layer may also be formed by ALD deposition, for example.

[0067] After the first source-drain structure is formed, a capacitor structure of a front-side memory may be formed on the front-side transistor.

[0068] In some embodiments, the implementation process of forming the first capacitor structure on the first transistor may be: forming a first dielectric layer on the first source-drain structure; etching a first portion of the first dielectric layer to expose the first source-drain structure; and forming the first capacitor structure on the first source-drain structure.

[0069] It can be understood that an insulating dielectric can be deposited on the first source-drain structure to form a first dielectric layer, and then a portion of the first dielectric layer is etched to expose the first source-drain structure below, and a layer of metal material is first deposited on the first source-drain structure, and then a dielectric material is deposited, and then another layer of metal material is deposited, so that a first capacitor structure including a first electrode and a second electrode, and a capacitor dielectric layer located between the first electrode and the second electrode can be formed, and thus the front memory can be prepared. Among them, the first dielectric layer located between the first capacitor structures can serve as an isolation structure between the first capacitor structures.

[0070] Step S130: flipping the first memory and removing the substrate to expose the second active structure and the semiconductor structure.

[0071] In some embodiments, the implementation process of step S130 may be: flipping the first memory and removing the substrate; thinning the first shallow trench isolation structure to a preset height to expose the second active structure and the semiconductor structure, and the thinned first shallow trench isolation structure is used to isolate the first transistor from the second transistor.

[0072] It can be understood that after the first capacitor structure is formed, the first capacitor structure can be bonded to the carrier wafer, and then the first capacitor structure can be flipped over, and the substrate can be removed and the first shallow trench isolation structure can be thinned to expose the second active structure and the semiconductor structure, so as to facilitate the subsequent formation of the BL structure and the preparation of the back side memory.

[0073] In some embodiments, an insulating material (such as silicon oxide) may be deposited on the first capacitor structure to form a third insulating layer, and the third insulating layer may be bonded to the carrier wafer, after which the first capacitor structure may be flipped over and the substrate may be removed.

[0074] After removing the substrate, the upper surface of the second active structure is flush with the upper surface of the first shallow trench isolation structure, so the first shallow trench isolation structure can be thinned to a preset height to expose the semiconductor structure. The preset height can be set according to actual needs, and the embodiment of the present application does not limit this.

[0075] Step S140 : depositing metal material on both sides of the semiconductor structure in the BL region to form a metal structure.

[0076] It can be understood that the semiconductor structure in step S110 is not connected in the BL region and the WL region, while the BL structure in the memory is not connected in the WL region but is connected in the BL region. Therefore, the embodiment of the present application deposits metal material between the semiconductor structures in the BL region to form a metal structure, and connects adjacent semiconductor structures through the metal structure. In this way, a BL structure including a semiconductor structure and a metal structure can be formed, and the semiconductor structure in the WL region is not affected.

[0077] In some embodiments, the implementation process of step S140 may be: depositing metal material on both sides of the semiconductor structure, the height of the metal material being the height of the semiconductor structure; and etching the metal material in the WL region to form a metal structure.

[0078] It can be understood that metal materials can be first deposited on both sides of the semiconductor structures in the WL region and the BL region, and then the metal materials in the WL region are etched, and the metal materials in the BL region are retained. Since the height of the metal material is the height of the semiconductor structure, the semiconductor structures in the BL region can be connected through the metal material, and the metal materials between the semiconductor structures in the WL region are removed to prevent short circuits, so that a metal structure can be formed.

[0079] In some embodiments, metal materials can also be deposited in both the WL region and the BL region, but due to the layout design and process manufacturing, the coverage area of ​​metal deposition in the BL region and the WL region is different. The metal material in the BL region can fill both sides of the semiconductor structure and the second active structure, that is, fill the grooves between the adjacent semiconductor structures and the second active structure, while the metal material in the WL region only covers the surfaces on both sides of the semiconductor structure and the second active structure. Afterwards, the metal materials in the two regions can be etched by anisotropic etching, and the etching rate is strictly controlled so that there is enough metal material at the semiconductor structure in the BL region to achieve conduction of the BL structure, while the metal material at the semiconductor structure in the WL region is removed to prevent short circuit between the BL and the WL.

[0080] In some embodiments, the metal material may be deposited by ALD deposition.

[0081] In some embodiments, after the BL structure is formed, an oxide material may be deposited on the BL structure in the BL region and the first shallow trench isolation structure in the WL region to form a second shallow trench isolation structure.

[0082] It is understandable that after forming the second shallow trench isolation structure, the third shallow trench isolation structure may be thinned to a preset height to expose the gate region of the back transistor so as to subsequently prepare the gate structure of the back transistor.

[0083] Step S150: forming a second memory based on the second active structure.

[0084] In some embodiments, the implementation process of step S150 may include the following two steps: forming a second transistor based on the second active structure; and forming a second capacitor structure on the second transistor.

[0085] In some embodiments, based on the second active structure, the implementation process of forming the second transistor can be: based on the second active structure, forming a second gate structure; removing the second gate structure in the BL region to form a third groove; depositing an insulating material on the second gate structure in the WL region and in the second groove to form a second insulating layer, the upper surface of the second insulating layer is flush with the upper surface of the second mask, and the second mask is located on the second active structure; removing the second mask to form a fourth groove; forming a second source and drain structure in the fourth groove.

[0086] It can be understood that after thinning the second shallow trench isolation structure to a preset height, the gate region of the back transistor is exposed, that is, a second gate groove is formed between the second active structure, so that an insulating material can be deposited at the second gate groove to form a second gate dielectric layer, and a metal material can be deposited on the second gate dielectric layer to form a second gate electrode layer. The second gate dielectric layer and the second gate electrode layer together constitute a second gate structure. The height of the second gate dielectric layer can be higher than the height of the second gate electrode layer.

[0087] In some embodiments, the second gate structure is removed in the BL region to form a third groove by: forming a sacrificial layer on the second gate electrode layer located in the BL region, wherein the upper surface of the sacrificial layer is flush with the upper surface of the second gate dielectric layer; and anisotropically etching the bottom of the sacrificial layer and the second gate electrode layer located below the sacrificial layer to form a third groove.

[0088] It can be understood that a sacrificial layer attached to the bottom of the second gate electrode layer, the sidewall of the second gate dielectric layer, and the sidewall of the second mask can be deposited on the second gate electrode layer in the BL region, and the upper surface of the sacrificial layer is flush with the upper surface of the second gate dielectric layer, and then the bottom of the sacrificial layer and the second gate electrode layer below the sacrificial layer are anisotropically etched to obtain a third groove. Since the anisotropic etching is etched downward from the bottom of the sacrificial layer, and a portion of the second gate electrode layer still exists below the sidewall of the sacrificial layer, this portion of the second gate electrode layer is retained.

[0089] In some embodiments, after the third recess is formed, the sacrificial layer may be removed.

[0090] In some embodiments, before forming the second insulating layer, a second mask may be formed on the second active structure in the WL region and the BL region, and the width of the second mask is the same as the width of the second active structure. After forming the third groove, an insulating material may be deposited on the second gate structure in the WL region and in the third groove to form a second insulating layer, and the upper surface of the second insulating layer is flush with the upper surface of the second mask. The second mask may then be removed to form a fourth groove, and a second source-drain structure of the back transistor may be formed in the fourth groove.

[0091] In some embodiments, an insulating material may be deposited on the second gate structure in the WL region to form an isolation layer so that only the BL region is processed. In this way, after removing the sacrificial layer, the isolation layer above the WL region may be removed so that a second insulating layer is formed on both the WL region and the BL region.

[0092] In some embodiments, after removing the sacrificial layer, an oxide material may be deposited in the third groove in the BL region to form a second oxide layer. Then, a second insulating layer is formed on the second oxide layer in the BL region and the second gate structure in the WL region. The second oxide layer may also be formed by ALD deposition, for example.

[0093] After the second source-drain structure is formed, a capacitor structure of a back side memory may be formed on the back side transistor.

[0094] In some embodiments, the implementation process of forming the second capacitor structure on the second transistor may be: forming a second dielectric layer on the second source-drain structure; etching a first portion of the second dielectric layer to expose the second source-drain structure; and forming a second capacitor structure on the second source-drain structure.

[0095] It can be understood that an insulating dielectric can be deposited on the second source-drain structure to form a second dielectric layer, and then a portion of the second dielectric layer is etched to expose the second source-drain structure below, and a layer of metal material is first deposited on the second source-drain structure, and then a dielectric material is deposited, and then another layer of metal material is deposited, so that a second capacitor structure including a first electrode and a second electrode, and a capacitor dielectric layer located between the first electrode and the second electrode can be formed, and thus the back side memory can be prepared. Among them, the second dielectric layer located between the second capacitor structures can serve as an isolation structure between the second capacitor structures.

[0096] In addition, in some embodiments, the spacing between the BL structures and the spacing between the WL structures in the embodiments of the present application can be the same or different, as long as the product of the spacing between the two is 4F 2 For example, the spacing between the BL structures and the spacing between the WL structures are both 2F, or the spacing between the BL structures is 4F, and the spacing between the WL structures is F. This embodiment of the application is not limited to this.

[0097] In the present application, a stacked structure including a first active structure, a semiconductor structure and a second active structure is formed on a substrate, and then a first memory (front memory) can be prepared based on the front active structure (first active structure); the front memory is flipped and the substrate is removed to expose the first active structure and the semiconductor structure; then a metal material is deposited on both sides of the semiconductor structure in the BL region to form a metal structure; finally, based on the second active structure, a second memory (back memory) is prepared. The embodiment of the present application forms an active structure by etching the BL region and the WL region at one time, ensuring self-alignment of the front and back BL and WL. Through wafer bonding and flipping, two storage units of 4F2 size are integrated on the front and back sides, so the equivalent area of ​​the memory is 2F2, which is equivalent to reducing the area of ​​the storage unit of the memory and improving the storage density and integration of the memory. In addition, the embodiment of the present application can also realize the diversification of the memory structure by changing the spacing between the BL structure and the WL structure.

[0098] The following uses the nanowire structure as an example to illustrate the preparation method of the memory provided by the embodiment of the present application. First, the first preparation process is introduced, that is, the active structure of the transistor in the memory is still a standard nanowire structure, and the spacing between the WL structure and the BL structure is different. Figure 2 This is a schematic top view of a memory in an embodiment of the present application. It should be noted that, for ease of understanding, only the nanowire structure, BL structure and WL structure are shown in the top view. The AA' direction is the cross-sectional direction of the memory along the BL structure; the BB' direction is the cross-sectional direction of the memory along the WL structure. Figures 3 to 21This is a schematic diagram of the structure of the memory in the first preparation process in the embodiment of the present application. Fig. 22 This is a schematic diagram of the first structure of the memory in the embodiment of the present application. Figures 3 to 22 (a) is a cross-sectional view of the memory along the cross-sectional direction of the BL structure (i.e., the AA' direction). Figures 3 to 22 (b) is a cross-sectional view of the memory along the cross-sectional direction of the WL structure (ie, the BB' direction).

[0099] In one example, the preparation process of the memory 10 may include the following steps:

[0100] Step 1: Form a first material layer 21, a second material layer 22 and a third material layer 23 on the original substrate 20 in sequence to obtain Figure 3 The structure shown.

[0101] The first material layer and the third material layer are doped in the same manner, and the doping concentration of the second material layer is higher than that of the first material layer.

[0102] For example, a layer of highly doped silicon may be epitaxially grown on a silicon substrate as the BL structure of the memory, and then a thicker layer of low-doped silicon may be epitaxially grown on this basis to prepare for the front-side memory device.

[0103] Step 2: Form a first mask 24 on the third material layer 23. The first mask 24 is used to define the active structures of the WL and BL regions. Then, based on the first mask 24, the third material layer 23, the second material layer 22 and the first material layer 21 are sequentially etched until the substrate 20 to form a self-aligned first active structure 111, a semiconductor structure 25 and a second active structure 121. Figure 4 The structure shown.

[0104] It can be understood that etching is performed simultaneously in the WL region and the BL region, so that self-alignment of the BL and the WL can be ensured.

[0105] Step 3: Deposit an oxide material on the substrate 20 to form a first shallow trench isolation structure 26, and perform CMP and etching to expose the front transistor to obtain Figure 5 The structure shown.

[0106] Step 4: selectively deposit an insulating material on the surface of the first active structure 111 to form a first gate dielectric layer 1131, thereby obtaining Figure 6 The structure shown.

[0107] Step 5: Deposit metal material on the first gate dielectric layer 1131 and perform CMP to a certain height to form a first gate electrode layer 1132. Figure 7 The structure shown.

[0108] The first gate dielectric layer 1131 and the first gate electrode layer 1132 constitute a first gate structure 113 , and the height of the first gate dielectric layer 1131 is higher than the height of the first gate electrode layer 1132 .

[0109] Step 6: Form an isolation layer 27 by photolithography and etching to cover the WL region so that only the BL region can be processed later. Figure 8 The structure shown.

[0110] Step 7: Deposit a sacrificial layer 28 on the first gate electrode layer 1132 and attached to the bottom of the first gate electrode layer 1132, the sidewall of the first gate dielectric layer 1131, and the sidewall of the first mask 24 to obtain Fig. 9 The structure shown.

[0111] Step 8: Anisotropically etch the bottom of the sacrificial layer 28 and the first gate electrode layer 1132 located below the sacrificial layer 28, then remove the sacrificial layer 28 to form a first groove 29, and obtain Fig.10 The structure shown.

[0112] It can be understood that the anisotropic etching is performed from the bottom of the sacrificial layer downwards, and a portion of the first gate electrode layer still exists under the sidewall of the sacrificial layer.

[0113] For example, when depositing the sacrificial layer, a very thin sacrificial layer may be deposited on the surface of the substrate by ALD deposition.

[0114] Step 9: Deposit an oxide material in the first groove 29 to form a first oxide layer 30, and obtain Fig.11 The structure shown.

[0115] Step 10: Remove the isolation layer 27 above the WL region, and deposit an insulating material (such as SiN) in the two regions to form a first insulating layer 31, so as to obtain Fig.12 The structure shown.

[0116] Step 11: Selectively etch the first mask 24 to form a second groove 32, and obtain Fig.13 The structure shown.

[0117] Step 12: forming a first source-drain structure 112 in the second groove 32, and depositing an insulating dielectric on the first source-drain structure 112 to form a first dielectric layer 33, so as to obtain Fig.14 The structure shown.

[0118] For example, ion implantation may be performed in the second groove 32 to deposit a metal material, which is then annealed to form silicide, and the silicide is used as the first source-drain structure.

[0119] Step 13: Etch a portion of the first dielectric layer 33 to expose the first source-drain structure 112, and form a first capacitor structure 34 on the first source-drain structure 112 to obtain Fig.15 The structure shown.

[0120] The first capacitor structure may include deposition of a metal upper plate, deposition of a dielectric layer, and deposition of a metal lower plate. Fig.15 This is a simplified representation only.

[0121] Step 14: Deposit insulating material on the first capacitor structure 34 to form a third insulating layer 13, and bond the third insulating layer 13 to the carrier wafer 14, and then flip the wafer to obtain the following: Fig.16 The structure shown.

[0122] Step 15: Remove the substrate 20 to the first shallow trench isolation structure 26 to obtain Fig.17 The structure shown.

[0123] Step 16: Thin the first shallow trench isolation structure 26 to the bottom of the semiconductor structure 25 to obtain Fig.18 The structure shown.

[0124] Step 17: Deposit metal materials in the WL region and the BL region simultaneously to obtain the following Fig.19 The structure shown.

[0125] It can be understood that, since the spacing of the active structures along the BL direction in the top view of the first preparation process is small, the deposited metal material is sufficient to fill the grooves between the adjacent second active structures 121 and the semiconductor structure 25, corresponding to Fig.19 (a). The spacing between the active structures along the WL direction is large, so the deposited metal material cannot fill the entire groove and can only cover the surface of the second active structure 121 and the semiconductor structure 25, corresponding to Fig.19 (b) For example, the metal material may be deposited by ALD.

[0126] Step 18: Anisotropically etch the metal material to form a BL structure 35, as shown in FIG. Fig. 20 The structure shown.

[0127] It can be understood that by anisotropically etching the metal material and strictly controlling the etching rate, there is enough metal material in the BL area, and the metal in the WL area is removed to prevent short circuit. Fig. 20 As shown in (a) and (b), the BL structure connects the semiconductor structure through the metal material in the BL region, but not in the WL region. Fig. 20(c) is a top view schematic diagram of the memory structure, the active structure 36 includes a first active structure 111 and a second active structure 121, the length of the active structure 36 along the WL direction and the BL direction is jointly determined by the metal deposition and etching processes, the spacing between the WL structure and the BL structure is different, and F and 4F here are only examples.

[0128] Step 19: Deposit an oxide material on the BL structure in the BL region and the first shallow trench isolation structure in the WL region and perform CMP to a certain height to form a second shallow trench isolation structure 37, and obtain Fig.21 The structure shown.

[0129] Step 20: Prepare a second transistor and a second capacitor structure 41 to obtain Fig. 22 The structure shown.

[0130] It can be understood that first, a second mask can be formed on the second active structure 121, and then an insulating material is selectively deposited on the surface of the second active structure 121 to form a second gate dielectric layer 1231. A metal material is deposited on the second gate dielectric layer 1231 and CMPed to a certain height to form a second gate electrode layer 1232, so as to form a second gate structure 123. Then, an isolation layer is formed by photolithography and etching to cover the WL region, so as to facilitate processing of the BL region. Afterwards, a sacrificial layer attached to the bottom of the second gate electrode layer 1242, the sidewalls of the second gate dielectric layer 1231, and the sidewalls of the second mask may be deposited on the second gate electrode layer 1232, the bottom of the sacrificial layer and the second gate electrode layer 1232 located below the sacrificial layer may be anisotropically etched, and then the sacrificial layer may be removed to form a groove, and an oxide material may be deposited in the groove to form a second oxide layer 38, the isolation layer above the WL region may be removed, an insulating material (such as SiN) may be deposited in the two regions to form a second insulating layer 39, the second mask may be selectively etched to form a groove, a second source-drain structure 122 may be formed in the groove, and an insulating dielectric may be deposited on the second source-drain structure 122 to form a second dielectric layer 40, a portion of the second dielectric layer 40 may be etched to expose the second source-drain structure 122, and a second capacitor structure 41 may be formed on the second source-drain structure 122. Here, the second drain structure of the second transistor is connected to the BL structure 35, and the second source structure of the second transistor is connected to the second capacitor structure 41.

[0131] You can refer to steps 4 to 13 here.

[0132] The second preparation process is described below, that is, the active structure of the transistor in the memory is still a nanosheet structure, but the length and width of the cross section of the nanosheet structure are different. The spacing between the WL structure and the BL structure is the same. Fig.23This is a top view schematic diagram of another memory in the embodiment of the present application. It should be noted that for ease of understanding, only the nanosheet structure, BL structure and WL structure are shown in the top view. The AA' direction is the cross-sectional direction of the memory along the BL structure; the BB' direction is the cross-sectional direction of the memory along the WL structure. Figures 24 to 33 This is a schematic diagram of the structure of the memory in the second preparation process in the embodiment of the present application. Fig.34 This is a schematic diagram of the second structure of the memory in the embodiment of the present application. Figures 24 to 34 (a) is a cross-sectional view of the memory along the cross-sectional direction of the BL structure (i.e., the AA' direction). Figures 24 to 34 (b) is a cross-sectional view of the memory along the cross-sectional direction of the WL structure (ie, the BB' direction).

[0133] In one example, the preparation process of the memory 10 may include the following steps:

[0134] Step 1: Form a first material layer 21, a second material layer 22 and a third material layer 23 on the original substrate 20 in sequence to obtain Fig.24 The structure shown.

[0135] The first material layer and the third material layer are doped in the same manner, and the doping concentration of the second material layer is higher than that of the first material layer.

[0136] For example, a layer of highly doped silicon may be epitaxially grown on a silicon substrate as the BL structure of the memory, and then a thicker layer of low-doped silicon may be epitaxially grown on this basis to prepare for the front-side memory device.

[0137] Step 2: Form a first mask 24 on the third material layer 23. The first mask 24 is used to define the active structures of the WL and BL regions. Then, based on the first mask 24, the third material layer 23, the second material layer 22 and the first material layer 21 are sequentially etched until the substrate 20 to form a self-aligned first active structure 111, a semiconductor structure 25 and a second active structure 121. Fig.25 The structure shown.

[0138] It can be understood that etching is performed simultaneously in the WL region and the BL region, so that self-alignment of the BL and the WL can be ensured.

[0139] Step 3: Deposit an oxide material on the substrate 20 to form a first shallow trench isolation structure 26, and perform CMP and etching to expose the front transistor to obtain Fig.26 The structure shown.

[0140] Step 4: Form a first transistor and a first capacitor structure 34 on the first shallow trench isolation structure 26 to obtain Fig. 27 The structure shown.

[0141] Here, please refer to the fourth to thirteenth steps in the first preparation process mentioned above, which will not be repeated here.

[0142] Step 5: Deposit insulating material on the first capacitor structure 34 to form a third insulating layer 13, and bond the third insulating layer 13 to the carrier wafer 14, and then flip the wafer to obtain Fig.28 The structure shown.

[0143] Step 6: Remove the substrate 20 to the first shallow trench isolation structure 26 to obtain Fig.29 The structure shown.

[0144] Step 7: Thinning the first shallow trench isolation structure 26 to the bottom of the semiconductor structure 25 to obtain Fig.30 The structure shown.

[0145] Step 8: Deposit metal materials in the WL region and the BL region simultaneously to obtain Fig.31 The structure shown.

[0146] It can be understood that, since the spacing of the active structures along the BL direction in the top view of the second preparation process is small, the deposited metal material is sufficient to fill the grooves between the adjacent second active structures 121 and the semiconductor structure 25, corresponding to Fig.31 (a). The spacing between the active structures along the WL direction is large, so the deposited metal material cannot fill the entire groove and can only cover the surface of the second active structure 121 and the semiconductor structure 25, corresponding to Fig.31 (b) For example, the metal material may be deposited by ALD.

[0147] Step 9: Anisotropically etch the metal material to form a BL structure 35, and obtain Fig.32 The structure shown.

[0148] It can be understood that by anisotropically etching the metal material and strictly controlling the etching rate, there is enough metal material in the BL area, and the metal in the WL area is removed to prevent short circuit. Fig.32 As shown in (a) and (b), the BL structure connects the semiconductor structure through the metal material in the BL region, but not in the WL region. Fig.32 (c) is a top view schematic diagram of the memory structure. The active structure 36 includes a first active structure 111 and a second active structure 121. The length of the active structure along the WL direction and the BL direction is jointly determined by the metal deposition and etching process. The spacing between the WL structure and the BL structure is the same.

[0149] Step 10: Deposit an oxide material on the BL structure in the BL region and the first shallow trench isolation structure in the WL region and perform CMP to a certain height to form a second shallow trench isolation structure 37, as shown in FIG. Fig.33 The structure shown.

[0150] Step 11: Prepare the second transistor and the second capacitor structure 41 to obtain Fig.34 The structure shown.

[0151] Here, reference may be made to the fourth to thirteenth steps in the first preparation process described above.

[0152] This application starts from the specific process flow of self-aligned flip-chip stacked transistors and is similar to 4F 2 The active structure is formed by integrating the BL area and the WL area, ensuring the complete self-alignment of the BL and WL. Through wafer bonding and flipping, the front and back integration 4F is realized 2 The equivalent area of ​​the memory is 2F. 2 , which is equivalent to reducing the area of ​​the memory cell of the memory and improving the storage density and integration of the memory.

[0153] Furthermore, the memory provided in the embodiment of the present application can be tested using a testing and analysis instrument, such as a scanning electron microscope (SEM), a transmission electron microscope (TEM), a scanning transmission electron microscope (STEM), etc. Taking TEM as an example, the embodiment of the present application can use TEM slicing to detect the structure of the above memory, and it can be observed that the 1T1C structure in the basic structure of the memory exists on both the front and back sides, and the WL structure and the BL structure are all self-aligned.

[0154] An embodiment of the present application provides a semiconductor device, including: a memory as described in the above embodiment.

[0155] An embodiment of the present application provides an electronic device, comprising: a circuit board and a semiconductor device as described in the above embodiment, wherein the semiconductor device is arranged on the circuit board. The semiconductor device comprises the above memory.

[0156] In the description of the embodiments of the present application, the description with reference to the terms "one embodiment", "an embodiment", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine the different embodiments or examples described in the present application and the features of the different embodiments or examples without contradiction.

[0157] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing a memory, characterized in that: The method comprises: Forming a stacked structure on a substrate, the stacked structure comprising: a first active structure, a semiconductor structure, and a second active structure stacked in sequence in a first direction, the first active structure being farther away from the substrate than the second active structure, the first active structure, the semiconductor structure, and the second active structure being self-aligned along the first direction, the doping concentration of the first active structure being the same as the doping concentration of the second active structure, and the doping concentration of the semiconductor structure being different from the doping concentration of the first active structure; Based on the first active structure, forming a first memory; Flipping the first memory and removing the substrate to expose the second active structure and the semiconductor structure; Depositing metal material on both sides of the semiconductor structure in the bit line BL region to form a metal structure, wherein the metal structure connects the semiconductor structure with an adjacent semiconductor structure; A second memory is formed based on the second active structure, wherein the first source-drain structure in the first memory and the second source-drain structure in the second memory share the semiconductor structure and the metal structure.

2. The method according to claim 1, characterized in that: The step of depositing metal material on both sides of the semiconductor structure in the bit line BL region to form a metal structure includes: Depositing metal material on both sides of the semiconductor structure, wherein the height of the metal material is the same as the height of the semiconductor structure; The metal material in the WL region is etched to form the metal structure.

3. The method according to claim 1, characterized in that: The forming of a stacked structure on a substrate comprises: stacking a first material layer, a second material layer and a third material layer in sequence on the substrate; The third material layer, the second material layer and the first material layer are etched to form the first active structure, the semiconductor structure and the second active structure.

4. The method according to claim 1, characterized in that: The forming of a first memory based on the first active structure includes: Based on the first active structure, forming a first transistor; forming a first capacitor structure on the first transistor; The forming of a second memory based on the second active structure comprises: Based on the second active structure, forming a second transistor; A second capacitor structure is formed on the second transistor.

5. The method according to claim 4, characterized in that The forming of a first transistor based on the first active structure comprises: Based on the first active structure, forming a first gate structure; Removing the first gate structure in the BL region to form a first groove; Depositing an insulating material on the first gate structure in the WL region and in the first groove to form a first insulating layer, wherein an upper surface of the first insulating layer is flush with an upper surface of a first mask, and the first mask is located on the first active structure; removing the first mask to form a second groove; A first source-drain structure is formed in the second groove.

6. The method according to claim 5, characterized in that The first gate structure includes a first gate electrode layer and a first gate dielectric layer surrounding the first gate electrode layer, wherein the height of the first gate electrode layer is lower than the height of the first gate dielectric layer; The removing the first gate structure in the BL region to form a first groove comprises: forming a sacrificial layer on the first gate electrode layer in the BL region, wherein an upper surface of the sacrificial layer is flush with an upper surface of the first gate dielectric layer; The bottom of the sacrificial layer and the first gate electrode layer located below the sacrificial layer are anisotropically etched to form the first groove.

7. The method according to claim 5, characterized in that The forming of a first capacitor structure on the first transistor comprises: forming a first dielectric layer on the first source-drain structure; Etching a first portion of the first dielectric layer to expose the first source-drain structure; The first capacitor structure is formed on the first source-drain structure.

8. A memory, prepared using the preparation method according to any one of claims 1 to 7, characterized in that: include: A BL structure, wherein the BL structure is composed of a semiconductor structure and a metal structure; a first memory; A second memory, wherein the second memory is arranged opposite to the first memory, and a first source-drain structure in the second memory and a second source-drain structure in the first memory share the BL structure.

9. A semiconductor device, characterized in that: include: A memory as claimed in claim 8.

10. An electronic device, characterized in that: include: A circuit board and a semiconductor device as claimed in claim 9, wherein the semiconductor device is arranged on the circuit board.

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