Efuse unit and layout structure thereof
By using the design of double-gate NMOS tube and AA fuse in the efuse unit, the layout area is reduced and the system reliability is improved, and the problem of difficult reduction in the layout area of the efuse unit array in the prior art is solved.
Patent Information
- Application Number
- CN202411296491.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-14
- Publication Date
- 2025-01-10
AI Technical Summary
The layout area of the existing efuse unit array is difficult to reduce, mainly because the area of the MOS control tube accounts for a large area, which makes the overall area difficult to compress.
Design an efuse unit, using a double-gate NMOS tube and AA fuse. The NMOS tube is composed of N0 tube and N1 tube in series, and the AA fuse is connected in parallel with N1 tube, and passes through two working modes (fuse working mode and conventional working mode ) Control the current, fuse the NMOS tube and the AA fuse to reduce the layout area.
The layout area of the efuse unit array is reduced, which improves the reliability of the system and fuses, reduces the free area of layout work, and improves work efficiency.
Smart Images
Figure CN119300348A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to an efuse unit and its layout structure. Background Art
[0002] Efuse is a one-time programmable (One Time Program) memory that is based on the electromigration (EM) principle and achieves a highly reliable on-chip programming function by blowing fuses.
[0003] The area of efuse is an important indicator. The main part of the area is the efuse unit array. Each efuse unit is composed of a fuse and a MOS control tube. The area of the MOS control tube occupies most of the entire unit area. Therefore, it can be concluded that the MOS control tube is the core factor that determines the overall area of efuse. However, it is very difficult to reduce the area of the MOS control tube. Summary of the invention
[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide an efuse unit and its layout structure, so as to solve the problem that the layout area of the efuse unit array in the prior art is difficult to reduce.
[0005] To achieve the above-mentioned purpose and other related purposes, the present application provides an efuse unit, which includes a dual-gate NMOS tube and an AA fuse, wherein the NMOS tube is a four-port (port G1, G2, S, BL) device composed of an N0 tube and an N1 tube connected in series, the AA fuse and the N1 tube are connected in parallel, the gate end of the N1 tube is port G2, the gate end of the N0 tube is port G1, and the source end is port S, one end of the AA fuse is connected to the drain ends of the N0 tube and the N1 tube, and the other end of the AA fuse is connected to the source end of the N1 tube as port BL.
[0006] Preferably, the AA fuse is formed of a metal compound layer formed on the active region.
[0007] Preferably, the metal compound layer comprises a metal silicide layer.
[0008] Preferably, the active region is an N+diff active region.
[0009] Preferably, the NMOS tube has two working modes, namely, a fuse working mode and a normal working mode.
[0010] Preferably, when the NMOS tube is in the fuse working mode, the port G2 is grounded, the N1 tube is disconnected, and the AA fuse allows current to pass.
[0011] Preferably, when the NMOS tube is in the normal working mode, the port G2 is connected to a high level, the N1 tube is turned on, and the current passing through the AA fuse is reduced, thereby ensuring that the AA fuse is not accidentally programmed.
[0012] Preferably, in both working modes, the port G1 of the NMOS tube is connected to the word line.
[0013] The present application also provides a layout structure of the above-mentioned efuse unit, in which the AA fuse is integrated into the NMOS tube area, and the NMOS tube has a dual gate terminal (port G1 and G2), wherein port G1 serves as a control terminal to control the magnitude of the programming current passing through the NMOS tube; port G2 is connected to a high potential in a normal working mode and to a ground potential in a fuse working mode; ports G1 and G2 share a common drain terminal, which is connected together through a metal layer and one end of a source terminal corresponding to port G2; the contact plug and the metal layer in the middle of the source terminal are removed to form the body of the AA fuse; the contact plug and the metal layer at the other end of the source terminal constitute the port BL of the NMOS tube.
[0014] Preferably, the port S of the NMOS tube is connected to the ground potential.
[0015] As described above, the efuse unit and its layout structure provided in the present application have the following beneficial effects: integrating the fuse and the MOS tube can reduce the layout area of the efuse unit array, improve the layout work efficiency, and at the same time, improve the reliability of the system and the fuse. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0017] Figure 1 (a) Schematic diagram showing the equivalent circuit of a conventional efuse unit;
[0018] Figure 1 (b) Schematic diagram showing the layout area of a conventional efuse unit;
[0019] Figure 1 (c) Schematic diagram of the layout structure of an NMOS tube showing a conventional efuse unit;
[0020] Figure 2 (a) is a schematic diagram showing an equivalent circuit of an efuse unit provided in an embodiment of the present application;
[0021] Figure 2(b) is a schematic diagram showing the working mode of the efuse unit provided in an embodiment of the present application;
[0022] Figure 3 (a) shows a schematic diagram of the layout area of the efuse unit provided in an embodiment of the present application;
[0023] Figure 3 (b) Displayed as Figure 3 (a) shows the schematic diagram of the layout structure of the NMOS tube in the efuse unit layout;
[0024] Figure 3 (c) Displayed as Figure 3 (b) shows a schematic diagram of a cross section of an NMOS tube at different positions in the NMOS tube layout structure;
[0025] Figure 4 (a) is a schematic diagram showing an equivalent circuit of an efuse unit pair composed of efuse units provided in an embodiment of the present application;
[0026] Figure 4 (b) Displayed as Figure 4 (a) Schematic diagram of the layout structure of the efuse unit pair. DETAILED DESCRIPTION
[0027] The following describes the implementation of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific implementations, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0028] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0029] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating directions or positional relationships, are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.
[0030] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0031] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0032] The equivalent circuit of a conventional efuse unit is as follows Figure 1 As shown in (a), it includes a fuse body (link) and a programming transistor N0, wherein one end of the fuse body is connected to the bit line (BL) port of the efuse unit, and the other end is connected to the drain of the transistor N0; the gate (G) of the transistor N0 is connected to the word line (WL) port of the efuse unit, and the source (S) of the transistor N0 is connected to the ground port of the efuse unit.
[0033] The layout area of the conventional efuse unit is as follows Figure 1 As shown in (b), the dashed box in the figure indicates the fuse area, and the rest is the NMOS tube area. The NMOS tube occupies most of the area in the efuse unit layout. The layout structure of the NMOS tube of a conventional efuse unit is as follows: Figure 1 As shown in (c), it includes the gate terminal (Gate), source terminal (Source) and drain terminal (Drain). The MOS tube adopts a multi-finger layout design method, that is, the gate terminal is composed of multiple columns of polysilicon or metal gate layers.
[0034] In order to further reduce the layout area of the efuse unit, the present application provides an efuse unit and its layout structure.
[0035] See also Figure 2 (a) shows a schematic diagram of an equivalent circuit of an efuse unit provided in an embodiment of the present application.
[0036] like Figure 2As shown in (a), the efuse unit includes a dual-gate NMOS tube and an AA fuse, wherein the NMOS tube is a four-port (port G1, G2, S, BL) device composed of an N0 tube and an N1 tube connected in series, the AA fuse is connected in parallel with the N1 tube, the gate end of the N1 tube is port G2, the gate end of the N0 tube is port G1, and the source end is port S, one end of the AA fuse is connected to the drain ends of the N0 tube and the N1 tube, and the other end of the AA fuse is connected to the source end of the N1 tube as port BL.
[0037] As an example, the AA fuse is composed of a metal compound layer formed on the active area (Active Area, abbreviated as AA), and has the same working mechanism as the metal fuse, both of which are blown fuses. Exemplarily, the active area can adopt the N+diff active area, and the metal compound layer can be a conventional metal silicide layer.
[0038] See also Figure 2 (b) is a schematic diagram showing the working mode of the efuse unit provided in an embodiment of the present application.
[0039] like Figure 2 As shown in (b), the NMOS tube of the efuse unit has two working modes, namely the fuse working mode and the normal working mode. When the port G2 of the NMOS tube is connected to the ground level VSS, the N1 tube is disconnected, the AA fuse allows current to pass, and the NMOS tube is in the fuse working mode. When the port G2 is connected to the high level VDD, the N1 tube is connected, and the NMOS tube is in the normal working mode. In the normal working mode, due to the current bypass of the AA fuse, the current passing through the AA fuse is reduced, ensuring that the fuse is not accidentally programmed, thereby improving the reliability of the system and the fuse. In both working modes, the port G1 of the NMOS tube is connected to the word line (WL).
[0040] See also Figure 3 (a) shows a schematic diagram of the layout area of the efuse unit provided in an embodiment of the present application.
[0041] like Figure 3 (a) shows that compared with Figure 1 (b) shows the layout area layout of the conventional efuse unit. Since the NMOS tube is integrated with the fuse part and uses the AA layer as the fuse medium, it can not only be directly combined and laid out, thereby improving the layout work efficiency, but also greatly reducing the area of the efuse unit and the idle area in the array layout. Figure 1 The area of the efuse unit (NMOS tube and fuse) shown in (b) is 14.4 square microns, while Figure 3 The actual area of the efuse unit shown in (a) can be reduced by 80%.
[0042] See also Figure 3 (b), which shows Figure 3 (a) shows the schematic diagram of the layout structure of the NMOS tube in the efuse unit layout.
[0043] like Figure 3 As shown in (b), the NMOS tube is a four-port (port G1, G2, S, BL) device, which adopts a dual-gate terminal (port G1 and G2) design, wherein port G1 is used as a control terminal to control the size of the programming current passing through the NMOS tube; port G2 is connected to a high potential in the normal working mode and to the ground potential in the fuse working mode; port S is connected to the ground potential. Ports G1 and G2 share the same drain terminal (Drain, i.e. D); the drain terminal D is also connected to one end of the source terminal S2 corresponding to port G2 through the metal layer M1; the contact plug CT and the metal layer M1 in the middle of the source terminal S2 are removed to form the body of the AA fuse; and the contact plug CT and the metal layer M1 at the other end of the source terminal S2 constitute the port BL of the NMOS tube.
[0044] See also Figure 3 (c), which shows Figure 3 (b) is a schematic diagram of the cross-section of NMOS tubes at different positions in the NMOS tube layout structure.
[0045] like Figure 3 As shown in (c), A-A' shows the lateral cross-section of the contact plugs at the two gate terminals (ports G1 and G2), BB' shows the cross-section at the drain terminal D shared by the two gate terminals, CC' shows the cross-sectional schematic diagram of the contact plug in the middle of the source terminal S2 removed, and D-D' shows the cross-sectional schematic diagram at the port BL.
[0046] See also Figure 4 (a) shows a schematic diagram of an equivalent circuit of an efuse unit pair composed of efuse units provided in an embodiment of the present application.
[0047] like Figure 4 As shown in (a), the efuse unit pair is composed of two NMOS tubes connected to the same BL line, and the ports G2 of the two NMOS tubes are both grounded.
[0048] See also Figure 4 (b), which shows Figure 4 (a) Schematic diagram of the layout structure of the efuse unit pair.
[0049] like Figure 4As shown in (b), the word lines WL1 and WL2 marked by box 1 are connected to the gate terminals of the two efuse units respectively, the second layer metal M2 marked by box 2 is used to connect the drain terminals (D1, D2) and source terminals (S1, S2) of different fingers of the NMOS tubes in the two efuse units, and the bit line BL uses the third layer metal M3 marked by box 3. The small squares are contact plugs CT, where the small squares with the same color as the box indicate that the contact plug CT is connected to the metal layer line marked by the box.
[0050] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present application in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0051] In summary, the efuse unit and its layout structure provided by the present application integrate the fuse and the MOS tube, which can reduce the layout area of the efuse unit array, improve the layout work efficiency, and at the same time, improve the reliability of the system and the fuse. Therefore, the present application effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.
[0052] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present application.
Claims
1. An efuse unit, characterized in that: The efuse unit includes a dual-gate NMOS tube and an AA fuse, wherein the NMOS tube is a four-port (port G1, G2, S, BL) device composed of an N0 tube and an N1 tube connected in series, the AA fuse is connected in parallel with the N1 tube, the gate end of the N1 tube is the port G2, the gate end of the N0 tube is the port G1, and the source end is the port S, one end of the AA fuse is connected to the drain ends of the N0 tube and the N1 tube, and the other end of the AA fuse is connected to the source end of the N1 tube, which is the port BL.
2. The efuse unit according to claim 1, characterized in that: The AA fuse is composed of a metal compound layer formed on the active region.
3. The efuse unit according to claim 2, characterized in that: The metal compound layer includes a metal silicide layer.
4. The efuse unit according to claim 2, characterized in that: The active region is an N+diff active region.
5. The efuse unit according to claim 1, characterized in that: The NMOS tube has two working modes, namely, a fuse working mode and a normal working mode.
6. The efuse unit according to claim 5, characterized in that: When the NMOS tube is in the fuse working mode, the port G2 is grounded, the N1 tube is disconnected, and the AA fuse allows current to pass.
7. The efuse unit according to claim 5, characterized in that: When the NMOS tube is in the normal working mode, the port G2 is connected to a high level, the N1 tube is turned on, and the current passing through the AA fuse is reduced, thereby ensuring that the AA fuse is not accidentally programmed.
8. The efuse unit according to claim 5, characterized in that: In the two working modes, the port G1 of the NMOS tube is connected to the word line.
9. A layout structure of an efuse unit according to any one of claims 1 to 8, characterized in that: The AA fuse is integrated into the NMOS tube region, and the NMOS tube has dual gate terminals (ports G1 and G2), wherein the port G1 is used as a control terminal to control the magnitude of the programming current passing through the NMOS tube; the port G2 is connected to a high potential in a normal working mode and to a ground potential in a fuse working mode; the ports G1 and G2 share a common drain terminal, and the drain terminal is connected together through a metal layer and one end of a source terminal corresponding to the port G2; the contact plug and the metal layer in the middle of the source terminal are removed to form the body of the AA fuse; the contact plug and the metal layer at the other end of the source terminal constitute the port BL of the NMOS tube.
10. The layout structure of the efuse unit according to claim 9, characterized in that: The port S of the NMOS tube is connected to the ground potential.