IGBT device structure and preparation method thereof

Abstract

The invention provides an IGBT (Insulated Gate Bipolar Translator) device structure and a preparation method thereof. The preparation method comprises the following steps: forming a plurality of gate trenches in an active region, and forming a gate oxide layer and a polycrystalline silicon layer; forming a grid line mask pattern; forming a polysilicon gate line, and reserving a gate line mask pattern on the polysilicon gate line; a hard mask medium is deposited, a first window and a second window which expose the surface of the active area are formed, and the second window exposes the grid line mask pattern on the grid line; etching is carried out, based on the etching selection ratio, the semiconductor substrate in the first window is partially removed to form an emitter region contact hole, and the grid line mask pattern in the second window is not removed to protect the grid line; and removing the grid line mask pattern in the second window by a wet method to form a grid line contact hole. According to the invention, the preparation of the emitter region contact hole and the line contact hole only needs to use one mask plate for photoetching and etching, compared with the traditional process, one mask plate is effectively reduced, the process flow is simplified, the production period is shortened, and the production efficiency is improved while the tape-out cost is reduced.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor integrated circuit design and manufacture, and in particular relates to an IGBT device structure and a preparation method thereof. Background Art

[0002] In the field of power semiconductors, the development of insulated gate bipolar transistor (IGBT) technology has experienced a transition from planar to trench type, which is accompanied by the reduction of cell pitch, that is, the size of the smallest repeating unit is getting smaller and smaller. This high-density integration brings a series of manufacturing challenges, especially the problem of wafer warpage, which directly affects the alignment accuracy of the contact hole mask and the trench gate mask during the manufacturing process, which is crucial to ensure the consistency of the saturation voltage drop (Vcesat) within the IGBT wafer.

[0003] With the development of trench IGBT technology, the distance from the active area contact hole to the trench gate is constantly shrinking, and the requirements for alignment accuracy are also increasing. If there is a deviation in alignment, the distance from the contact hole to the trench gate will be insufficient, which will affect the performance of the IGBT. When making the emitter contact hole and the gate line (Bus Poly) contact hole in the existing IGBT, in order to avoid the gate line (Bus Poly) being cut, two masks are usually required to be used for etching separately, where one mask is used for etching the emitter contact hole and the other is used for etching the gate line (Bus Poly) contact hole. This double mask process can improve the reliability and performance of the product, but it will greatly increase the complexity of the manufacturing process.

[0004] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide an IGBT device structure and a preparation method thereof, so as to solve the problem of the contact hole etching process of the IGBT in the prior art.

[0006] To achieve the above-mentioned purpose and other related purposes, the present invention provides a method for preparing an IGBT device structure, the method comprising: providing a semiconductor substrate, wherein an active region, a transition region and a terminal region are arranged in sequence on the semiconductor substrate; forming a plurality of gate trenches arranged at intervals in the active region, and forming a gate oxide layer at the bottom and sidewalls of each of the gate trenches; forming a polysilicon layer in the gate trenches and on the surface of the semiconductor substrate; forming a dielectric protection layer on the surface of the polysilicon layer, and patterning and etching the dielectric protection layer to form a gate line mask pattern; etching the polysilicon layer based on the gate line mask pattern to form a polysilicon gate line, and retaining the gate line mask pattern on the polysilicon gate line; depositing a gate line on the semiconductor substrate; A hard mask medium is provided, and the hard mask medium is patterned to form a first window exposing the surface of the active area and a second window exposing the gate line contact area, wherein the second window exposes the gate line mask pattern on the gate line; etching is performed based on the hard mask medium, and by setting an etching selection ratio between the semiconductor substrate and the gate line mask pattern, the semiconductor substrate in the first window at the active area is partially removed to form an emitter area contact hole, and the gate line mask pattern in the second window at the gate line contact area is not removed to protect the gate line; the gate line mask pattern in the second window is removed by a wet process to form a gate line contact hole exposing the gate line; and a front metal is formed in the emitter area contact hole and the gate line contact hole.

[0007] Optionally, before forming a plurality of gate trenches arranged at intervals in the active area, the method further includes forming a field oxide layer on the surface of the terminal area.

[0008] Optionally, before forming a field oxide layer on the surface of the terminal region, the method further includes the steps of: forming a lateral variable doping region in the transition region and the terminal region by ion implantation; and forming a cutoff ring doping region at the edge of the terminal region by ion implantation.

[0009] Optionally, the dielectric protection layer includes a silicon nitride layer, or the dielectric protection layer includes a composite layer of a silicon dioxide layer and a silicon nitride layer stacked.

[0010] Optionally, when etching the polysilicon layer based on the gate line mask pattern, the polysilicon layer on each gate trench is removed, and the polysilicon layer in each gate trench is partially removed to form a groove, and the preparation method also includes the step of forming a thermal oxide layer on the bottom and side walls of the groove and the surface of the active area.

[0011] Optionally, forming the emitter contact hole includes the steps of: etching based on the hard mask medium, and based on the etching selectivity of the semiconductor substrate exposed between the thermal oxide layer at the bottom and sidewall of the groove and the groove, self-aligningly removing a portion of the semiconductor substrate at the active area to form the emitter contact hole.

[0012] Optionally, the preparation method further comprises the step of: performing ion implantation on the active region in sequence to form a carrier storage region, a body region and an emission region in the active region.

[0013] Optionally, depositing a hard mask medium on the semiconductor substrate includes the steps of: depositing a borophosphosilicate glass layer on the semiconductor substrate, and then performing a reflow process on the borophosphosilicate glass layer to form a hard mask medium.

[0014] Optionally, before forming the front metal, the steps also include: forming an injection barrier layer on the side walls and bottom of the emitter contact hole and the gate line contact hole; removing the injection barrier layer at the bottom of the emitter contact hole and the gate line contact hole by an etching back process; forming a contact doping region at the bottom of the emitter contact hole and the gate line contact hole by an ion implantation process; and removing the injection barrier layer by a wet process.

[0015] Optionally, after forming the front metal, the method further includes the steps of: performing ion implantation on the back side of the semiconductor substrate to form a collector region; performing ion implantation on the back side of the semiconductor substrate to form a hydrogen ion doped region, wherein the hydrogen ion doped region is arranged adjacent to the collector region; and forming a back metal layer on the back side of the semiconductor substrate.

[0016] The present invention also provides an IGBT device structure, which is prepared by the method for preparing the IGBT device structure described in any one of the above schemes.

[0017] As described above, the IGBT device structure and the preparation method thereof of the present invention have the following beneficial effects:

[0018] The present invention provides a process for preparing emitter contact holes by a self-alignment process, which can automatically realize accurate positioning of the emitter contact holes, ensure the distance from the emitter contact holes to the trench gates, and thus ensure the consistency of the saturation voltage drop (Vcesat) of each IGBT device in a wafer.

[0019] The present invention optimizes and adjusts the etching process of gate line contact holes and emitter area contact holes. Under the condition of realizing automatic quasi-emitter area contact hole etching, by pre-fabricating and retaining the gate line mask pattern, the gate line is protected from being etched in the process when the emitter area contact hole is etched, thereby avoiding the problem of gate line breakage caused by etching. Subsequently, the gate line contact hole can be formed by removing the gate line mask pattern only through a wet process, so that the preparation of the emitter area contact hole and the line contact hole only needs to use one mask plate for photolithography and etching. Compared with the traditional process, one contact hole etching mask plate can be effectively reduced, thereby simplifying the entire process flow, shortening the production cycle, reducing the wafer production cost and improving the production efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The included drawings are used to provide a further understanding of the embodiments of the present application, which constitute a part of the specification, are used to illustrate the implementation of the present application, and together with the text description, explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application.

[0021] Figure 1 to Figure 15 It is a schematic diagram showing the structure of each step of the method for preparing the IGBT device structure according to an embodiment of the present invention, wherein: Fig.15 Shown is a schematic structural diagram of an IGBT device structure according to an embodiment of the present invention.

[0022] Component number description:

[0023] 1 Semiconductor substrate

[0024] 1a Gate trench

[0025] 2 Lateral variable doping region

[0026] 3 Field Oxide Layer

[0027] 4. Stop ring doping region

[0028] 5 Gate Oxide

[0029] 6 Polysilicon layer

[0030] 7 Gate line mask pattern

[0031] 8 Grooves

[0032] 9 Carrier storage area

[0033] 10 Body Area

[0034] 11 Launch Area

[0035] 12 Thermal Oxide Layer

[0036] 13 borophosphosilicate glass layer

[0037] 14. Emitter contact hole

[0038] 15 Contact doping region

[0039] 16 Bottom front metal layer

[0040] 17 Top front metal layer

[0041] 18 Collector region

[0042] 19 Hydrogen ion doped region

[0043] 191 The first N-type doping peak

[0044] 192 The second N-type doping peak

[0045] 193 The third N-type doping peak

[0046] 194 The fourth N-type doping peak

[0047] 20 Back metal layer DETAILED DESCRIPTION

[0048] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0049] It should be emphasized that the term “include / comprises” when used herein refers to the presence of features, integers, steps or components, but does not exclude the presence or addition of one or more other features, integers, steps or components.

[0050] Features described and / or illustrated with respect to one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0051] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0052] For ease of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0053] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0054] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0055] like Figure 1 to Figure 15 As shown, this embodiment provides a method for preparing an IGBT device structure, and the preparation method comprises the following steps:

[0056] like Figure 1 As shown, firstly, step 1) is performed to provide a semiconductor substrate 1, on which an active region, a transition region and a terminal region arranged in sequence are provided.

[0057] In one embodiment, the semiconductor substrate 1 may be a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, etc. The semiconductor substrate 1 may be doped, and its doping concentration and thickness may be set according to the withstand voltage requirement of the IGBT device. In this embodiment, the semiconductor substrate 1 is a silicon substrate, and its doping type is N-type doping.

[0058] like Figure 2-3 As shown, step 2) is then performed to form a plurality of spaced-apart gate trenches 1a in the active area, and a gate oxide layer 5 is formed at the bottom and sidewalls of each gate trench 1a; a polysilicon layer 6 is formed in the gate trench 1a and on the surface of the semiconductor substrate 1.

[0059] In one embodiment, before forming a plurality of gate trenches 1a arranged at intervals in the active region, the process further includes the steps of: forming a lateral variable doping region 2 in the transition region and the terminal region by ion implantation; and forming a stop ring doping region 4 at the edge of the terminal region by ion implantation. Specifically, P-type ions (such as boron, etc.) can be implanted in the transition region and the terminal region through a mask, and the implantation dose can be 1e12cm -2 ~5e13cm -2 The implantation energy can be 60keV~200keV, and then N-type ions (such as phosphorus, etc.) are implanted in the edge area of ​​the terminal area through the mask, with an implantation dose of 1e15cm -2 ~1e16cm -2, the implantation energy is 60keV~200keV, and a thermal process is promoted (such as annealing process), the promotion temperature is 1050℃~1250℃, the time is 30min~300min, so as to form a P-type doped field limiting ring (JTE) or a lateral variable doping region 2 (VLD) terminal in the P-type ion implantation region, and form an N-type doped stop ring doping region 4 in the N-type ion implantation region. Of course, in other embodiments, the stop ring doping region 4 may not be additionally made to save process costs.

[0060] In one embodiment, before forming a plurality of spaced-apart gate trenches 1a in the active area, the step further includes: forming a field oxide layer 3 on the surface of the terminal area. For example, the field oxide layer 3 can be formed on the surface of the semiconductor substrate 1 by a thermal oxidation process, and then the field oxide layer 3 is formed on the surface of the terminal area by a photolithography and etching process.

[0061] In one embodiment, a plurality of spaced-apart gate trenches 1a can be formed in the active area by photolithography and etching processes, and then a gate oxide layer 5 is formed at the bottom and sidewalls of each gate trench 1a by a thermal oxidation process (such as heating by a furnace tube in an air or oxygen atmosphere, etc.); and then a polysilicon layer 6 is formed in the gate trench 1a and on the surface of the semiconductor substrate 1 by a deposition process.

[0062] like Figure 4-5 As shown, step 3 is then performed to form a dielectric protection layer on the surface of the polysilicon layer 6, and to perform patterning etching on the dielectric protection layer to form a gate line mask pattern 7.

[0063] In one embodiment, the dielectric protective layer is selected to be a material having a high etching selectivity ratio with the semiconductor substrate 1 material. The high selectivity ratio can be, for example, semiconductor substrate 1: dielectric protective layer greater than or equal to 50:1, etc. For example, when the semiconductor substrate 1 is a silicon substrate, the dielectric protective layer can be a silicon nitride layer, or the dielectric protective layer can be a composite layer of a stack of a silicon dioxide layer and a silicon nitride layer, wherein the silicon dioxide layer is the bottom layer and the silicon nitride layer is the top layer.

[0064] like Figure 6 As shown, step 4 is then performed to etch the polysilicon layer 6 based on the gate line mask pattern 7 to form a polysilicon gate line, and the gate line mask pattern 7 is retained on the polysilicon gate line.

[0065] like Figure 7-8 As shown, when the polysilicon layer 6 is etched based on the gate line mask pattern 7, the polysilicon layer 6 on each gate trench 1a is removed, and the polysilicon layer 6 in each gate trench 1a is partially removed to form a groove 8, and the depth of the groove 8 can be 0.4 microns to 0.7 microns.

[0066] Afterwards, ions are implanted into the active region in sequence to form a carrier storage region 9, a body region 10 and an emission region 11 in the active region.

[0067] Specifically, the carrier storage area 9 is injected through a mask or the carrier storage area 9 is generally injected without a mask. The injected ions may be phosphorus and the injection dose may be 1e12 cm -2 ~5e13cm -2 The implantation energy can be 80KeV~2MeV, the push temperature is 1050℃~1250℃, the time is 30min~300min, and then the body area is implanted 10 times. The implanted ions can be boron, and the implantation dose is 4e13cm -2 ~1e14cm -2 The injection energy is 60keV~200keV, the push temperature can be 1050℃~1250℃, the time is 10min~120min, and then the emitter area 11 is injected through the mask. The injected ions can be arsenic and the injection dose can be 5e15cm -2 ~2e16cm -2 The injection energy can be 60keV~600keV, the advancement temperature can be 900℃~1000℃, and the time can be 30min~120min.

[0068] Finally, a thermal oxide layer 12 is formed on the bottom and sidewalls of the groove 8 and the surface of the active area. For example, a furnace tube may be used to grow the thermal oxide layer 12, and the thickness of the thermal oxide layer 12 may be 1000 angstroms to 3000 angstroms.

[0069] like Fig. 9 and Fig.10 As shown, step 5) is then performed to deposit a hard mask medium on the semiconductor substrate 1 and pattern the hard mask medium to form a first window exposing the surface of the active area and a second window exposing the gate line contact area, wherein the second window exposes the gate line mask pattern 7 on the gate line.

[0070] In one embodiment, depositing a hard mask dielectric on the semiconductor substrate 1 includes the steps of depositing a borophosphosilicate glass layer (BPSG) 13 on the semiconductor substrate 1, and then performing a reflow process on the borophosphosilicate glass layer (BPSG) 13 to form a hard mask dielectric. Specifically, the thickness of the deposited borophosphosilicate glass layer (BPSG) 13 may be 8000 angstroms to 15000 angstroms, the reflow temperature of the borophosphosilicate glass layer (BPSG) 13 may be 900° C. to 1000° C., and the time may be 30 minutes to 240 minutes.

[0071] like Fig.11As shown, step 6 is then performed, etching is performed based on the hard mask medium, and by setting the etching selection ratio of the semiconductor substrate 1 and the gate line mask pattern 7, the semiconductor substrate 1 in the first window at the active area is partially removed to form an emitter area contact hole 14, and the gate line mask pattern 7 in the second window at the gate line contact area is not removed to protect the gate line.

[0072] In one embodiment, forming the emitter contact hole 14 comprises the steps of: performing etching based on the hard mask medium, based on the etching selectivity of the thermal oxide layer 12 at the bottom and sidewall of the groove 8 and the semiconductor substrate 1 (such as a silicon substrate) exposed between the groove 8, self-aligningly removing a portion of the semiconductor substrate 1 at the active area to form the emitter contact hole 14, such as Fig.11 As shown. The present invention provides a process for preparing the emitter contact hole 14 by a self-alignment process, which can automatically realize the precise positioning of the emitter contact hole 14, ensure the distance between the emitter contact hole 14 and the trench gate, and thus ensure the consistency of the saturation voltage drop (Vcesat) of each IGBT device in the wafer. At the same time, the hard mask medium exposes the stop ring doping region 4, and the emitter contact hole 14 is etched to form a contact hole in the stop ring doping region 4.

[0073] like Fig.12 As shown, before forming the front metal, the steps also include: forming an injection barrier layer on the sidewalls and bottom of the emitter contact hole 14 and the gate contact hole; removing the injection barrier layer at the bottom of the emitter contact hole 14 and the gate contact hole by a back etching process; forming a contact doping region 15 at the bottom of the emitter contact hole 14 and the gate contact hole by an ion implantation process; and removing the injection barrier layer by a wet process. Specifically, considering that when the emitter contact hole 14 is implanted, the implantation of the sidewall of the emitter contact hole 14 will affect the doping of the emitter 11, before the emitter contact hole 14 is implanted, a silicon nitride with a thickness of 500 angstroms to 1500 angstroms is first deposited, and then back etching is performed. The silicon nitride retained on the sidewall of the emitter contact hole 14 can prevent P-type ions from being implanted into the sidewall area of ​​the emitter contact hole 14, and then boron or BF2 is implanted into the contact hole to form a P+ type contact doping region 15, wherein the implantation energy of BF2 can be 20keV to 50keV, and the implantation dose can be 5e14cm -2 ~5e15cm -2 , or the boron implantation energy can be 40keV~100keV, and the implantation dose can be 5e12cm -2 ~5e14cm -2 Finally, the silicon nitride on the sidewall is removed by a wet process. It should be noted that the implantation of the contact doping region 15 can also be performed after the gate line mask pattern 7 is subsequently removed by a wet process, and is not limited to the examples listed here.

[0074] like Fig.13 As shown, step 7) is then performed to remove the gate line mask pattern 7 in the second window by a wet process without a mask to form a gate line contact hole exposing the gate line.

[0075] The present invention optimizes and adjusts the etching process of the gate line contact hole and the emitter area contact hole 14. Under the condition of realizing automatic quasi-emitter area contact hole 14 etching, by pre-fabricating and retaining the gate line mask pattern 7, the gate line is protected from being etched in the process when the emitter area contact hole 14 is etched, thereby avoiding the problem of the gate line being etched and causing breakage. Subsequently, the gate line contact hole can be formed by removing the gate line mask pattern 7 through a wet process, so that the preparation of the emitter area contact hole 14 and the line contact hole only needs to use one mask plate for photolithography and etching. Compared with the traditional process, one contact hole etching mask plate can be effectively reduced, thereby simplifying the entire process flow, shortening the production cycle, reducing the wafer production cost and improving the production efficiency.

[0076] like Fig.14 As shown, step 8) is then performed to form a front metal in the emitter region contact hole 14 and the gate line contact hole.

[0077] In one embodiment, the bottom front metal layer 16 (such as Ti / TiN / W) is prepared by a metal deposition process and etched back, and then the upper front metal layer 17 (such as AlCu) is deposited by a metal deposition process, and metal photolithography and etching are performed to form a front metal layer. Specifically, the front metal layer can be used to lead out the emitter region 11, the gate line and the stop ring doping region 4. At the same time, if there is field plate polysilicon, the front metal layer can also lead out the field plate polysilicon at the same time.

[0078] like Fig.15 As shown, step 9 is finally performed to perform ion implantation on the back side of the semiconductor substrate 1 to form a collector region 18; perform ion implantation on the back side of the semiconductor substrate 1 to form a hydrogen ion doped region 19, wherein the hydrogen ion doped region 19 is arranged adjacent to the collector region 18; and form a back metal layer 20 on the back side of the semiconductor substrate 1.

[0079] In one embodiment, the semiconductor substrate 1 is first turned over and thinned to a certain thickness, the thickness of which depends on the withstand voltage requirement of the IGBT device, and then a boron ion implantation is performed with an implantation energy of 60KeV to 20KeV and an implantation dose of 3e12cm -2 ~1e14cm -2, forming a P-type collector region 18, and then using laser annealing equipment to activate the injected boron ions; then hydrogen is injected four times from the back side of the semiconductor substrate 1 and annealed to form a hydrogen ion doped region 19 (191 represents the first N-type doping peak formed by hydrogen injection; 192 represents the second N-type doping peak formed by hydrogen injection; 193 represents the third N-type doping peak formed by hydrogen injection; 194 represents the fourth N-type doping peak formed by hydrogen injection, and the concentration of the doping peak can be gradually increased from 191 to 194). It should be noted that the hydrogen injection is 5 times or 3 times or 2 times or 1 time, and is not limited to the examples listed here. Finally, it is deposited on the back side of the semiconductor substrate 1 to form a back metal layer 20, and the back metal layer 20 can be Al / Ti / Ni / Ag.

[0080] like Fig.15 As shown, this embodiment further provides an IGBT device structure, and the IGBT device structure is prepared by the preparation method of the IGBT device structure described in any of the above embodiments.

[0081] As described above, the IGBT device structure and the preparation method thereof of the present invention have the following beneficial effects:

[0082] The present invention provides a process for preparing emitter contact holes by a self-alignment process, which can automatically realize accurate positioning of the emitter contact holes, ensure the distance from the emitter contact holes to the trench gates, and thus ensure the consistency of the saturation voltage drop (Vcesat) of each IGBT device in a wafer.

[0083] The present invention optimizes and adjusts the etching process of gate line contact holes and emitter area contact holes. Under the condition of realizing automatic quasi-emitter area contact hole etching, by pre-fabricating and retaining the gate line mask pattern, the gate line is protected from being etched in the process when the emitter area contact hole is etched, thereby avoiding the problem of gate line breakage caused by etching. Subsequently, the gate line contact hole can be formed by removing the gate line mask pattern only through a wet process, so that the preparation of the emitter area contact hole and the line contact hole only needs to use one mask plate for photolithography and etching. Compared with the traditional process, one contact hole etching mask plate can be effectively reduced, thereby simplifying the entire process flow, shortening the production cycle, reducing the wafer production cost and improving the production efficiency.

[0084] Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0085] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing an IGBT device structure, characterized in that: The preparation method comprises: Providing a semiconductor substrate, wherein an active region, a transition region and a terminal region are arranged in sequence; Forming a plurality of gate trenches arranged at intervals in the active area, and forming a gate oxide layer at the bottom and sidewall of each of the gate trenches; forming a polysilicon layer in the gate trench and on the surface of the semiconductor substrate; Forming a dielectric protection layer on the surface of the polysilicon layer, and pattern-etching the dielectric protection layer to form a gate line mask pattern; Etching the polysilicon layer based on the gate line mask pattern to form a polysilicon gate line, wherein the gate line mask pattern is retained on the polysilicon gate line; Depositing a hard mask dielectric on the semiconductor substrate, and patterning the hard mask dielectric to form a first window exposing the surface of the active area and a second window exposing the gate line contact area, wherein the second window exposes the gate line mask pattern on the gate line; Etching is performed based on the hard mask medium, and by setting an etching selection ratio between the semiconductor substrate and the gate line mask pattern, the semiconductor substrate in the first window at the active area is partially removed to form an emitter area contact hole, and the gate line mask pattern in the second window at the gate line contact area is not removed to protect the gate line; Removing the gate line mask pattern in the second window by a wet process to form a gate line contact hole exposing the gate line; A front metal is formed in the emitter region contact hole and the gate line contact hole.

2. The method for preparing an IGBT device structure according to claim 1, characterized in that: Before forming a plurality of gate trenches arranged at intervals in the active area, the method further comprises the following steps: A field oxide layer is formed on the surface of the terminal region.

3. The method for preparing an IGBT device structure according to claim 2, characterized in that: Before forming a field oxide layer on the surface of the terminal region, the method further comprises the following steps: Forming lateral variable doping regions in the transition region and the terminal region by ion implantation; A cut-off ring doping region is formed at the edge of the terminal region by ion implantation.

4. The method for preparing an IGBT device structure according to claim 1, characterized in that: The dielectric protection layer includes a silicon nitride layer, or the dielectric protection layer includes a composite layer of a silicon dioxide layer and a silicon nitride layer stacked.

5. The method for preparing an IGBT device structure according to claim 1, characterized in that: When etching the polysilicon layer based on the gate line mask pattern, the polysilicon layer on each gate trench is removed, and the polysilicon layer in each gate trench is partially removed to form a groove, and the preparation method further includes the steps of: A thermal oxide layer is formed on the bottom and sidewall of the groove and the surface of the active area.

6. The method for preparing an IGBT device structure according to claim 5, characterized in that: Forming the emitter region contact hole comprises the following steps: Etching is performed based on the hard mask medium, and based on the etching selectivity of the semiconductor substrate exposed between the thermal oxide layer at the bottom and sidewall of the groove and the groove, a portion of the semiconductor substrate at the active area is self-alignedly removed to form an emitter area contact hole.

7. The method for preparing an IGBT device structure according to claim 1, characterized in that: The preparation method further comprises the steps of: By sequentially performing ion implantation on the active region, a carrier storage region, a body region and an emission region are formed in the active region.

8. The method for preparing an IGBT device structure according to claim 1, characterized in that: Depositing a hard mask dielectric on the semiconductor substrate comprises the steps of: A borophosphosilicate glass layer is deposited on the semiconductor substrate, and then a reflow process is performed on the borophosphosilicate glass layer to form a hard mask dielectric.

9. The method for preparing an IGBT device structure according to claim 1, characterized in that: Before forming the front metal, the following steps are also included: forming an injection blocking layer on the sidewalls and bottom of the emitter region contact hole and the gate line contact hole; Removing the injection barrier layer at the bottom of the emitter contact hole and the gate line contact hole by an etch-back process; Forming a contact doping region at the bottom of the emitter region contact hole and the gate line contact hole by an ion implantation process; The implantation barrier layer is removed by a wet process.

10. The method for preparing an IGBT device structure according to claim 1, characterized in that: After forming the front metal, the following steps are also included: Performing ion implantation on the back side of the semiconductor substrate to form a collector region; Performing ion implantation on the back side of the semiconductor substrate to form a hydrogen ion doped region, wherein the hydrogen ion doped region is disposed adjacent to the collector region; A back metal layer is formed on the back side of the semiconductor substrate.

11. An IGBT device structure, characterized in that: The IGBT device structure is prepared by the method for preparing an IGBT device structure according to any one of claims 1 to 10.

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