Method for mitigating cache interference in partitioned computing system

Abstract

The invention discloses a method for mitigating cache interference in a partitioned computing system. A method for mitigating cache interference in a partitioned computing system includes performing cache shading on a cache; allocating the cache group with the cache color to a serial execution partition; and performing flush and invalidation operations on a cache group associated with an incoming partition that shares the same cache color with other partitions of the serial execution prior to execution of the partitions of the serial execution.

Description

Technical Field

[0001] The present invention relates generally to cache management techniques, and more particularly to mitigating cache interference in partitioned computing systems. Background Art

[0002] Robust partitioning is a key fundamental requirement in Integrated Modular Avionics (IMA) platforms. Temporal partitioning of cache is one of the main challenges in current partitioned computing systems due to cache interference.

[0003] Figure 1 A schematic diagram showing cache interference generated when partitions are executed serially is shown. As shown in the partitioned computing system 100, partitions A, B, C, and D can execute tasks on core 0 and core 1 of the partitioned computing system 100. When executing tasks, partitions A, B, C, and D can access the L1 cache of core 0, the L1 cache of core 1, and the L2 cache of the partitioned computing system 100, as indicated by the stars in the figure. Further, as shown in the timing 150, partitions A and B can be executed serially on core 0, and partitions C and D can be executed serially on core 1. For partitions that are executed serially in time, one partition is coming (referred to as "arriving partitions"). Specifically, for partitions that are executed serially, one partition (e.g., partition A) evicts the data of the incoming partition (e.g., partition B) from the private cache (L1 cache) of the corresponding core (e.g., core 0) or the shared cache (L2 cache) of the partitioned computing system 100. As a result, the incoming partition (partition B) is interfered with by the partition (partition A). This interference when partitions are executed serially also exists in the case of a single-core processor.

[0004] Figure 2 A schematic diagram showing cache interference generated when partitions are executed in parallel. As described in partitioned computing system 200, the corresponding processes of partition A, partition B, and partition C (represented by circles therein) can execute tasks in parallel on cores 0, 1, 2, and 3 of partitioned computing system 200. When executing tasks, partition A, partition B, partition C, and partition D can access the L2 cache of partitioned computing system 200, as indicated by the stars in the figure. Partition A, partition B, partition C, and partition D can also access the L1 cache of the core where they are executed (not shown in the figure). Further as shown in timing 250, for partitions executed in parallel on multiple cores, a partition executed on one core will evict cache lines used in a shared cache by partitions executed on other cores, thereby causing cache interference.

[0005] Various approaches have been proposed to address the problem of cache interference in partitioned computing systems.

[0006] Figure 3An existing solution to solve cache interference in a partition system is shown. According to the solution, only one core (core 0) is enabled in a multi-core SoC, and the cache shared between serially executed partitions (partition A and partition D) is flushed and invalidated.

[0007] Figure 4 Another existing solution to solve cache interference in a partitioned system is shown. According to this solution, critical software partitions (partition B, partition E) are scheduled on only one core (core 1) for a period of time, and cache flushing and invalidation operations are performed before running these critical software partitions.

[0008] US Patent US 8069308 B2 uses cache coloring technology to ensure that critical software partitions have dedicated cache lines and memory pools.

[0009] Figure 5 A way-based cache partitioning method is shown, which is a hardware implementation method. As shown in the figure, the method colors the cache by way (as shown in different legends). The method has the advantage of low hardware cost. However, the method is limited by the number and allocation granularity of cache partitions, and is only supported on some processors.

[0010] Figure 6 A set-based cache partitioning method is shown, which is a software-implemented method. As shown in the figure, the method colors the cache by group, where one or more cache groups can be assigned the same cache color. In the case where multiple cache groups are assigned the same cache color, multiple consecutive or non-consecutive cache groups can be assigned the same cache color. This method is described in detail in U.S. Patent US 8069308 B2. This method has at least the following limitations: (i) Memory co-partitioning problem: page coloring simultaneously partitions the entire physical memory into multiple cache partitions. If a certain number of cache partitions are assigned to a task, the same number of memory partitions are also assigned to that task. However, the memory usage of a task is not necessarily related to its cache usage; (ii) Performance degradation: As the number of tasks increases, the amount of cache that can be used for a single task becomes less and less, which leads to performance degradation.

[0011] There is a need in the art for a technique that can alleviate cache interference in a partitioned computing system and maintain system performance. Summary of the invention

[0012] The present invention is provided in order to provide a technology capable of alleviating cache interference in a partitioned computing system and maintaining system performance.

[0013] According to one aspect of the present invention, a method for mitigating cache interference in a partitioned computing system is provided, comprising: performing cache coloring on a cache; assigning a cache group having a cache color to a partition executed serially; and, before the serially executed partition is executed, performing flush and invalidation operations on a cache group associated with an incoming partition that shares the same cache color as other serially executed partitions.

[0014] In the method as described above, the partitioned computing system is on a multi-core processor, and the cache includes a private cache of each core of the multi-core processor and a shared cache of the multi-core processor.

[0015] The method as described in any one of the above claims, further comprising: allocating cache groups having different cache colors as part of the shared cache to the partitions executing in parallel.

[0016] A method as described in any one of the above, wherein performing cache coloring comprises: translating a virtual address of a partition into a physical address; and associating the physical address with a specific cache group.

[0017] A method as described in any of the above, wherein converting the virtual address of the partition to the physical address comprises: converting the virtual address of the partition to the physical address by the operating system. A method as described in any of the above, wherein converting the virtual address of the partition to the physical address comprises: converting the virtual address of the partition to an intermediate physical address by the guest operating system; and converting the intermediate physical address to the physical address by the hypervisor.

[0018] A method as described in any one of the above, wherein performing cache coloring comprises: using overlapping bits between a physical page index bit of the physical address and a cache group index of the cache address for page coloring bits.

[0019] A method as described in any one of the above items, wherein the cache comprises a multi-way set associative cache.

[0020] According to another aspect of the present invention, a method for mitigating cache interference in a partitioned computing system is provided, comprising: performing cache coloring on a shared cache of a multi-core processor; and assigning cache groups with different cache colors to partitions executed in parallel on multiple cores of the multi-core processor, the cache groups being part of the shared cache.

[0021] The method as described above, wherein the partitions executed in parallel include: two or more partitions executed in parallel on two or more cores; and partitions including two or more processes executed in parallel on two or more cores.

[0022] The method for alleviating cache interference in a partitioned computing system according to the present invention can maintain the performance of the system while alleviating cache interference in the partitioned system. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A schematic diagram showing cache interference that occurs when partitions are executed serially.

[0024] Figure 2 A schematic diagram showing cache interference that occurs when partitions are executed in parallel.

[0025] Figure 3 An existing solution to address cache interference in a partitioned system is shown.

[0026] Figure 4 Another existing solution to address cache interference in a partitioned system is shown.

[0027] Figure 5 Shows a way-based cache partitioning method.

[0028] Figure 6 A group-based cache partitioning approach is shown.

[0029] Figure 7 The ARINC 653P1-5 scheduling paradigm for multi-core processors is shown.

[0030] Figure 8 A schematic diagram showing mitigation of cache interference through cache coloring and flushing according to an embodiment of the present invention.

[0031] Fig. 9 A schematic diagram showing mitigation of cache interference through cache coloring and flushing according to an embodiment of the present invention.

[0032] Fig.10 A schematic diagram showing the mapping between physical addresses and cache addresses according to an embodiment of the present invention.

[0033] Fig.11 A schematic diagram showing a process of implementing cache shading according to an embodiment of the present invention is shown.

[0034] Fig.12 A schematic diagram showing a process of implementing cache shading according to another embodiment of the present invention is shown.

[0035] Fig.13 A flow chart of a method for mitigating cache interference in a partitioned computing system according to an embodiment of the present invention is shown.

[0036] Fig.14 A flow chart of a method for mitigating cache interference in a partitioned computing system according to another embodiment of the present invention is shown. DETAILED DESCRIPTION

[0037] In this application, the term "partition" (as a noun) or "software partition" refers to a partition in a partitioned computing system that performs tasks, each partition being allocated independent memory and scheduled to perform tasks on processing resources (cores). The term "cache coloring" refers to the logical division and identification of a cache so that the cache can be divided into several cache areas by cache color. The term "cache group" refers to a portion of a cache, and cache coloring can be performed to manage one or more consecutive or non-consecutive cache groups as the same cache color. The term "flush" refers to transferring the contents of a cache to memory and clearing the cache.

[0038] Figure 7 The ARINC 653P1-5 scheduling paradigm for a multi-core processor is shown. As shown, multiple processes (process 1, process 2) within partition C can be scheduled to execute on different cores (core 2, core 3) at the same time. At the same time, multiple partitions (partition 1, partition 2, partition 3) can also be scheduled to execute on different cores (core 0, core 1, core 2, core 3) at the same time.

[0039] Figure 8 A schematic diagram showing mitigation of cache interference through cache coloring and flushing according to an embodiment of the present invention.

[0040] exist Figure 8 In FIG. 1 , different illustrations are used to illustrate that cache groups with different cache colors are assigned to corresponding partitions, wherein cache groups with different cache colors may include a single cache group assigned with one cache color or multiple cache groups with the same cache color assigned to the partitions. Figure 8 In the scenario shown in , there is a case where partitions executed serially on the same core share the same cache color (i.e., are assigned a cache group with the same cache color). For example, partition B (including its process 1 and process 2) and partition E (including process 1) executed serially on core 1 share the same cache color, and process 2 and partition G of partition C executed serially on core 3 share the same cache color.

[0041] In some embodiments, before the serially executed partitions are executed, the cache groups to which the partitions sharing the same cache color are assigned may be invalidated and flushed. Figure 8In the scenario shown in , flush and invalidate operations are performed on cache groups with the same color assigned to partitions B and E that are executed serially on core 1, and flush and invalidate operations are performed on cache groups with the same color assigned to partitions C and G that are executed serially on core 3. Partitions that are executed serially share the same cache area (including private cache and shared cache), thereby expelling each other's data. Flushing and invalidating operations on the cache area before the partition is executed can provide a deterministic state for the incoming partition. Since the invalidation and flushing are for the cache group rather than the entire cache, the flushing and invalidation operations take much less time. Recent caches (for example, caches in ARM processors) support flushing and invalidating caches by group or by way. Using such caches enables flushing and invalidating operations on cache groups (with corresponding cache colors) associated with the corresponding core.

[0042] In some embodiments, cache groups with different cache colors can be assigned to the partitions (e.g., partition A, partition B, and partition C) executing in parallel, and the cache group includes a portion of the shared cache of the processor. Thus, the partitions executing in parallel are assigned a shared cache so that each partition executing in parallel has its own private cache area in the shared cache. This ensures that one partition cannot evict the data of another partition.

[0043] like Figure 8 The process described in the above greatly reduces the processing time by flushing the cache groups and avoiding the flushing and invalidation of the entire cache. At the same time, the flexible combination of cache coloring and cache flushing and invalidation can achieve a balance between the determinism of the partition state and the system performance.

[0044] Fig. 9 A schematic diagram showing mitigation of cache interference through cache coloring and flushing according to an embodiment of the present invention.

[0045] exist Fig. 9 In FIG. 1 , different legends are used to illustrate that cache groups with different cache colors are assigned to corresponding partitions. Fig. 9 In the scenario shown in , there is a case where partitions executed serially on different cores share the same cache color (i.e., are assigned cache groups with the same cache color). For example, partition B executed on core 1 (including its processes 1 and 2) and partition E executed on core 2 (including process 1) share the same cache color, and partition D executed on core 0 and partition C executed on cores 2 and 3 share the same cache color.

[0046] In some embodiments, before the serially executed partitions are executed, the cache groups to which the partitions sharing the same cache color are assigned may be invalidated and flushed. Fig. 9In the scenario shown in , flush and invalidate operations are performed on cache groups with the same color assigned to partition B executed on core 1 and partition F executed on core 2, and flush and invalidate operations are performed on cache groups with the same color assigned to partition D executed on core 0 and partition C executed on cores 2 and 3. Partitions executed serially share the same cache area (including private cache and shared cache), thereby expelling each other's data. Flushing and invalidating operations on the cache area before the partition is executed can provide a deterministic state for the incoming partition. Since the invalidation and flushing are for the cache group rather than the entire cache, the flushing and invalidation operations take much less time. Recent caches (for example, caches in ARM processors) support flushing and invalidating caches by group or by way. Using such caches enables flushing and invalidating operations on cache groups (with corresponding cache colors) associated with the corresponding core.

[0047] In some embodiments, cache groups with different cache colors can be assigned to the partitions (e.g., partition A, partition B, and partition C) executing in parallel, and the cache group includes a portion of the shared cache of the processor. Thus, the partitions executing in parallel are assigned a shared cache so that each partition executing in parallel has its own private cache area in the shared cache. This ensures that one partition cannot evict the data of another partition.

[0048] like Fig. 9 The process described in the above greatly reduces the processing time by flushing the cache groups and avoiding the flushing and invalidation of the entire cache. At the same time, the flexible combination of cache coloring and cache flushing and invalidation can achieve a balance between the determinism of the partition state and the system performance.

[0049] pass Figure 8 and Fig. 9 The process shown in can alleviate cache interference between partitions and support application scenarios where multiple processes in a partition share memory between processes.

[0050] Fig.10 A schematic diagram showing the mapping between physical addresses and cache addresses according to an embodiment of the present invention.

[0051] Fig.101014. The format of the physical address 1010 shown in FIG. 1010 may include a physical page index 1012 and a page offset 1014. The format of the cache address 1020 may include a cache tag 1022, a group index 1024, and a cache line 1026. A physically indexed cache 1030 may use the physical address for indexing. Memory pages mapped to the same cache line may be assigned the same color. The overlapping bits between the cache group index 1024 and the physical page index 1012 may be referred to as page color bits 1025. Group-based cache coloring may use these page color bits 1025 to identify different colors. Here, one or more consecutive or non-consecutive cache groups may be managed as the same color through these overlapping bits.

[0052] Fig.11 A schematic diagram showing a process of implementing cache shading according to an embodiment of the present invention is shown.

[0053] exist Fig.11 Different cache colors or page colors are displayed in different legends. Fig.11 As described in, the Operating System (OS) may perform a translation of the virtual address mapping 1110 to the physical address mapping 1130, as indicated at 1120. The physical address may then be associated with a particular cache set by hardware (as shown by the 16-way set-associated L2 cache 1150), as indicated at 1140. The OS controls the mapping of a partition's virtual address to a physical address belonging to the same page color and cache color. The cache coloring establishes a virtual address to physical address translation such that no two partitions access the same cache set in a shared cache. Therefore, one partition will not evict a cache line that another partition has already fetched into the shared cache. Fig.11 The example process shown in can manage one or more contiguous or non-contiguous cache groups as the same cache color.

[0054] Fig.12 A schematic diagram showing a process of implementing cache shading according to another embodiment of the present invention is shown.

[0055] like Fig.11 The process of implementing cache coloring through the OS shown in has an impact on the internal structure of the Real Time Operating System (RTOS). Since the RTOS memory management function is about the memory area allocated for the kernel space, shared memory, partitions (e.g., ARINC 653 partitions), stacks, heaps, etc. are affected. Fig.12 Cache shading performed by the hypervisor in can solve the above problems.

[0056] exist Fig.12 Different cache colors or page colors are displayed in different legends. Fig.12, a virtual address mapping 1210 may be converted by a guest OS to an intermediate physical address mapping 1230, as shown at 1220. Specifically, the conversion may be implemented using the first level address translation of the MMU. The intermediate physical address mapping 1230 may be converted by the hypervisor to a physical address mapping 1250, as shown at 1240. Specifically, the conversion may be implemented using the second level address translation of the MMU. Physical addresses may be associated with specific cache groups (as shown by the 16-way set-associated L2 cache 1270) by hardware, as indicated at 1260. The hypervisor controls the mapping of virtual addresses of a partition to physical addresses belonging to the same page color and cache color. Fig.12 The example process shown in can manage one or more contiguous or non-contiguous cache groups as the same cache color.

[0057] As an example, the cache coloring process may be implemented using the open source hypervisor Xvisor.

[0058] With respect to cache coloring performed by the OS as shown in 11, Fig.12 The cache coloring performed by the hypervisor described in the embodiment is more sophisticated and cleaner, which allows the unmodified guest OS to benefit from the automatic cache coloring. At the same time, the cache coloring performed by the hypervisor is also unaware of the processes in the partition, which also helps to enable the cache interference mitigation method according to an embodiment of the present invention to also mitigate inter-core cache interference between processes in the partition.

[0059] Fig.13 A flow chart of a method 1300 for mitigating cache interference in a partitioned computing system according to one embodiment of the present invention is shown. The method 1300 can be applicable to a partitioned computing system on a single-core processor or a multi-core processor.

[0060] The method 1300 may include: performing coloring on the cache at block 1310. By performing coloring on the cache, each cache group may have a corresponding cache color.

[0061] The method 1300 may include, at block 1330 , assigning cache groups having cache colors to partitions that execute serially.

[0062] The method 1300 may include, at block 1350 , performing flush and invalidate operations on cache groups associated with incoming partitions that share the same cache color as other partitions that are executed serially, prior to execution of the partitions that are executed serially.

[0063] As an example, Figure 8As shown in , for partitions B and E that are executed serially on core 1, they are assigned cache groups with the same cache color, so before partitions B and E are executed, flush and invalid operations can be performed on the cache groups assigned to them. Similarly, before partitions C and G are executed, flush and invalid operations can be performed on the cache groups assigned to them.

[0064] As an example, Fig. 9 As shown in , for partitions C and D that are executed serially on different cores, they are assigned cache groups with the same cache color, so before partitions C and D are executed, flush and invalid operations can be performed on the cache groups assigned to them. Similarly, before partitions B and F are executed, flush and invalid operations can be performed on the cache groups assigned to them.

[0065] Since the invalidation and flushing is targeted at the cache group rather than the entire cache, the flush and invalidation operations take much less time.

[0066] In some embodiments, the partitioned computing system may be on a multi-core processor, and the cache may include a private cache of each core of the multi-core processor and a shared cache of the multi-core processor.

[0067] In some embodiments, method 1300 may further include, at block 1370, assigning cache groups that are part of a shared cache and have different cache colors to the partitions executing in parallel. The cache groups assigned to the partitions executing in parallel may be cache groups that are part of a shared cache and have different cache colors. This may be as follows: Figure 8 and Fig. 9 As shown in FIG. 1 , cache groups with different cache colors are assigned to the partitions executed in parallel. By assigning a portion of the shared cache to the partitions executed in parallel as their private portion, one partition will not evict the data of other partitions, thereby alleviating cache interference.

[0068] The execution order of the steps in box 1370 relative to the steps in box 1310, box 1330, and box 1350 is not limited. As an example, the steps in box 1370 may be performed before or after the steps in box 1310, box 1330, and box 1350, or at least partially in parallel with the steps in box 1310, box 1330, and box 1350.

[0069] In some embodiments, performing the steps in block 1310 may include, in block 1312, translating the virtual address of the partition into a physical address. In some embodiments, performing the steps in block 1312 may include, by the OS, translating the virtual address of the partition into a physical address. This may be done as follows: Fig.11 As shown at 1120 in FIG.

[0070] In some embodiments, performing the steps in block 1312 may include: translating the virtual address, by the guest OS, into an intermediate physical address. This may be as follows: Fig.12 In some embodiments, the steps in block 1312 may also include: converting the intermediate physical address to the physical address by the hypervisor. This may be as shown in FIG. Fig.12 As shown at 1240 in FIG. Cache shading performed by the hypervisor is more sophisticated and cleaner than cache shading performed by the OS, which allows an unmodified guest OS to benefit from automatic cache shading. At the same time, cache shading performed by the hypervisor is also unaware of the processes in the partition, which also helps to enable the method for mitigating cache interference according to an embodiment of the present invention to also mitigate inter-core cache interference between processes in the partition.

[0071] Executing the steps in block 1310 may also include associating the physical address with a particular cache group at block 1314. The steps in block 1314 may be performed by hardware. This may be performed as follows: Fig.11 1140 of them and Fig.12 As shown in 1260.

[0072] In some embodiments, performing the steps in block 1310 may include using the overlapping bits between the physical page index bits of the physical address and the cache group index of the cache address for the page coloring bits. This may be done as follows: Fig.10 as shown in .

[0073] In some embodiments, the cache may be an N-way set associative cache.

[0074] Fig.14 A flow chart of a method 1400 for mitigating cache interference in a partitioned computing system according to another embodiment of the present invention is shown. The method 1400 is applicable to multiple parallel partitions executed in a partitioned computing system on a multi-core processor.

[0075] The method 1400 may include, at block 1410 , performing cache coloring on a shared cache of a multi-core processor.

[0076] Method 1400 may include, at block 1430, assigning cache groups having different cache colors to partitions executing in parallel on multiple cores of a multi-core processor, the cache groups being part of a shared cache. This may be done as follows: Figure 8 and Fig. 9 As shown in FIG. 1 , cache groups with different cache colors are assigned to the partitions executed in parallel. By assigning a portion of the shared cache to the partitions executed in parallel as their private portion, one partition will not evict the data of other partitions, thereby alleviating cache interference.

[0077] In some embodiments, the partitions executed in parallel may include two or more partitions executed in parallel on two or more cores (e.g., Figure 8 , Fig. 9 A partition A, a partition B in ). A partition executed in parallel may also include a partition whose two or more processes are executed in parallel on two or more cores (e.g., Figure 8 , Fig. 9 Partition C).

[0078] The method according to an embodiment of the present invention can alleviate cache interference in a partitioned computing system. Some embodiments can use accurate cache flushing and invalidation operations based on cache groups to greatly reduce the time of cache operations, thereby solving the limitations of page coloring schemes currently used for multi-core processors. Some embodiments can flexibly combine cache coloring with cache flushing and invalidation to seek a balance between the determinism of partition state and system performance. Further embodiments can use a hypervisor to perform cache coloring, which is further superior to the scheme of performing cache coloring through the OS.

[0079] Experimental results show that cache shading and cache block allocation greatly improve the worst-case memory access bandwidth (up to 1.2-12.0 times) and reduce cache interference (down to 15.4%-66.4% of the original level).

[0080] The method according to an embodiment of the present invention performs cache flushing and invalidation operations according to cache groups, which greatly reduces the time compared to performing flushing and invalidation operations on the entire cache. As an example, if there are 10 cache colors for the same cache size, performing flushing and invalidation operations on a cache group with one cache color only takes 10% of the above overall time.

Claims

1. A method for mitigating cache interference in a partitioned computing system, comprising: Perform cache shading on the cache; Assign cache groups with cache colors to partitions that execute serially; as well as Prior to execution of the serially executed partitions, flush and invalidate operations are performed on cache groups associated with incoming partitions that share the same cache color as other serially executed partitions.

2. The method according to claim 1, characterized in that The partitioned computing system is on a multi-core processor, and The cache includes a private cache of each core of the multi-core processor and a shared cache of the multi-core processor.

3. The method according to claim 2, characterized in that Also includes: Cache groups that are part of the shared cache and have different cache colors are assigned to the partitions that execute in parallel.

4. The method according to claim 1, characterized in that Executing cache shading involves: Converting a virtual address of the partition to a physical address; and The physical address is associated with a particular cache set.

5. The method according to claim 4, characterized in that Converting the virtual address of the partition into a physical address includes: converting the virtual address of the partition into a physical address by the operating system.

6. The method according to claim 4, characterized in that Converting a partition's virtual address to a physical address involves: The guest operating system translates the virtual address of the partition into an intermediate physical address; and The intermediate physical address is translated into the physical address by the hypervisor.

7. The method according to claim 1, characterized in that Performing cache coloring includes using overlapping bits between physical page index bits of the physical address and a cache set index of the cache address for page coloring bits.

8. The method according to claim 1, characterized in that The cache comprises a multi-way set associative cache.

9. A method for mitigating cache interference in a partitioned computing system, comprising: Perform cache coloring on shared caches of multi-core processors; as well as Cache groups with different cache colors are assigned to partitions that are executed in parallel on multiple cores of the multi-core processor, the cache groups being part of the shared cache.

10. The method according to claim 9, characterized in that: The partitions executed in parallel include: two or more partitions executed in parallel on two or more cores; and Partitioning includes two or more processes that execute in parallel on two or more cores.

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