Memory neural circuit, neural circuit array and memory neural network

Abstract

The invention discloses a memory neural circuit, a neural circuit array and a memory neural network, and relates to the technical field of analog digital circuits. The circuit comprises seven transistors, a capacitor, six signal input ends and an output end Output, wherein the seven transistors are respectively a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor. The neural circuit disclosed by the invention can effectively process light, pressure and chemical signals by integrating a long-term memory function and a multi-mode signal processing capability, so that the neural circuit adapts to various application scenes, the dependence of a traditional scheme on electric signals is broken through, and the circuit realizes higher flexibility and adaptability by directly receiving and processing various types of input signals; in addition, the circuit simulates behaviors and characteristics of neurons, has efficient signal processing and memory functions, and performs long-term memory storage by realizing mechanisms such as synaptic plasticity and long-term enhancement, so that information processing is more stable and reliable.

Description

Technical Field

[0001] The present invention relates to the field of analog digital circuit technology, in particular to a memory neural circuit, a neural circuit array and a memory neural network. Background Art

[0002] Synapses are important basic units for training memory and processing data in the human brain. Therefore, developing new materials and new structures and studying the plasticity of synapses based on new artificial materials and optoelectronic devices are of great significance to the research of neuromorphic devices and the realization of brain-like hardware design. At present, common solutions for synaptic device technology include simulated resistive synaptic devices, phase change material synaptic devices, electrochemical synaptic devices, and organic synaptic devices.

[0003] Using circuits to simulate neuron behavior is also one of the directions for simulating synaptic functions. Currently, the existing technical solutions include I&F Neuron Circuits (I&F), Leaky Integrate-and-Fire (LIF), NeuronCircuits, Spiking Neural Networks (SNNs) and Analog Synapse Circuits. Among the existing neuron circuit solutions, I&F and LIF models can basically simulate the firing mechanism of neurons, but they mainly rely on electrical signal processing and cannot effectively process light, pressure and chemical signals. Although SNNs can simulate the behavior of spiking neurons, they need to convert non-electrical signals into electrical signals. Therefore, due to the limitations of materials and processes, existing technologies can usually only achieve short-term information storage and lack support for long-term memory. For this reason, we propose memory neural circuits, neural circuit arrays and memory neural networks. Summary of the invention

[0004] The purpose of the present invention is to provide a memory neural circuit, a neural circuit array and a memory neural network to solve the problems raised in the above-mentioned background technology.

[0005] According to a first aspect of the present invention, in order to achieve the above-mentioned purpose, the present invention provides the following technical solutions: a memory neural circuit, comprising seven transistors, a capacitor, six signal input terminals and an output terminal Output, the seven transistors are respectively a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor, the six signal input terminals are respectively a Vstimulus input terminal connected to the second transistor and the fourth transistor, a Sn input terminal connected to the second transistor, a Sn-1 input terminal connected to the fourth transistor, a VINT input terminal connected to the capacitor, an RD input terminal connected to the fifth transistor, and an ELVDD input terminal, and the output terminal Output is connected to the sixth transistor;

[0006] The second transistor, the third transistor, the seventh transistor and the input terminals Sn, Vstimulus and VINT constitute a reset unit of the circuit, which is used to clear or reset the signals of each node in the circuit;

[0007] The first transistor, the second transistor, the third transistor, the fourth transistor, the capacitor and the input terminals Sn-1, Sn, and Vstimulus constitute a signal receiving and memory unit of the circuit, which is used to realize signal conversion and memory;

[0008] The first transistor, the fifth transistor, the sixth transistor, the input terminal RD[N], ELVDD, and the output terminal Output constitute a signal reading and transmitting unit of the circuit, which is used to realize signal conversion and transmission.

[0009] Furthermore, the second transistor, the third transistor and the seventh transistor in the reset unit are electrically connected through wires, and the input control signal at the input terminal Sn can turn on the second transistor, the third transistor and the seventh transistor. At this time, the VINT input terminal receives the signal and writes it into each node inside the circuit to achieve the potential reset of the transistor gate and the capacitor.

[0010] Furthermore, the input end of the first transistor in the signal receiving and memory unit is connected to the output end of the second transistor, the second transistor and the third transistor are electrically connected through a wire, the input end of the third transistor is connected to the capacitor, the output end of the fourth transistor is connected to the capacitor, and the input end Sn-1 inputs a control signal to turn on the fourth transistor. At this time, Vstimulus inputs an excitation signal, and the signal voltage is recorded at both ends of the capacitor to realize the conversion of the current signal to the voltage signal for signal reception, and then the third transistor and the fourth transistor are turned off to realize signal latch memory.

[0011] Furthermore, the output end of the first transistor in the signal reading and transmission unit is connected to the input end of the sixth transistor, the sixth transistor is connected to the output end Output, the fifth transistor and the sixth transistor are electrically connected through a wire, and the input signal at the input end RD[N] causes the fifth transistor and the sixth transistor to be turned on. At this time, the capacitor controls the first transistor to convert the recorded voltage signal into a current signal, which is used to realize the output and transmission of the signal from the Output port.

[0012] Furthermore, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor and the seventh transistor may be configured as NPN transistors, PNP transistors or CMOS transistors.

[0013] Furthermore, a diode is connected in series to the Vstimulus input terminal for inputting a pressure signal, a chemical stimulation signal or a light stimulation signal;

[0014] Or a sensor is connected in series to sense external stimulation signals and convert the signals into electrical stimulation signals before inputting them into the circuit.

[0015] According to a second aspect of the present invention, the present invention provides a neural circuit array, comprising a plurality of the above-mentioned memory neural circuits, wherein the plurality of memory neural circuits are assigned to logic rows and logic columns of the neural circuit array, and:

[0016] The Vstimulus input terminal of the memory neural circuit in each column is connected to the Output output terminal of the previous memory neural circuit, and is used to receive a stimulus signal from the corresponding previous memory neural circuit in use;

[0017] The Sn-1 input terminal of the previous memory neural circuit in each row is connected to the Sn-1 input terminal of the next memory neural circuit, so as to transmit the action signal from the previous memory neural circuit to the next during use.

[0018] According to a third aspect of the present invention, the present invention provides a memory neural network, comprising the above-mentioned neural circuit array.

[0019] The present invention has at least the following beneficial effects:

[0020] The neural circuit of the present invention integrates long-term memory function and multimodal signal processing capabilities, can effectively process light, pressure and chemical signals, and adapt to various application scenarios, breaking through the traditional solution's reliance on electrical signals. By directly receiving and processing various types of input signals, the circuit achieves higher flexibility and adaptability. In addition, the circuit simulates the behavior and characteristics of neurons, has efficient signal processing and memory functions, and performs long-term memory storage by realizing mechanisms such as synaptic plasticity and long-term potentiation, making information processing more stable and reliable.

[0021] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 is a schematic diagram of the structure of the neural circuit in the present invention;

[0023] Figure 2 is a diagram of the structure of a neural circuit in Embodiment 1 of the present invention;

[0024] Figure 3 is a diagram of the structure of a neural circuit in Embodiment 2 of the present invention;

[0025] Figure 4 is a substructure diagram of a single memory neural circuit in Embodiment 3 of the present invention;

[0026] Figure 5It is a schematic diagram of the structure of the neural circuit array in Example 3 of the present invention.

[0027] Reference numerals:

[0028] T1, a first transistor; T2, a second transistor; T3, a third transistor; T4, a fourth transistor; T5, a fifth transistor; T6, a sixth transistor; T7, a seventh transistor; C1, a capacitor. DETAILED DESCRIPTION

[0029] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0030] See also Figure 1-Figure 2 The present invention provides a technical solution: a memory neural circuit, a neural circuit array and a memory neural network, including seven transistors, a capacitor C1, six signal input terminals and an output terminal Output, the seven transistors are respectively a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a seventh transistor T7, the six signal input terminals are respectively a Vstimulus input terminal connected to the second transistor T2 and the fourth transistor T4, a Sn-1 input terminal connected to the second transistor T2Sn input terminal, a Sn-1 input terminal connected to the fourth transistor T4, a VINT input terminal connected to the capacitor C1, an RD input terminal connected to the fifth transistor T5, and an ELVDD input terminal, and the output terminal Output is connected to the sixth transistor T6;

[0031] It should be noted that the Vstimulus port mainly inputs excitation signals, which are used to input synaptic electrical stimulation (or various forms of signals such as light stimulation) of simulated nerves. The electrical signals include various types such as DC, AC and pulse.

[0032] Sn, Sn-1: mirror pulse input signal, used to control the timing control signal of signal writing and internal circuit reset;

[0033] Vint: DC input signal, used to reset and initialize the capacitor C1 and the transistor signal;

[0034] ELVDD: DC input signal, used to provide power for circuit operation;

[0035] RD: Circuit signal output control signal, which can be DC, AC or pulse signal, used to control the neural circuit to convert and output the electrical stimulation signal to the next node after memory (can be cascaded);

[0036] Output: Output signal, which is the electrical stimulation signal that the neural circuit memorizes and converts into an output to the next node.

[0037] With respect to the technical solution of this embodiment, from the perspective of functional units, the circuit mainly includes three parts: a reset unit, a signal receiving and memory unit, and a signal reading and transmitting unit, which respectively correspond to the presynaptic, synaptic cleft, and postsynaptic functions of the nerve;

[0038] The second transistor T2, the third transistor T3, the seventh transistor T7 and the input terminals Sn, Vstimulus and VINT constitute a reset unit of the circuit, which is used to clear or reset the signals of each node in the circuit;

[0039] The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the capacitor C1 and the input terminals Sn-1, Sn, and Vstimulus constitute a signal receiving and memory unit of the circuit, which is used to realize signal conversion and memory;

[0040] The first transistor T1 , the fifth transistor T5 , the sixth transistor T6 , the input terminal RD[N], ELVDD, and the output terminal Output constitute a signal reading and transmitting unit of the circuit, which is used to realize signal conversion and transmission.

[0041] With respect to the technical solution of this embodiment, the second transistor T2, the third transistor T3 and the seventh transistor T7 in the reset unit are electrically connected through wires, and the input terminal Sn inputs a control signal that can turn on the second transistor T2, the third transistor T3 and the seventh transistor T7. At this time, the VINT input terminal receives a signal and writes it into each node inside the circuit, so that the voltage signal across the capacitor C1 is reset or cleared. At this time, the capacitor C1 is connected to the first transistor T1, which can realize the resetting of the gate potential of the first transistor T1.

[0042] With respect to the technical solution of this embodiment, the input end of the first transistor T1 in the signal receiving and memory unit is connected to the output end of the second transistor T2, the second transistor T2 and the third transistor T3 are electrically connected through a wire, the input end of the third transistor T3 is connected to the capacitor C1, the output end of the fourth transistor T4 is connected to the capacitor C1, and the input end Sn-1 inputs a control signal to turn on the fourth transistor T4. At this time, Vstimulus inputs an excitation signal, and the signal voltage is recorded at both ends of the capacitor C1 to realize the conversion of the current signal to the voltage signal for realizing signal reception. Subsequently, the second transistor T2, the third transistor T3 and the fourth transistor T4 are turned off. At this time, the signal recorded at both ends of the capacitor C1 will be latched at the position of the first transistor T1, thereby realizing signal latch memory.

[0043] According to the technical solution of this embodiment, the output end of the first transistor T1 in the signal reading and transmission unit is connected to the input end of the sixth transistor T6, the sixth transistor T6 is connected to the output end Output, the fifth transistor T5 and the sixth transistor T6 are electrically connected through a wire, and the input end RD[N] inputs a signal to turn on the fifth transistor T5 and the sixth transistor T6. At this time, the capacitor C1 controls the first transistor T1 to convert the recorded voltage signal into a current signal. At this time, the current signal will be output through the sixth transistor T6 and the Output port connected to it, thereby realizing the output or transmitting the signal to the next level.

[0044] Furthermore, the first transistor T1 , the second transistor T2 , the third transistor T3 , the fourth transistor T4 , the fifth transistor T5 , the sixth transistor T6 and the seventh transistor T7 may be configured as NPN transistors, PNP transistors or CMOS transistors.

[0045] Specifically, in actual use, the memory neural circuit first needs to input a signal through the VINT input terminal and write it into each node inside the circuit to reset the potential of the transistor gate and the capacitor C1, and then input an excitation signal through Vstimulus. The signal voltage is recorded at both ends of the capacitor C1 to realize the conversion of the current signal to the voltage signal. Subsequently, the second transistor T2, the third transistor T3 and the fourth transistor T4 are turned off to latch the signal to realize the memory function, and then the fifth transistor T5 and the sixth transistor T6 are turned on. The capacitor C1 controls the first transistor T1 to realize the conversion of the voltage signal into a current signal, which is read out by the Output-IPSC port or transmitted to the next level of neurons. Finally, the signal reading and transmission unit and the reset and reset unit are turned off, and the Vstimulus input terminal continues to receive the excitation signal of the external or previous level of neurons, thus completing a cycle. At the same time, this step can also enter the signal reset step.

[0046] Embodiment 2:

[0047] like Figure 3 As shown, the fundamental difference between the second embodiment and the first embodiment is that: a diode is connected in series to the Vstimulus input terminal, so that the Vstimulus input terminal can input a pressure signal, a chemical stimulation signal or a light stimulation signal when the input electrical signal simulates the performance of the electrical synapse;

[0048] The Vstimulus input terminal can also be connected in series with a sensor to sense external stimulation signals and convert the signals into electrical stimulation signals before inputting them into the circuit.

[0049] Embodiment three:

[0050] like Figure 4-Figure 5 As shown, this embodiment provides a neural circuit array, comprising a plurality of the above-mentioned memory neural circuits, wherein the plurality of memory neural circuits are assigned to logic rows and logic columns of the neural circuit array, and:

[0051] The Vstimulus input terminal of the memory neural circuit in each column is connected to the Output output terminal of the previous memory neural circuit, and is used to receive a stimulus signal from the corresponding previous memory neural circuit in use;

[0052] The Sn-1 input terminal of the previous memory neural circuit in each row is connected to the Sn-1 input terminal of the next memory neural circuit, so as to transmit the action signal from the previous memory neural circuit to the next during use.

[0053] It should be noted that Figure 4 The cascade wiring of a single neural circuit subunit is shown. Each memory neural circuit can be used as a neuron synapse subunit. Multiple units are cascaded together to form a mesh neural circuit array, such as Figure 5 As shown, the output signal of the previous stage circuit is used as the input excitation signal of the next stage circuit, and the scale of the specific array can be expanded in three dimensions according to actual needs.

[0054] Embodiment 4:

[0055] This embodiment provides a memory neural network, including the above-mentioned neural circuit array.

[0056] In summary, the neural circuit of the present invention can effectively process light, pressure and chemical signals by integrating long-term memory function and multimodal signal processing capabilities, so that it can adapt to various application scenarios, breaking through the traditional solution's dependence on electrical signals. By directly receiving and processing various types of input signals, the circuit achieves higher flexibility and adaptability. In addition, the circuit simulates the behavior and characteristics of neurons, has efficient signal processing and memory functions, and performs long-term memory storage by realizing mechanisms such as synaptic plasticity and long-term potentiation, making information processing more stable and reliable.

[0057] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0058] For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to the specific circumstances. When an element is referred to as being "assembled on", "installed on", "fixed on" or "set on" another element, it can be directly on the other element or there can also be a centered element. When an element is considered to be "connected" to another element, it can be directly connected to the other element or there may be a centered element at the same time. The terms "vertical", "horizontal", "up", "down", "left", "right" and similar expressions used herein are only for illustrative purposes and are not intended to be the only implementation method.

[0059] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

[0060] In the description of this specification, the description with reference to the terms "one embodiment", "example", "specific example", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

Claims

1. A memory neural circuit, characterized in that It includes seven transistors, a capacitor, six signal input terminals and an output terminal Output, the seven transistors are respectively a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor, the six signal input terminals are respectively a Vstimulus input terminal connected to the second transistor and the fourth transistor, a Sn input terminal connected to the second transistor, a Sn-1 input terminal connected to the fourth transistor, a VINT input terminal connected to the capacitor, an RD input terminal connected to the fifth transistor, and an ELVDD input terminal, and the output terminal Output is connected to the sixth transistor; The second transistor, the third transistor, the seventh transistor and the input terminals Sn, Vstimulus and VINT constitute a reset unit of the circuit, which is used to clear or reset the signals of each node in the circuit; The first transistor, the second transistor, the third transistor, the fourth transistor, the capacitor and the input terminals Sn-1, Sn, and Vstimulus constitute a signal receiving and memory unit of the circuit, which is used to realize signal conversion and memory; The first transistor, the fifth transistor, the sixth transistor, the input terminal RD[N], ELVDD, and the output terminal Output constitute a signal reading and transmitting unit of the circuit, which is used to realize signal conversion and transmission.

2. The memory neural circuit according to claim 1, characterized in that: The second transistor, the third transistor and the seventh transistor in the reset unit are electrically connected through wires, and the input control signal at the input terminal Sn can turn on the second transistor, the third transistor and the seventh transistor. At this time, the VINT input terminal receives the signal and writes it into each node inside the circuit to achieve the potential reset of the transistor gate and the capacitor.

3. The memory neural circuit according to claim 2, characterized in that: The input end of the first transistor in the signal receiving and memory unit is connected to the output end of the second transistor, the second transistor and the third transistor are electrically connected through a wire, the input end of the third transistor is connected to a capacitor, the output end of the fourth transistor is connected to a capacitor, and the input end Sn-1 inputs a control signal to turn on the fourth transistor. At this time, Vstimulus inputs an excitation signal, and the signal voltage is recorded at both ends of the capacitor to realize the conversion of the current signal to the voltage signal for signal reception. Subsequently, the second transistor, the third transistor and the fourth transistor are turned off to realize signal latch memory.

4. The memory neural circuit according to claim 3, characterized in that: The output end of the first transistor in the signal reading and transmission unit is connected to the input end of the sixth transistor, the sixth transistor is connected to the output end Output, the fifth transistor and the sixth transistor are electrically connected through a wire, and the input end RD[N] inputs a signal to turn on the fifth transistor and the sixth transistor. At this time, the capacitor controls the first transistor to convert the recorded voltage signal into a current signal, which is used to realize the output and transmission of the signal from the Output port.

5. The memory neural circuit according to claim 4, characterized in that: The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor and the seventh transistor may be configured as NPN transistors, PNP transistors or CMOS transistors.

6. The memory neural circuit according to claim 1, characterized in that: The Vstimulus input terminal is connected in series with a diode for inputting a pressure signal, a chemical stimulation signal or a light stimulation signal; Or a sensor is connected in series to sense external stimulation signals and convert the signals into electrical stimulation signals before inputting them into the circuit.

7. A neural circuit array, comprising a plurality of memory neural circuits according to any one of claims 1 to 6, characterized in that: A plurality of memory neural circuits are assigned to logical rows and logical columns of the neural circuit array, and: The Vstimulus input terminal of the memory neural circuit in each column is connected to the Output output terminal of the previous memory neural circuit, and is used to receive a stimulus signal from the corresponding previous memory neural circuit in use; The Sn-1 input terminal of the previous memory neural circuit in each row is connected to the Sn-1 input terminal of the next memory neural circuit, so as to transmit the action signal from the previous memory neural circuit to the next during use.

8. A memory neural network, characterized in that: Comprising a neural circuit array as claimed in claim 7.

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