Deep groove isolation structure and manufacturing method thereof

Abstract

The invention provides a deep groove isolation structure and a manufacturing method thereof. The deep groove isolation structure comprises a substrate; the deep groove is located in the substrate; the dielectric layer covers the side wall and the bottom of the deep groove; the through groove penetrates through a part of the dielectric layer located at the bottom of the deep groove and exposes the substrate; the first semiconductor material layer is a P-type epitaxial layer, fills the through groove and is connected with the substrate; and the second semiconductor material layer fills the deep groove and is connected with the first semiconductor material layer, and the second semiconductor layer at the top of the deep groove has metal contact. According to the invention, the filling difficulty of the deep groove is reduced, the resistance of electrical connection between the second semiconductor material layer in the deep groove and the P-type lightly doped epitaxial layer of the substrate is reduced, and the uniformity and stability of electrical connection are improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a deep trench isolation structure and a manufacturing method thereof. Background Art

[0002] Common device isolation technologies include PN junction isolation, LOCOS isolation, trench isolation, and full dielectric isolation (SOI). As the voltage withstand requirements for high-voltage devices continue to increase, deep trench isolation (DTI) has gradually become the mainstream isolation process for high-voltage devices. Compared with PN junction isolation, DTI significantly improves isolation effectiveness, reduces shutdown current, increases breakdown voltage, reduces chip size, increases IC device density, and improves device reliability. For example, the alpha (amplification factor) of a parasitic NPN transistor in adjacent devices at the same distance can be reduced by 1 / 10 after using DTI, significantly reducing the possibility of parasitic transistor malfunction.

[0003] However, to ensure better isolation and minimize leakage, DTI trenches are becoming increasingly deeper. However, as trenches become deeper, the fabrication of deep trench isolation structures presents process difficulties, primarily in trench etching, cleaning, and filling.

[0004] How to overcome process difficulties to ensure the isolation effect of the deep trench isolation structure is a technical problem that technical personnel in this field urgently need to solve. Summary of the Invention

[0005] The object of the present invention is to provide a deep trench isolation structure and a manufacturing method thereof, which effectively reduces the technical difficulty of the deep trench isolation structure and improves the uniformity and stability of the electrical connection between the deep trench isolation structure and the substrate.

[0006] To solve the above technical problems, according to a first aspect of the present invention, a deep trench isolation structure is provided, comprising: substrate; a deep trench located in the substrate; a dielectric layer covering the sidewalls and bottom of the deep trench; A through trench, penetrating a portion of the dielectric layer located at the bottom of the deep trench to expose the substrate; a first semiconductor material layer, wherein the first semiconductor material layer is a P-type epitaxial layer, the first semiconductor material layer fills the through-groove and is connected to the substrate; and The second semiconductor material layer fills the deep trench and is connected to the first semiconductor material layer. The second semiconductor material layer at the top of the deep trench has a metal contact.

[0007] Optionally, the material of the first semiconductor material layer is the same as that of the substrate.

[0008] Optionally, the electrical conductivity of the first semiconductor material layer is between that of the second semiconductor material layer and the substrate.

[0009] Optionally, the second semiconductor material layer includes a polycrystalline state and / or an amorphous state.

[0010] Optionally, the polycrystalline state and / or amorphous state is heavily P-type doped.

[0011] Optionally, the doping concentration of P-type ions in the P-type heavy doping is greater than or equal to 5×10 19 cm -3 , less than or equal to 2x10 22 cm -3 .

[0012] Optionally, the material of the second semiconductor material layer includes one or a combination of silicon, germanium, gallium arsenide and indium phosphide.

[0013] Optionally, the dielectric layer comprises one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, and silicon carbonitride.

[0014] Optionally, the dielectric layer is a stacked structure consisting of a silicon oxide layer and a silicon nitride layer.

[0015] To solve the above technical problems, according to a second aspect of the present invention, a method for manufacturing a deep trench isolation structure is provided, comprising the following steps: providing a substrate; forming a deep trench, wherein the deep trench is located in the substrate; forming a dielectric layer, wherein the dielectric layer covers the sidewalls and the bottom of the deep trench; removing a portion of the dielectric layer at the bottom of the deep trench to form a through trench exposing the substrate; forming a first semiconductor material layer in the through-groove and a second semiconductor material layer in the deep trench by an epitaxial process, wherein the first semiconductor material layer is a P-type epitaxial layer; and A metal contact is formed on the second semiconductor material layer at the top of the deep trench.

[0016] Compared with the prior art, in the deep trench isolation structure and the manufacturing method thereof provided by the present invention, after removing part of the dielectric layer at the bottom of the deep trench to form a through trench exposing the substrate, a first semiconductor material layer is formed in the through trench and a second semiconductor material layer is formed in the deep trench by an epitaxial process. The first semiconductor material layer is a P-type epitaxial layer, thereby reducing the difficulty of filling the deep trench and reducing the resistance of the electrical connection between the second semiconductor material layer in the deep trench and the substrate, thereby improving the uniformity and stability of the electrical connection.

[0017] In addition, since the through trench and the deep trench are filled by adopting the epitaxial process, there is no need to purchase an additional machine to fill the deep trench, which reduces the process cost and improves the process compatibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a schematic diagram of the first deep trench isolation structure.

[0019] Figure 2 It is a schematic diagram of the second deep trench isolation structure.

[0020] Figure 3 It is a schematic diagram of the third deep trench isolation structure.

[0021] Figure 4 It is a schematic diagram of the fourth deep trench isolation structure.

[0022] Figure 5 It is a schematic diagram of the fifth deep trench isolation structure.

[0023] Figure 6 FIG. 1 is a schematic diagram of a deep trench isolation structure provided by an embodiment of the present invention.

[0024] Figure 7 4 is a flow chart of a method for manufacturing a deep trench isolation structure provided by one embodiment of the present invention.

[0025] Description of reference numerals: 10 - deep trench; 11 - through trench; 20 - dielectric layer; 21 - silicon nitride layer; 22 - silicon oxide layer; 30 - isolation layer; 40 - semiconductor material layer; 41 - first semiconductor material layer; 42 - second semiconductor material layer; 100 - substrate. DETAILED DESCRIPTION

[0026] Figures 1 to 5 Schematic diagrams of several deep trench isolation structures are shown.

[0027] Please refer to Figure 1As shown, a dielectric layer 20 is formed on the sidewalls and bottom of the deep trench 10, and an isolation layer 30 is filled in the deep trench 10. The material of the dielectric layer 20 includes silicon oxide, and the material of the isolation layer 30 also includes silicon oxide, that is, the deep trench 10 is only filled with silicon oxide. Figure 1 The deep trench isolation structure shown in the figure has excessive internal stress (overstress), which causes the wafer to deform or even warp, affecting device performance and may even lead to loose wafer adhesion and cause wafer breakage.

[0028] Please refer to Figure 2 As shown, a dielectric layer 20 is formed on the sidewalls and bottom of the deep trench 10. A semiconductor material layer 40 is filled in the deep trench 10. A dielectric layer 20 is also formed on the semiconductor material layer 40, that is, on the top of the deep trench 10. That is, the dielectric layer 20 surrounds the semiconductor material layer 40. In this embodiment, the material of the dielectric layer 20 is silicon oxide, and the material of the semiconductor material layer 40 is polycrystalline silicon. Figure 2 The deep trench isolation structure shown in the figure ensures the flatness of the wafer because polysilicon grows synchronously on the front and back sides of the wafer. The device uniformity corresponding to this structure is also relatively good.

[0029] Please refer to Figure 3 As shown, a dielectric layer 20 is formed on the sidewalls and bottom of the deep trench 10, a semiconductor material layer 40 is filled in the deep trench 10, and a dielectric layer 20 is also formed on the top of the semiconductor material layer 40. The dielectric layer 20 surrounds the semiconductor material layer 40, and a through groove is formed at the bottom of the deep trench 10. A portion of the semiconductor material layer 40 is exposed at the top of the deep trench 10. The exposed semiconductor material layer 40 has a metal contact, that is, the top of the semiconductor material layer 40 is grounded. In this embodiment, the material of the dielectric layer 20 is silicon oxide, and the semiconductor material layer 40 is P + Polysilicon (P + poly-Si). Figure 3 The manufacturing process of the deep trench isolation structure shown is complex, but the isolation performance is better and the uniformity of the structure is better. However, since P + Polysilicon, additional filling P is required + Polysilicon machine.

[0030] Please refer to Figure 4As shown, a dielectric layer 20 is formed on the sidewalls and bottom of the deep trench 10. The dielectric layer 20 includes a silicon nitride layer 21 covering the sidewalls and bottom of the deep trench 10 and a silicon oxide layer 22 covering the silicon nitride layer 21. The deep trench 10 is filled with a semiconductor material layer 40. A silicon oxide layer 22 is also formed on top of the semiconductor material layer 40. The silicon oxide layer 22 surrounds the semiconductor material layer 40. In this embodiment, the semiconductor material layer 40 is polycrystalline silicon. Figure 4 The manufacturing process of the deep trench isolation structure is complex and the manufacturing cost is relatively high.

[0031] Please refer to Figure 5 As shown, a dielectric layer 20 is formed on the sidewalls and bottom of the deep trench 10. The dielectric layer 20 includes a silicon nitride layer 21 covering the sidewalls and bottom of the deep trench 10 and a silicon oxide layer 22 covering the silicon nitride layer 21. A semiconductor material layer 40 is filled in the deep trench 10, and a silicon oxide layer 22 is also formed on the top of the semiconductor material layer 40. The silicon oxide layer 22 surrounds the semiconductor material layer 40. A through groove is formed at the bottom of the deep trench 10, and a portion of the semiconductor material layer 40 is exposed at the top of the deep trench 10. The exposed semiconductor material layer 40 has a metal contact, that is, the top of the semiconductor material layer 40 is grounded. In this embodiment, the material of the semiconductor material layer 40 is P + Polysilicon. Figure 5 The manufacturing process of the deep trench isolation structure shown is complex, but the isolation performance is better and the uniformity of the structure is better. However, since P + Polysilicon, additional filling P is required + Polysilicon machine.

[0032] In response to the problems existing in the above-mentioned various deep trench isolation structures, the present invention provides a deep trench isolation structure, comprising: a substrate; a deep trench located in the substrate; a dielectric layer covering the sidewalls and bottom of the deep trench; a through trench penetrating the portion of the dielectric layer located at the bottom of the deep trench to expose the substrate; a first semiconductor material layer, the first semiconductor material layer being a P-type epitaxial layer, the first semiconductor material layer filling the through trench and being connected to the P-type lightly doped epitaxial layer; and a second semiconductor material layer filling the deep trench and being connected to the first semiconductor material layer, and the second semiconductor material layer at the top of the deep trench having a metal contact.

[0033] Correspondingly, the present invention also provides a method for manufacturing a deep trench isolation structure, comprising the following steps: providing a substrate; forming a deep trench, wherein the deep trench is located in the substrate; forming a dielectric layer, wherein the dielectric layer covers the sidewalls and bottom of the deep trench; removing a portion of the dielectric layer at the bottom of the deep trench to form a through trench exposing the substrate; forming a first semiconductor material layer in the through trench and a second semiconductor material layer in the deep trench through an epitaxial process, wherein the first semiconductor material layer is a P-type epitaxial layer; and forming a metal contact on the second semiconductor material layer at the top of the deep trench.

[0034] In the deep trench isolation structure and its manufacturing method provided by the present invention, after removing part of the dielectric layer at the bottom of the deep trench to form a through trench exposing the substrate, a first semiconductor material layer is formed in the through trench and a second semiconductor material layer is formed in the deep trench by an epitaxial process. The first semiconductor material layer is a P-type epitaxial layer, thereby reducing the difficulty of filling the deep trench and reducing the resistance of the electrical connection between the second semiconductor material layer in the deep trench and the P-type lightly doped epitaxial layer of the substrate, thereby improving the uniformity and stability of the electrical connection.

[0035] To make the objects, advantages, and features of the present invention more clearly apparent, the present invention is further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale. They are only used to conveniently and clearly assist in illustrating the purposes of the embodiments of the present invention. In addition, the structures shown in the drawings are often part of the actual structure. In particular, different drawings may need to illustrate different focuses and sometimes use different scales.

[0036] As used in the present invention, the singular forms "a", "an" and "the" include plural objects, unless the content clearly indicates otherwise. As used in the present invention, the term "or" is generally used in a sense including "and / or", unless the content clearly indicates otherwise. As used in the present invention, the term "several" is generally used in a sense including "at least one", unless the content clearly indicates otherwise. As used in the present invention, the term "at least two" is generally used in a sense including "two or more", unless the content clearly indicates otherwise. In addition, the terms "first", "second" and "third" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first", "second" and "third" may explicitly or implicitly include one or at least two of the features, unless the content clearly indicates otherwise.

[0037] Figure 6 FIG. 1 is a schematic diagram of a deep trench isolation structure provided by an embodiment of the present invention. Figure 6As shown, the deep trench isolation structure provided in this embodiment includes: substrate 100; A deep trench 10, wherein the deep trench 10 is located in the substrate 100; a dielectric layer 20 , the dielectric layer 20 covering the sidewalls and bottom of the deep trench 10 ; a through-groove 11 , wherein the through-groove 11 penetrates a portion of the dielectric layer 20 located at the bottom of the deep trench 10 to expose the substrate 100 ; a first semiconductor material layer 41 , wherein the first semiconductor material layer 41 is a P-type epitaxial layer, the first semiconductor material layer 41 fills the through-groove 11 and is connected to the substrate 100 ; and The second semiconductor material layer 42 fills the deep trench 10 and is connected to the first semiconductor material layer 41 . The second semiconductor material layer 42 at the top of the deep trench 10 has a metal contact.

[0038] In an embodiment of the present invention, the through-groove 11 penetrates a portion of the dielectric layer 20 located at the bottom of the deep groove 10, the first semiconductor material layer 41 filled in the through-groove 11 is connected to the substrate 100, the second semiconductor material layer 42 filled in the deep groove 10 is connected to the first semiconductor material layer 41, and the second semiconductor material layer 42 at the top of the deep groove 10 has a metal contact, and the first semiconductor material layer 41 is P-type epitaxial, thereby reducing the resistance of the electrical connection between the second semiconductor material layer 42 in the deep groove 10 and the substrate 100, and improving the uniformity and stability of the electrical connection.

[0039] In one embodiment of the present invention, the material of the substrate 100 includes one or more combinations of silicon, germanium, silicon germanium (SiGe), and silicon carbide (SiC). The material of the first semiconductor material layer 41 can be the same as that of the substrate 100, or it can be different from that of the substrate 100. The electrical conductivity of the first semiconductor material layer 41 is between that of the second semiconductor material layer 42 and that of the substrate 100.

[0040] In one embodiment of the present invention, the second semiconductor material layer 42 can be the same as the first semiconductor material layer 41, and both are P-type epitaxial layers. In another embodiment of the present invention, the second semiconductor material layer 42 includes a polycrystalline state and / or an amorphous state. For example, the material of the second semiconductor material layer 42 is polycrystalline silicon and / or amorphous silicon, and the polycrystalline state and / or the amorphous state are heavily P-type doped, and the doping concentration of P-type ions in the P-type heavy doping is greater than or equal to 5x10 19 / cm -3 , less than or equal to 2x10 22 / cm-3 In another embodiment of the present invention, a portion of the second semiconductor material layer 42 near the first semiconductor material layer 41 is epitaxial silicon, and a portion away from the first semiconductor material layer 41 is polycrystalline silicon and / or amorphous silicon. A gap may also be formed in the region near the top of the deep trench 10. The shape of the second semiconductor material layer 42 may be determined by the actual aspect ratio of the deep trench 10.

[0041] In one embodiment of the present invention, the material of the second semiconductor material layer 42 includes one or a combination of silicon, germanium, gallium arsenide and indium phosphide.

[0042] The dielectric layer 20 comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, and silicon carbonitride. In one embodiment of the present invention, the dielectric layer 20 is a stacked structure consisting of a silicon nitride layer and a silicon oxide layer. Figure 6 As shown, the dielectric layer 20 includes a silicon nitride layer 21 and a silicon oxide layer 22, wherein the silicon nitride layer 21 covers the sidewalls and bottom of the deep trench 10, and the silicon oxide layer 22 covers the silicon nitride layer 21. In another embodiment of the present invention, the dielectric layer 20 may be only a silicon oxide layer.

[0043] The deep trench isolation structure provided by the present invention is achieved by filling a first semiconductor material layer 41 (specifically a P-type epitaxial layer) in the through trench 11, wherein the first semiconductor material layer 41 is connected to the substrate 100, and filling a second semiconductor material layer 42 in the deep trench 10, wherein the second semiconductor material layer 42 is connected to the first semiconductor material layer 41, and the second semiconductor material layer 42 at the top of the deep trench 10 has a metal contact, thereby reducing the resistance of the electrical connection between the second semiconductor material layer 42 in the deep trench 10 and the substrate 100, thereby improving the uniformity and stability of the electrical connection.

[0044] Correspondingly, the present invention also provides a method for manufacturing a deep trench isolation structure, which is used to manufacture the deep trench isolation structure described above.

[0045] Figure 7 This is a flow chart of a method for manufacturing a deep trench isolation structure according to an embodiment of the present invention. Figure 7 As shown, the method for manufacturing the deep trench isolation structure provided in this embodiment includes the following steps: Step S1: providing a substrate; Step S2: forming a deep trench, wherein the deep trench is located in the substrate; Step S3: forming a dielectric layer, wherein the dielectric layer covers the sidewalls and bottom of the deep trench; Step S4: removing a portion of the dielectric layer at the bottom of the deep trench to form a through trench exposing the substrate; Step S5: forming a first semiconductor material layer in the through-groove and a second semiconductor material layer in the deep trench by an epitaxial process, wherein the first semiconductor material layer is a P-type epitaxial layer; and Step S6: forming a metal contact on the second semiconductor material layer at the top of the deep trench.

[0046] Next, we will combine Figure 6 and Figure 7 A method for manufacturing a deep trench isolation structure provided by an embodiment of the present invention is described in detail.

[0047] In step S1 , a substrate 100 is provided.

[0048] The material of the substrate 100 can be one or more combinations of silicon, germanium, silicon germanium (SiGe), and silicon carbide (SiC). Of course, the material of the substrate 100 can also be other materials known to those skilled in the art, and the present invention is not limited to this.

[0049] In step S2 , a deep trench 10 is formed. The deep trench 10 is located in the substrate 100 .

[0050] Illustratively, a patterned photoresist layer may be formed on the substrate 100 , and a portion of the substrate 100 may be etched using the patterned photoresist layer as a mask to form the deep trench 10 in the substrate 100 , and then the patterned photoresist layer may be removed.

[0051] In step S3 , a dielectric layer 20 is formed to cover the sidewalls and bottom of the deep trench 10 .

[0052] The dielectric layer 20 comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, and silicon carbonitride. In one embodiment of the present invention, the dielectric layer 20 is a stacked structure consisting of a silicon nitride layer and a silicon oxide layer. Figure 6 As shown, the dielectric layer 20 includes a silicon nitride layer 21 and a silicon oxide layer 22 . The silicon nitride layer 21 covers the sidewalls and the bottom of the deep trench 10 , and the silicon oxide layer 22 covers the silicon nitride layer 21 .

[0053] In step S4 , a portion of the dielectric layer 20 at the bottom of the deep trench 10 is removed to form a through trench 11 exposing the substrate 100 .

[0054] After forming the dielectric layer 20 , the dielectric layer 20 in a partial area at the bottom of the deep trench 10 is etched away to expose the substrate 100 , thereby forming the through trench 11 penetrating the dielectric layer 20 . The through trench 11 may be located in the middle area at the bottom of the deep trench 10 .

[0055] In step S5 , a first semiconductor material layer 41 is formed in the through trench 11 and a second semiconductor material layer 42 is formed in the deep trench 10 by an epitaxial process. The first semiconductor material layer 41 is a P-type epitaxial layer.

[0056] In this embodiment, an epitaxial process is used to form a first semiconductor material layer 41 in the through-groove 11. The first semiconductor material layer 41 fills the through-groove 11. Then, an epitaxial process is continued to form a second semiconductor material layer 42 in the deep trench 10. The first semiconductor material layer 41 is a P-type epitaxial layer.

[0057] When the aspect ratio of the deep trench 10 is relatively small, the second semiconductor material layer 42 may be entirely a P-type epitaxial layer. When the aspect ratio of the deep trench 10 is relatively large, a portion of the second semiconductor material layer 42 close to the first semiconductor material layer 41 may be a P-type epitaxial layer, while another portion away from the first semiconductor material layer 41 may be polycrystalline or / and amorphous, such as polycrystalline silicon or amorphous silicon. When the aspect ratio of the deep trench 10 continues to increase, voids may be formed in the deep trench 10. The morphology of the second semiconductor material layer 42 may be determined based on the actual aspect ratio of the deep trench 10.

[0058] In one embodiment of the present invention, the material of the first semiconductor material layer 42 is the same as that of the substrate 100. In another embodiment of the present invention, the material of the first semiconductor material layer 42 is different from that of the substrate 100. The electrical conductivity of the first semiconductor material layer 41 is between that of the second semiconductor material layer 42 and that of the substrate 100.

[0059] In one embodiment of the present invention, the material of the second semiconductor material layer 42 includes one or a combination of silicon, germanium, gallium arsenide and indium phosphide.

[0060] The present invention forms a first semiconductor material layer 41 in the through-groove 11 through an epitaxial process, and the first semiconductor material layer 41 is a P-type epitaxial layer. The second semiconductor material layer 42 is further formed in the deep groove 10 through the epitaxial process. Compared with the prior art, the difficulty of filling the deep groove 10 is reduced, and at the same time, the resistance of the electrical connection between the second semiconductor material layer 42 in the deep groove 10 and the P-type lightly doped epitaxial layer 102 of the substrate is reduced, thereby improving the uniformity and stability of the electrical connection.

[0061] In addition, the present invention adopts an epitaxial process to fill the through trench 11 and the deep trench 10 , and there is no need to purchase an additional machine to fill the deep trench 10 , which reduces process costs and improves process compatibility.

[0062] In step S6 , a metal contact is formed on the second semiconductor material layer 42 at the top of the deep trench 10 .

[0063] In this embodiment, illustratively, a silicon oxide layer 22 is first formed on the second semiconductor material layer 42, and the silicon oxide layer 22 covers the second semiconductor material layer 42. Then, a portion of the silicon oxide layer 22 is etched away to expose a portion of the second semiconductor material layer 42. Then, a metal contact is formed on the exposed second semiconductor material layer 42 to ground the second semiconductor material layer 42.

[0064] In the manufacturing method of the deep trench isolation structure provided by the present invention, after removing part of the dielectric layer 20 at the bottom of the deep trench 10 to form a through trench 11 exposing the substrate 100, a first semiconductor material layer 41 is formed in the through trench 11 and a second semiconductor material layer 42 is formed in the deep trench 10 through an epitaxial process. The first semiconductor material layer 41 is a P-type epitaxial layer, thereby reducing the difficulty of filling the deep trench 10 and reducing the resistance of the electrical connection between the second semiconductor material layer 42 in the deep trench 10 and the P-type lightly doped epitaxial layer 102 of the substrate, thereby improving the uniformity and stability of the electrical connection.

[0065] In addition, since the through trench 11 and the deep trench 10 are filled by the epitaxial process, there is no need to purchase an additional machine to fill the deep trench 10, which reduces the process cost and improves the process compatibility.

[0066] To sum up, in the deep trench isolation structure and its manufacturing method provided by the present invention, after removing part of the dielectric layer at the bottom of the deep trench to form a through trench exposing the substrate, a first semiconductor material layer is formed in the through trench and a second semiconductor material layer is formed in the deep trench through an epitaxial process. The first semiconductor material layer is a P-type epitaxial layer, which reduces the difficulty of filling the deep trench and at the same time reduces the resistance of the electrical connection between the second semiconductor material layer in the deep trench and the P-type lightly doped epitaxial layer of the substrate, thereby improving the uniformity and stability of the electrical connection.

[0067] In addition, since the through trench and the deep trench are filled by adopting the epitaxial process, there is no need to purchase an additional machine to fill the deep trench, which reduces the process cost and improves the process compatibility.

[0068] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A deep trench isolation structure, characterized in that: include: substrate; a deep groove located in the substrate; a dielectric layer covering the sidewalls and the bottom of the deep trench; A through groove, penetrating a portion of the dielectric layer located at the bottom of the deep groove, exposing the substrate; A first semiconductor material layer, wherein the first semiconductor material layer is a P-type epitaxial layer, the first semiconductor material layer fills the through groove and is connected to the substrate; as well as The second semiconductor material layer fills the deep trench and is connected to the first semiconductor material layer. The second semiconductor material layer at the top of the deep trench has a metal contact.

2. The deep trench isolation structure according to claim 1, characterized in that: The material of the first semiconductor material layer is the same as that of the substrate.

3. The deep trench isolation structure according to claim 1, characterized in that: The electrical conductivity of the first semiconductor material layer is between that of the second semiconductor material layer and the substrate.

4. The deep trench isolation structure according to claim 1, characterized in that: The second semiconductor material layer includes a polycrystalline state and / or an amorphous state.

5. The deep trench isolation structure according to claim 4, characterized in that: The polycrystalline state and / or amorphous state is / are heavily P-type doped.

6. The deep trench isolation structure according to claim 5, characterized in that: The doping concentration of P-type ions in the P-type heavy doping is greater than or equal to 5x10 19 cm -3 , less than or equal to 2x10 22 cm -3 .

7. The deep trench isolation structure according to claim 1, characterized in that: The material of the second semiconductor material layer includes one or more combinations of silicon, germanium, gallium arsenide and indium phosphide.

8. The deep trench isolation structure according to claim 1, wherein: The material of the dielectric layer includes one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, and silicon carbonitride.

9. The deep trench isolation structure according to claim 8, characterized in that: The dielectric layer is a stacked structure consisting of a silicon nitride layer and a silicon oxide layer.

10. A method for manufacturing a deep trench isolation structure, characterized in that: The following steps are involved: providing a substrate; forming a deep trench, wherein the deep trench is located in the substrate; forming a dielectric layer, wherein the dielectric layer covers the sidewalls and the bottom of the deep trench; removing a portion of the dielectric layer at the bottom of the deep trench to form a through trench exposing the substrate; forming a first semiconductor material layer in the through-groove and a second semiconductor material layer in the deep groove by an epitaxial process, wherein the first semiconductor material layer is a P-type epitaxial layer; as well as A metal contact is formed on the second semiconductor material layer at the top of the deep trench.

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