Deep groove isolation structure and manufacturing method thereof

Abstract

The invention provides a deep trench isolation structure and a manufacturing method thereof, and the structure comprises a substrate which comprises a P-type lightly-doped substrate and a P-type lightly-doped epitaxial layer; the N-type heavily doped layer is located on the P-type lightly doped epitaxial layer; the deep groove penetrates through the N-type heavily doped layer and extends into the substrate; the dielectric layer covers the side wall and the bottom of the deep groove; the through groove penetrates through the dielectric layer at the bottom of the deep groove and extends into the substrate, and the cross section size in the substrate is greater than or equal to that in the dielectric layer; the first semiconductor material layer is a P-type epitaxial layer, fills the through groove and is connected with the substrate; and the second semiconductor material layer fills the deep groove and is connected with the first semiconductor material layer, and the second semiconductor layer at the top of the deep groove has metal contact. According to the invention, the filling difficulty and process cost of the deep groove are reduced, the resistance of electrical connection between the second semiconductor material layer in the deep groove and the substrate is reduced, and the uniformity and stability of electrical connection are improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a deep trench isolation structure and a manufacturing method thereof. Background Art

[0002] Common device isolation technologies include: PN junction isolation, LOCOS isolation, trench isolation and full dielectric isolation (SOI). As the requirements for voltage resistance of high-voltage devices continue to increase, deep trench isolation (DTI) has gradually become the mainstream isolation process. Compared with PN junction isolation, DTI has greatly improved the isolation effect, reduced the off-current, reduced the chip size, increased the density of IC devices, and improved the reliability of device operation. For example, in adjacent devices at the same distance, the alph value (amplification factor) of the parasitic NPN transistor can be reduced by 1 / 10 after using DTI, thereby greatly reducing the possibility of parasitic transistor misoperation.

[0003] However, in order to ensure better isolation and less leakage, the DTI trench is getting deeper and deeper. As the trench gets deeper, the manufacturing process of the deep trench isolation structure will encounter process difficulties, mainly in the etching, cleaning and filling of the deep trench.

[0004] How to overcome process difficulties to ensure the isolation effect of the deep trench isolation structure is a technical problem that technical personnel in this field need to solve urgently. Summary of the invention

[0005] The object of the present invention is to provide a deep trench isolation structure and a manufacturing method thereof, which effectively reduces the difficulty of filling the deep trench isolation structure and improves the uniformity and stability of the electrical connection between the deep trench isolation structure and the bottom substrate.

[0006] In order to solve the above technical problems, according to a first aspect of the present invention, a deep trench isolation structure is provided, comprising: A substrate, comprising a P-type lightly doped substrate and a P-type lightly doped epitaxial layer located on the P-type lightly doped substrate; An N-type heavily doped layer, located on the P-type lightly doped epitaxial layer; A deep trench, penetrating the N-type heavily doped layer and extending into the substrate; a dielectric layer covering the sidewalls and the bottom of the deep trench; A through groove, penetrating the dielectric layer in a partial area at the bottom of the deep groove and extending into the substrate, wherein the cross-sectional dimension of the through groove in the substrate is greater than or equal to the cross-sectional dimension of the through groove in the dielectric layer; A first semiconductor material layer, wherein the first semiconductor material layer is a P-type epitaxial layer, the first semiconductor material layer fills the through groove and is connected to the substrate; and The second semiconductor material layer fills the deep trench and is connected to the first semiconductor material layer. The second semiconductor material layer at the top of the deep trench has a metal contact.

[0007] Optionally, when the deep trench penetrates the N-type heavily doped layer and extends into the P-type lightly doped epitaxial layer, the material of the first semiconductor material layer is the same as that of the P-type lightly doped epitaxial layer.

[0008] Optionally, the electrical conductivity of the first semiconductor material layer is between that of the second semiconductor material layer and the P-type lightly doped epitaxial layer.

[0009] Optionally, when the deep trench penetrates the N-type heavily doped layer and the P-type lightly doped epitaxial layer and extends into the P-type lightly doped substrate, the material of the first semiconductor material layer is the same as that of the P-type lightly doped substrate.

[0010] Optionally, the electrical conductivity of the first semiconductor material layer is between that of the second semiconductor material layer and the P-type lightly doped substrate.

[0011] Optionally, the second semiconductor material layer contains polycrystalline and / or amorphous states.

[0012] Optionally, the polycrystalline state and / or the amorphous state is heavily P-type doped, and the doping concentration is greater than or equal to 5×10 19 cm -3 , less than or equal to 2x10 22 cm -3 .

[0013] Optionally, the material of the second semiconductor material layer includes one or a combination of silicon, germanium, gallium arsenide and indium phosphide.

[0014] Optionally, the doping concentration of the P-type lightly doped epitaxial layer is greater than the doping concentration of the P-type lightly doped substrate.

[0015] Optionally, a cross-sectional dimension of the through-groove in the substrate is greater than a cross-sectional dimension of the through-groove in the dielectric layer.

[0016] In order to solve the above technical problem, according to a second aspect of the present invention, a method for manufacturing a deep trench isolation structure is provided, comprising the following steps: Providing a substrate, the substrate comprising a P-type lightly doped substrate and a P-type lightly doped epitaxial layer located on the P-type lightly doped substrate; forming an N-type heavily doped layer on the P-type lightly doped epitaxial layer; forming a deep trench, wherein the deep trench penetrates the N-type heavily doped layer and extends into the substrate; forming a dielectric layer, wherein the dielectric layer covers the sidewalls and the bottom of the deep trench; Removing the dielectric layer from a portion of the bottom of the deep trench, and wet-cleaning the exposed substrate to form a through-groove, wherein the cross-sectional size of the through-groove in the substrate is greater than or equal to the cross-sectional size of the through-groove in the dielectric layer; forming a first semiconductor material layer in the through-groove and a second semiconductor material layer in the deep groove by an epitaxial process, wherein the first semiconductor material layer is a P-type epitaxial layer; and A metal contact is formed on the second semiconductor material layer at the top of the deep trench.

[0017] Compared with the prior art, in the deep trench isolation structure and the manufacturing method thereof provided by the present invention, after the dielectric layer in a partial area of ​​the bottom of the deep trench is removed to form a through trench exposed and extending into the substrate, a first semiconductor material layer is formed in the through trench and a second semiconductor material layer is formed in the deep trench through an epitaxial process, and the first semiconductor material layer is a P-type epitaxial layer, thereby reducing the difficulty of filling the deep trench, and at the same time reducing the resistance of the electrical connection between the second semiconductor material layer in the deep trench and the substrate, thereby improving the uniformity and stability of the electrical connection.

[0018] In addition, since the through-grooves and the deep grooves are filled with an epitaxial process, there is no need to purchase additional machines to fill the deep grooves, which reduces process costs and improves process compatibility.

[0019] At the same time, the through groove penetrates the dielectric layer and extends into the substrate, so that the contact area between the first semiconductor material layer and the substrate becomes larger, thereby reducing the contact resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a schematic diagram of the first deep trench isolation structure.

[0021] Figure 2 is a schematic diagram of the second deep trench isolation structure.

[0022] Figure 3 It is a schematic diagram of the third deep trench isolation structure.

[0023] Figure 4 Schematic diagram of the fourth deep trench isolation structure.

[0024] Figure 5 Schematic diagram of the fifth deep trench isolation structure.

[0025] Figure 6 FIG. 1 is a schematic diagram of a deep trench isolation structure provided in a first embodiment of the present invention.

[0026] Figure 7 FIG. 4 is a schematic diagram of a deep trench isolation structure provided in a second embodiment of the present invention.

[0027] Figure 8 FIG. 4 is a schematic diagram of a deep trench isolation structure provided in a third embodiment of the present invention.

[0028] Fig. 9 FIG. 4 is a schematic diagram of a deep trench isolation structure provided in a fourth embodiment of the present invention.

[0029] Fig.10 Detailed description of the invention The figure is a flow chart of a method for manufacturing a deep trench isolation structure provided by an embodiment of the present invention.

[0030] Description of reference numerals: 10-deep trench; 11-through trench; 20-dielectric layer; 21-silicon nitride layer; 22-silicon oxide layer; 30-isolation layer; 40-semiconductor material layer; 41-first semiconductor material layer; 42-second semiconductor material layer; 100-substrate; 101-P-type lightly doped substrate; 102-P-type lightly doped epitaxial layer; 200-N-type heavily doped layer; 201-N + Heavily doped layer; 202-N - Heavily doped layer. DETAILED DESCRIPTION

[0031] Figures 1 to 5 Schematic diagrams of several deep trench isolation structures are shown.

[0032] Please refer to Figure 1 As shown, a dielectric layer 20 is formed on the sidewall and bottom of the deep trench 10, and an isolation layer 30 is filled in the deep trench 10, wherein the material of the dielectric layer 20 includes silicon oxide, and the material of the isolation layer 30 includes silicon oxide, that is, the deep trench 10 is only filled with silicon oxide. Figure 1 The internal stress of the deep trench isolation structure shown is too large (over stress), which causes the wafer to deform or even warp, which not only affects the device performance, but may even cause the wafer to be loosely adsorbed and cause breakage.

[0033] Please refer to Figure 2 As shown, a dielectric layer 20 is formed on the sidewall and bottom of the deep trench 10, a semiconductor material layer 40 is filled in the deep trench 10, and a dielectric layer 20 is also formed on the semiconductor material layer 40, that is, on the top of the deep trench 10, that is, the dielectric layer 20 surrounds the semiconductor material layer 40. In this embodiment, the material of the dielectric layer 20 is silicon oxide, and the material of the semiconductor material layer 40 is polysilicon. Figure 2 The deep trench isolation structure shown in the figure ensures the flatness of the wafer because polysilicon grows synchronously on the front and back sides of the wafer, and the device uniformity corresponding to the structure is also relatively good.

[0034] Please refer to Figure 3 As shown, a dielectric layer 20 is formed on the sidewall and bottom of the deep trench 10, a semiconductor material layer 40 is filled in the deep trench 10, a dielectric layer 20 is also formed on the top of the semiconductor material layer 40, the dielectric layer 20 surrounds the semiconductor material layer 40, and a through groove is formed at the bottom of the deep trench 10, the semiconductor material layer 40 is in contact with the substrate at the bottom, and a portion of the semiconductor material layer 40 is also exposed at the top of the deep trench 10, and the exposed semiconductor material layer 40 has a metal contact, that is, the semiconductor material layer 40 at the top is grounded. In this embodiment, the material of the dielectric layer 20 is silicon oxide, and the semiconductor material layer 40 is P + Polysilicon (P + poly-Si). Figure 3 The manufacturing process of the deep trench isolation structure shown in FIG. 1 is complex, but the isolation performance is better and the uniformity of the structure is better. However, since P is required to be filled in the deep trench 10, + Polysilicon, additional filling P is required + Polysilicon machine.

[0035] Please refer to Figure 4 As shown, a dielectric layer 20 is formed on the sidewall and bottom of the deep trench 10, and the dielectric layer 20 includes a silicon nitride layer 21 covering the sidewall and bottom of the deep trench 10 and a silicon oxide layer 22 covering the silicon nitride layer 21. A semiconductor material layer 40 is filled in the deep trench 10, and a silicon oxide layer 22 is also formed on the top of the semiconductor material layer 40. The silicon oxide layer 22 surrounds the semiconductor material layer 40. In this embodiment, the semiconductor material layer 40 is polysilicon. Figure 4 The manufacturing process of the deep trench isolation structure is complex and the manufacturing cost is relatively high.

[0036] Please refer to Figure 5 As shown, a dielectric layer 20 is formed on the sidewall and bottom of the deep trench 10, and the dielectric layer 20 includes a silicon nitride layer 21 covering the sidewall and bottom of the deep trench 10 and a silicon oxide layer 22 covering the silicon nitride layer 21. A semiconductor material layer 40 is filled in the deep trench 10, and a silicon oxide layer 22 is also formed on the top of the semiconductor material layer 40, and the silicon oxide layer 22 surrounds the semiconductor material layer 40. A through groove is formed at the bottom of the deep trench 10, and the semiconductor material layer 40 is in contact with the substrate at the bottom, and a portion of the semiconductor material layer 40 is also exposed at the top of the deep trench 10, and the exposed semiconductor material layer 40 has a metal contact, that is, the top of the semiconductor material layer 40 is grounded. In this embodiment, the material of the semiconductor material layer 40 is P + Polysilicon. Figure 5The manufacturing process of the deep trench isolation structure shown in FIG. 1 is complex, but the isolation performance is better and the uniformity of the structure is better. However, since P is required to be filled in the deep trench 10, + Polysilicon, additional filling P is required + Polysilicon machine.

[0037] In view of the problems existing in the above-mentioned various deep trench isolation structures, the present invention provides a deep trench isolation structure, comprising: a substrate, comprising a P-type lightly doped substrate and a P-type lightly doped epitaxial layer located on the P-type lightly doped substrate; an N-type heavily doped layer, located on the P-type lightly doped epitaxial layer; a deep trench, penetrating the N-type heavily doped layer and extending into the substrate; a dielectric layer, covering the sidewalls and the bottom of the deep trench; a through-groove, penetrating the dielectric layer at a partial area at the bottom of the deep trench and extending into the substrate, and the cross-sectional size of the through-groove located in the substrate is greater than or equal to the cross-sectional size of the through-groove located in the dielectric layer; a first semiconductor material layer, the first semiconductor material layer is a P-type epitaxial layer, the first semiconductor material layer fills the through-groove and is connected to the substrate; and a second semiconductor material layer, filling the deep trench, being connected to the first semiconductor material layer, and the second semiconductor material layer at the top of the deep trench has a metal contact.

[0038] Correspondingly, the present invention also provides a method for manufacturing a deep trench isolation structure, comprising the following steps: providing a substrate, the substrate comprising a P-type lightly doped substrate and a P-type lightly doped epitaxial layer located on the P-type lightly doped substrate; forming the N-type heavily doped layer on the P-type lightly doped epitaxial layer; forming a deep trench, the deep trench penetrating the N-type heavily doped layer and extending into the substrate; forming a dielectric layer, the dielectric layer covering the sidewalls and bottom of the deep trench; removing the dielectric layer from a partial area of ​​the bottom of the deep trench, and wet cleaning the exposed substrate to form a through trench, the cross-sectional size of the through trench located in the substrate being greater than or equal to the cross-sectional size of the through trench located in the dielectric layer; forming a first semiconductor material layer in the through trench and a second semiconductor material layer in the deep trench through an epitaxial process, the first semiconductor material layer being a P-type epitaxial layer; and forming a metal contact on the second semiconductor material layer at the top of the deep trench.

[0039] In the deep trench isolation structure and the manufacturing method thereof provided by the present invention, after the dielectric layer in a partial area of ​​the bottom of the deep trench is removed to form a through trench exposed and extending into the substrate, a first semiconductor material layer is formed in the through trench and a second semiconductor material layer is formed in the deep trench by an epitaxial process, and the first semiconductor material layer is a P-type epitaxial layer, thereby reducing the difficulty of filling the deep trench and reducing the resistance of the electrical connection between the second semiconductor material layer in the deep trench and the substrate, thereby improving the uniformity and stability of the electrical connection.

[0040] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0041] As used in the present invention, the singular forms "one", "an" and "the" include plural objects, unless the content clearly indicates otherwise. As used in the present invention, the term "or" is generally used in a sense that includes "and / or", unless the content clearly indicates otherwise. As used in the present invention, the term "several" is generally used in a sense that includes "at least one", unless the content clearly indicates otherwise. As used in the present invention, the term "at least two" is generally used in a sense that includes "two or more", unless the content clearly indicates otherwise. In addition, the terms "first", "second", and "third" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features, unless the content clearly indicates otherwise.

[0042] The deep trench isolation structure provided by the embodiment of the present invention includes: A substrate, comprising a P-type lightly doped substrate and a P-type lightly doped epitaxial layer located on the P-type lightly doped substrate; An N-type heavily doped layer, located on the P-type lightly doped epitaxial layer; A deep trench, penetrating the N-type heavily doped layer and extending into the substrate; a dielectric layer covering the sidewalls and the bottom of the deep trench; A through groove, penetrating the dielectric layer in a partial area at the bottom of the deep groove and extending into the substrate, wherein the cross-sectional dimension of the through groove in the substrate is greater than or equal to the cross-sectional dimension of the through groove in the dielectric layer; A first semiconductor material layer, wherein the first semiconductor material layer is a P-type epitaxial layer, the first semiconductor material layer fills the through groove and is connected to the substrate; and The second semiconductor material layer fills the deep trench and is connected to the first semiconductor material layer. The second semiconductor material layer at the top of the deep trench has a metal contact.

[0043] The deep trench penetrates the N-type heavily doped layer and may extend into the P-type lightly doped epitaxial layer, or penetrates the P-type lightly doped epitaxial layer and extends into the P-type lightly doped substrate.

[0044] The following describes four embodiments as examples.

[0045] Figure 6 Schematic diagram of a deep trench isolation structure provided by the first embodiment of the present invention. Figure 6 As shown, the deep trench isolation structure provided in this embodiment includes: A substrate 100, wherein the substrate 100 includes a P-type lightly doped substrate 101 and a P-type lightly doped epitaxial layer 102 located on the P-type lightly doped substrate 101; An N-type heavily doped layer 200 , wherein the N-type heavily doped layer 200 is located on the P-type lightly doped epitaxial layer 102 ; A deep trench 10, wherein the deep trench 10 penetrates the N-type heavily doped layer 200 and extends into the P-type lightly doped epitaxial layer 102; a dielectric layer 20, wherein the dielectric layer 20 covers the sidewalls and the bottom of the deep trench 10; A through groove 11, wherein the through groove 11 penetrates the dielectric layer 20 in a partial area at the bottom of the deep groove 10 and extends into the P-type lightly doped epitaxial layer 102, and the cross-sectional size of the through groove 11 in the P-type lightly doped epitaxial layer 102 is greater than or equal to the cross-sectional size of the through groove 11 in the dielectric layer 20; a first semiconductor material layer 41 , wherein the first semiconductor material layer 41 is a P-type epitaxial layer, the first semiconductor material layer 41 fills the through-groove 11 , and is connected to the P-type lightly doped epitaxial layer 102 ; and The second semiconductor material layer 42 fills the deep trench 10 and is connected to the first semiconductor material layer 41 , and the second semiconductor material layer 42 at the top of the deep trench 10 has a metal contact.

[0046] In an embodiment of the present invention, the through groove 11 penetrates the dielectric layer 20 in a partial area at the bottom of the deep groove 10 and extends into the P-type lightly doped epitaxial layer 102, the first semiconductor material layer 41 filled in the through groove 11 is connected to the P-type lightly doped epitaxial layer 102, the second semiconductor material layer 42 filled in the deep groove 10 is connected to the first semiconductor material layer 41, and the second semiconductor material layer 42 at the top of the deep groove 10 has a metal contact, and the first semiconductor material layer 41 is P-type epitaxial, thereby reducing the resistance of the electrical connection between the second semiconductor material layer 42 in the deep groove 10 and the P-type lightly doped epitaxial layer 102, and improving the uniformity and stability of the electrical connection.

[0047] In one embodiment of the present invention, the doping concentration of the P-type lightly doped epitaxial layer 102 is greater than the doping concentration of the P-type lightly doped substrate 101. The doping concentration of the P-type ions in the P-type lightly doped epitaxial layer 102 is greater than or equal to 1×10 15 cm -3 , less than or equal to 8x10 19 cm -3 . The material of the P-type lightly doped substrate 101 includes one or more combinations of silicon, germanium, silicon germanium (SiGe) and silicon carbide (SiC). The material of the P-type lightly doped epitaxial layer 102 includes one or more combinations of silicon, germanium, silicon germanium (SiGe) and silicon carbide (SiC). Of course, the P-type lightly doped substrate 101 and the P-type lightly doped epitaxial layer 102 may also be other materials known to those skilled in the art. The material of the P-type lightly doped substrate 101 may be the same as the material of the P-type lightly doped epitaxial layer 102, or may be different from the material of the P-type lightly doped epitaxial layer 102.

[0048] In one embodiment of the present invention, the P-type lightly doped substrate 101 is P - The P-type lightly doped epitaxial layer 102 is P - The lightly doped epitaxial layer, the first semiconductor material layer 41 is P + epitaxial layer, the second semiconductor material layer 42 is P + The N-type heavily doped layer 200 may include N-type lightly doped epitaxial layer 102 and N-type doped epitaxial layer 102. + The heavily doped layer 201 and N - Heavily doped layer 202 .

[0049] In an embodiment of the present invention, the distance between the bottom surface of the deep trench 10 and the upper surface of the P-type lightly doped epitaxial layer 102 is greater than or equal to 1 μm and less than or equal to 50 μm, but is certainly not limited thereto.

[0050] The material of the first semiconductor material layer 41 may be the same as that of the P-type lightly doped epitaxial layer 102. Of course, in another embodiment of the present invention, the material of the first semiconductor material layer 41 may also be different from that of the P-type lightly doped epitaxial layer 102. The conductivity of the first semiconductor material layer 41 is between that of the second semiconductor material layer 42 and the P-type lightly doped epitaxial layer 102.

[0051] In one embodiment of the present invention, the second semiconductor material layer 42 may be the same as the first semiconductor material layer 41, and both are P-type epitaxial layers. In another embodiment of the present invention, the second semiconductor material layer 42 includes polycrystalline and / or amorphous states. For example, the material of the second semiconductor material layer 42 is polycrystalline silicon and / or amorphous silicon, and the polycrystalline and / or amorphous states are P-type heavily doped, and the doping concentration of P-type ions in the P-type heavily doped is greater than or equal to 5x10 19 cm -3 , less than or equal to 2x10 22 cm -3 In another embodiment of the present invention, a portion of the second semiconductor material layer 42 close to the first semiconductor material layer 41 is epitaxial silicon, and a portion away from the first semiconductor material layer 41 is polycrystalline silicon or / and amorphous silicon, and a gap may be formed in the region close to the top of the deep trench 10. The shape of the second semiconductor material layer 42 may be determined by the actual aspect ratio of the deep trench 10.

[0052] In one embodiment of the present invention, the material of the second semiconductor material layer 42 includes one or a combination of silicon, germanium, gallium arsenide and indium phosphide.

[0053] The material of the dielectric layer 20 includes one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, and silicon carbonitride. Figure 6 As shown, the dielectric 20 includes a silicon nitride layer 21 and a silicon oxide layer 22 , wherein the silicon nitride layer 21 covers the sidewall and the bottom of the deep trench 10 , and the silicon oxide layer 22 covers the silicon nitride layer 21 .

[0054] The deep trench isolation structure provided by the present invention is achieved by filling a first semiconductor material layer 41 (specifically a P-type epitaxial layer) in the through trench 11, wherein the first semiconductor material layer 41 is connected to the P-type lightly doped epitaxial layer 102, and filling a second semiconductor material layer 42 in the deep trench 10, wherein the second semiconductor material layer 42 is connected to the first semiconductor material layer 41, and the second semiconductor material layer 42 at the top of the deep trench 10 has a metal contact, thereby reducing the resistance of the electrical connection between the second semiconductor material layer 42 in the deep trench 10 and the P-type lightly doped epitaxial layer 102 of the substrate, thereby improving the uniformity and stability of the electrical connection.

[0055] In one embodiment of the present invention, the through groove 11 penetrates the dielectric layer 20 in a partial area of ​​the bottom of the deep groove 10 and extends into the P-type lightly doped epitaxial layer 102, so that the contact area between the first semiconductor material layer 41 and the P-type lightly doped epitaxial layer 102 becomes larger, thereby reducing the contact resistance. The through groove 11 can be located at the center of the bottom of the deep groove 10.

[0056] In one embodiment of the present invention, the cross-sectional dimension of the through groove 11 located in the P-type lightly doped epitaxial layer 102 is greater than the cross-sectional dimension of the through groove 11 located in the dielectric layer 20, that is, the cross-sectional dimension of the through groove 11 is an inverted T-shape, so as to further increase the contact area between the first semiconductor material layer 41 and the P-type lightly doped epitaxial layer 102 and further reduce the contact resistance. In another embodiment of the present invention, the cross-sectional dimension of the through groove 11 located in the P-type lightly doped epitaxial layer 102 is equal to the cross-sectional dimension of the through groove 11 located in the dielectric layer 20, that is, the cross-sectional dimension of the through groove 11 is a rectangle. Of course, the cross-sectional dimension of the through groove 11 is not limited thereto.

[0057] Figure 7 Schematic diagram of a deep trench isolation structure provided by a second embodiment of the present invention. Figure 7 As shown, this embodiment and Figure 6 The difference of the illustrated embodiment is that the dielectric layer 20 is a single-layer structure, such as a silicon oxide layer.

[0058] The through groove 11 penetrates the dielectric layer 20 and extends into the P-type lightly doped epitaxial layer 102, so that the contact area between the first semiconductor material layer 41 and the P-type lightly doped epitaxial layer 102 becomes larger, thereby reducing the contact resistance. The through groove 11 can be located at the center of the bottom of the deep groove 10.

[0059] In one embodiment of the present invention, the P-type lightly doped epitaxial layer 102 at the bottom of the deep trench 10 is P + The bottom of the through groove 11 is located at P + The P-type lightly doped epitaxial layer 102 of the epitaxial layer.

[0060] In one embodiment of the present invention, please refer to Figure 7 As shown, the cross-sectional dimensions of the through grooves 11 in the horizontal direction are equal. In another embodiment of the present invention, the cross-sectional dimensions of the through grooves 11 located in the P-type lightly doped epitaxial layer 102 may be greater than the cross-sectional dimensions of the through grooves 11 located in the dielectric layer 20, that is, the cross-sectional dimensions of the through grooves 11 are inverted T-shaped, so as to further increase the contact area between the first semiconductor material layer 41 and the P-type lightly doped epitaxial layer 102, and further reduce the contact resistance. Of course, the cross-sectional dimensions of the through grooves 11 are not limited thereto.

[0061] Figure 8 Schematic diagram of a deep trench isolation structure provided by the third embodiment of the present invention. Figure 8 As shown, this embodiment and Figure 6 The difference of the illustrated embodiment is that the deep trench 10 penetrates the N-type heavily doped layer 200 and the P-type lightly doped epitaxial layer 102 and extends into the P-type lightly doped substrate 101 .

[0062] In one embodiment of the present invention, the doping concentration of the P-type lightly doped epitaxial layer 102 is greater than the doping concentration of the P-type lightly doped substrate 101. The material of the P-type lightly doped substrate 101 includes one or more combinations of silicon, germanium, silicon germanium (SiGe) and silicon carbide (SiC). The material of the P-type lightly doped epitaxial layer 102 includes one or more combinations of silicon, germanium, silicon germanium and silicon carbide. Of course, the P-type lightly doped substrate 101 and the P-type lightly doped epitaxial layer 102 may also be other materials known to those skilled in the art. The material of the P-type lightly doped substrate 101 may be the same as the material of the P-type lightly doped epitaxial layer 102, or may be different from the material of the P-type lightly doped epitaxial layer 102.

[0063] In one embodiment of the present invention, the material of the first semiconductor material layer 41 may be the same as the material of the P-type lightly doped substrate 101. Of course, in another embodiment of the present invention, the material of the first semiconductor material layer 41 may also be different from the material of the P-type lightly doped substrate 101. The conductivity of the first semiconductor material layer 41 is between that of the second semiconductor material layer 42 and the P-type lightly doped substrate 101.

[0064] In one embodiment of the present invention, Figure 8 In the embodiment, the bottom of the deep trench 10 is located in the P-type lightly doped substrate 101, and the upper surface of the dielectric layer 20 formed at the bottom of the deep trench 10 is higher than the upper surface of the P-type lightly doped substrate 101. In another embodiment of the present invention, the bottom of the deep trench 10 is located in the P-type lightly doped substrate 101, and the upper surface of the dielectric layer 20 formed at the bottom of the deep trench 10 is lower than the upper surface of the P-type lightly doped substrate 101. The present invention is not limited to this.

[0065] In one embodiment of the present invention, the material of the second semiconductor material layer 42 includes one or a combination of silicon, germanium, gallium arsenide and indium phosphide, but is not limited thereto.

[0066] In one embodiment of the present invention, the second semiconductor material layer 42 may be the same as the first semiconductor material layer 41, and both are P-type epitaxial layers. In another embodiment of the present invention, the second semiconductor material layer 42 includes polycrystalline and / or amorphous states. For example, the material of the second semiconductor material layer 42 is polycrystalline silicon and / or amorphous silicon, and the polycrystalline and / or amorphous states are P-type heavily doped, and the doping concentration of P-type ions in the P-type heavily doped is greater than or equal to 5x10 19 cm -3 , less than or equal to 2x10 22 cm -3In another embodiment of the present invention, a portion of the second semiconductor material layer 42 close to the first semiconductor material layer 41 is epitaxial silicon, and a portion away from the first semiconductor material layer 41 is polycrystalline silicon or / and amorphous silicon, and a gap may be formed in the region close to the top of the deep trench 10. The shape of the second semiconductor material layer 42 may be determined by the actual aspect ratio of the deep trench 10.

[0067] In an embodiment of the present invention, the through groove 11 penetrates the dielectric layer 20 located in a partial area at the bottom of the deep groove 10, the first semiconductor material layer 41 filled in the through groove 11 is connected to the P-type lightly doped substrate 101, the second semiconductor material layer 42 filled in the deep groove 10 is connected to the first semiconductor material layer 41, and the second semiconductor material layer 42 at the top of the deep groove 10 has a metal contact, and the first semiconductor material layer 41 is P-type epitaxial, thereby reducing the resistance of the electrical connection between the second semiconductor material layer 42 in the deep groove 10 and the P-type lightly doped substrate 101, and improving the uniformity and stability of the electrical connection.

[0068] In one embodiment of the present invention, the through groove 11 penetrates the dielectric layer 20 in a partial area of ​​the bottom of the deep groove 10 and extends into the P-type lightly doped substrate 101, so that the contact area between the first semiconductor material layer 41 and the P-type lightly doped substrate 101 becomes larger, thereby reducing the contact resistance. The through groove 11 can be located at the center of the bottom of the deep groove 10.

[0069] In one embodiment of the present invention, the cross-sectional dimension of the through-groove 11 located in the P-type lightly doped substrate 101 is greater than the cross-sectional dimension of the through-groove 11 located in the dielectric layer 20, that is, the cross-sectional dimension of the through-groove 11 is an inverted T-shape, so as to further increase the contact area between the first semiconductor material layer 41 and the P-type lightly doped substrate 101 and further reduce the contact resistance. In another embodiment of the present invention, the cross-sectional dimension of the through-groove 11 located in the P-type lightly doped substrate 101 is equal to the cross-sectional dimension of the through-groove 11 located in the dielectric layer 20, that is, the cross-sectional dimension of the through-groove 11 is a rectangle. Of course, the cross-sectional dimension of the through-groove 11 is not limited thereto.

[0070] Fig. 9 FIG. 4 is a schematic diagram of a deep trench isolation structure provided by a fourth embodiment of the present invention. Fig. 9 As shown, this embodiment and Figure 7 The difference of the illustrated embodiment is that the deep trench 10 penetrates the N-type heavily doped layer 200 and the P-type lightly doped epitaxial layer 102 and extends into the P-type lightly doped substrate 101 .

[0071] The through groove 11 penetrates the dielectric layer 20 and the P-type lightly doped epitaxial layer 102 and extends into the P-type lightly doped substrate 101, so that the contact area between the first semiconductor material layer 41 and the P-type lightly doped epitaxial layer 102 becomes larger, thereby reducing the contact resistance. The through groove 11 can be located at the center of the bottom of the deep groove 10.

[0072] In one embodiment of the present invention, the P-type lightly doped substrate 101 at the bottom of the deep trench 10 is P + doping layer, the bottom of the through groove 11 is located at P + The doping layer is in the P-type lightly doped substrate 101 .

[0073] In one embodiment of the present invention, please refer to Fig. 9 As shown, the cross-sectional dimensions of the through grooves 11 in the horizontal direction are equal. In another embodiment of the present invention, the cross-sectional dimensions of the through grooves 11 located in the P-type lightly doped substrate 101 may be greater than the cross-sectional dimensions of the through grooves 11 located in the dielectric layer 20, that is, the cross-sectional dimensions of the through grooves 11 are inverted T-shaped, so as to further increase the contact area between the first semiconductor material layer 41 and the P-type lightly doped substrate 101, and further reduce the contact resistance. Of course, the cross-sectional dimensions of the through grooves 11 are not limited thereto.

[0074] Correspondingly, the present invention also provides a method for manufacturing a deep trench isolation structure, which is used to manufacture the deep trench isolation structure as described above.

[0075] Fig.10 1 is a flow chart of a method for manufacturing a deep trench isolation structure according to an embodiment of the present invention. Figure 6 and Figure 8 The deep trench isolation structure shown in the figure is used as an example. Figure 8 As shown, the method for manufacturing the deep trench isolation structure provided in this embodiment includes the following steps: Step S1: providing a substrate, wherein the substrate comprises a P-type lightly doped substrate and a P-type lightly doped epitaxial layer located on the P-type lightly doped substrate; Step S2: forming the N-type heavily doped layer on the P-type lightly doped epitaxial layer; Step S3: forming a deep trench, wherein the deep trench penetrates the N-type heavily doped layer and extends into the substrate; Step S4: forming a dielectric layer, wherein the dielectric layer covers the sidewalls and the bottom of the deep trench; Step S5: removing the dielectric layer in a partial area at the bottom of the deep trench, and wet-cleaning the exposed substrate to form a through-groove, wherein the cross-sectional size of the through-groove in the substrate is greater than or equal to the cross-sectional size of the through-groove in the dielectric layer; Step S6: forming a first semiconductor material layer in the through-groove and a second semiconductor material layer in the deep groove by an epitaxial process, wherein the first semiconductor material layer is a P-type epitaxial layer; and Step S7: forming a metal contact on the second semiconductor material layer at the top of the deep trench.

[0076] Next, we will combine Figure 6 , Figure 8 and Fig.10 The method for manufacturing the deep trench isolation structure provided by the embodiment of the present invention is described in detail.

[0077] In step S1 , a substrate 100 is provided. The substrate 100 includes a P-type lightly doped substrate 101 and a P-type lightly doped epitaxial layer 102 located on the P-type lightly doped substrate 101 .

[0078] The material of the P-type lightly doped substrate 101 may be one or more of silicon, germanium, silicon germanium, and silicon carbide, and the material of the P-type lightly doped epitaxial layer 102 may also be one or more of silicon, germanium, silicon germanium, and silicon carbide. The material of the P-type lightly doped substrate 101 may be the same as the material of the P-type lightly doped epitaxial layer 102, or may be different from the material of the P-type lightly doped epitaxial layer 102.

[0079] In this embodiment, the doping concentration of the P-type ions in the P-type lightly doped epitaxial layer 102 is greater than or equal to 1×10 15 cm -3 , less than or equal to 8x10 19 cm -3 , but is not limited thereto. The doping concentration of the P-type lightly doped epitaxial layer 102 is greater than the doping concentration of the P-type lightly doped substrate 101. - The lightly doped epitaxial layer, the P-type lightly doped substrate 101 is also P - Lightly doped layer.

[0080] In step S2 , the N-type heavily doped layer 200 is formed on the P-type lightly doped epitaxial layer 102 .

[0081] In this embodiment, a semiconductor device (not shown) is formed on the substrate 100. The semiconductor device includes an N-type heavily doped layer 200. The N-type heavily doped layer 200 is formed on the P-type lightly doped epitaxial layer 102. The deep trench isolation structure is used to isolate adjacent semiconductor devices.

[0082] The N-type heavily doped layer 200 may include an N-type lightly doped epitaxial layer 102 formed on the P-type lightly doped epitaxial layer 102. + The heavily doped layer 201 is formed on the N +The N on the heavily doped layer 201 - Heavily doped layer 202 .

[0083] In step S3 , a deep trench 10 is formed. The deep trench 10 penetrates the N-type heavily doped layer 200 and extends into the substrate 100 .

[0084] refer to Figure 6 As shown, the deep trench 10 penetrates the N-type heavily doped layer 200 and extends into the P-type lightly doped layer 102. Figure 8 As shown, the deep trench 10 penetrates the N-type heavily doped layer 200 and the P-type lightly doped layer 102 and extends into the P-type lightly doped substrate 101 .

[0085] Exemplarily, a patterned photoresist layer can be formed on the N-type heavily doped layer 200, and the N-type heavily doped layer 200 and the P-type lightly doped epitaxial layer 102 can be etched using the patterned photoresist layer as a mask, and the etching can be stopped at the P-type lightly doped epitaxial layer 102 to form the deep trench 10. Alternatively, the N-type heavily doped layer 200, the P-type lightly doped epitaxial layer 102, and the P-type lightly doped substrate 101 can be etched, and the etching can be stopped in the P-type lightly doped substrate 101 to form the deep trench 10, and then the patterned photoresist layer can be removed.

[0086] In step S4 , a dielectric layer 20 is formed, and the dielectric layer 20 covers the sidewalls and the bottom of the deep trench 10 .

[0087] The dielectric layer 20 comprises one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, and silicon carbonitride. Figure 6 and Figure 7 As shown, the dielectric layer 20 includes a silicon nitride layer 21 and a silicon oxide layer 22 . The silicon nitride layer 21 covers the sidewall and the bottom of the deep trench 10 , and the silicon oxide layer 22 covers the silicon nitride layer 21 .

[0088] In step S5, the dielectric layer 20 in a partial area at the bottom of the deep groove 10 is removed, and the exposed substrate 100 is wet cleaned to form a through groove 11, and the cross-sectional size of the through groove 11 located in the substrate 100 is greater than or equal to the cross-sectional size of the through groove 11 located in the dielectric layer 20.

[0089] Figure 6 In the embodiment, the through groove 11 extends into the P-type lightly doped epitaxial layer 102 and exposes a portion of the P-type lightly doped epitaxial layer 102. Figure 8 In the embodiment, the through groove 11 extends into the P-type lightly doped substrate 101 and exposes a portion of the P-type lightly doped substrate 101 .

[0090] Specifically, after forming the dielectric layer 20, the dielectric layer 20 of a part of the bottom area of ​​the deep trench 10 is etched away to expose the bottom area of ​​the dielectric layer 20, that is, to expose the P-type lightly doped epitaxial layer 102 or the P-type lightly doped substrate 101, and then the exposed area is wet cleaned to remove a part of the thickness of the P-type lightly doped epitaxial layer 102 or the P-type lightly doped substrate 101, forming the through groove 11 penetrating the dielectric layer 20 and extending into the substrate 100, and the through groove 11 can be located in the middle area of ​​the bottom of the deep trench 10. In this embodiment, the cleaning solution of the wet cleaning includes TMAH (tetramethylammonium hydroxide).

[0091] In one embodiment of the present invention, the cross-sectional size of the through groove 11 located in the substrate 100 (specifically, the P-type lightly doped substrate 101 or the P-type lightly doped epitaxial layer 102) is greater than the cross-sectional size of the through groove 11 located in the dielectric layer 20, that is, the cross-sectional size of the through groove 11 is an inverted T-shaped, so as to further increase the contact area between the first semiconductor material layer 41 and the substrate 100 and further reduce the contact resistance. In another embodiment of the present invention, the cross-sectional size of the through groove 11 located in the substrate 100 is equal to the cross-sectional size of the through groove 11 located in the dielectric layer 20, that is, the cross-sectional size of the through groove 11 is a rectangle. Of course, the cross-sectional size of the through groove 11 is not limited to this.

[0092] In step S6 , a first semiconductor material layer 41 is formed in the through-groove 11 and a second semiconductor material layer 42 is formed in the deep groove 10 by an epitaxial process, wherein the first semiconductor material layer 41 is a P-type epitaxial layer.

[0093] In this embodiment, an epitaxial process is used to form a first semiconductor material layer 41 in the through groove 11, and the first semiconductor material layer 41 fills the through groove 11, and then an epitaxial process is continued to form a second semiconductor material layer 42 in the deep groove 10. The first semiconductor material layer 41 is a P-type epitaxial layer.

[0094] When the aspect ratio of the deep trench 10 is relatively small, the second semiconductor material layer 42 may be entirely a P-type epitaxial layer. When the aspect ratio of the deep trench 10 is relatively large, a portion of the second semiconductor material layer 42 close to the first semiconductor material layer 41 may be a P-type epitaxial layer, while another portion away from the first semiconductor material layer 41 may be polycrystalline or / and amorphous, such as polycrystalline silicon or amorphous silicon. When the aspect ratio of the deep trench 10 continues to increase, a gap may be formed in the deep trench 10. The shape of the second semiconductor material layer 42 may be determined according to the actual aspect ratio of the deep trench 10.

[0095] In one embodiment of the present invention, the material of the second semiconductor material layer 42 includes one or a combination of silicon, germanium, gallium arsenide and indium phosphide.

[0096] In one embodiment of the present invention, when the deep trench 10 penetrates the N-type heavily doped layer 200 and extends into the P-type lightly doped epitaxial layer 102, the material of the first semiconductor material layer 41 is the same as the material of the P-type lightly doped epitaxial layer 102, and the conductivity of the first semiconductor material layer 41 is between the second semiconductor material layer 42 and the P-type lightly doped epitaxial layer 102. Of course, the material of the first semiconductor material layer 41 and the material of the P-type lightly doped epitaxial layer 102 may also be different.

[0097] In another embodiment of the present invention, when the deep trench 10 penetrates the N-type heavily doped layer 200 and the P-type lightly doped epitaxial layer 102 and extends into the P-type lightly doped substrate 101, the material of the first semiconductor material layer 41 is the same as that of the P-type lightly doped substrate 101, and the conductivity of the first semiconductor material layer 41 is between that of the second semiconductor material layer 42 and the P-type lightly doped substrate 101. Of course, the material of the first semiconductor material layer 41 and the material of the P-type lightly doped substrate 101 may also be different.

[0098] The present invention forms a first semiconductor material layer 41 in the through groove 11 through an epitaxial process, and the first semiconductor material layer 41 is a P-type epitaxial layer, and continues to form a second semiconductor material layer 42 in the deep groove 10 through an epitaxial process. Compared with the prior art, the difficulty of filling the deep groove 10 is reduced, and at the same time, the resistance of the electrical connection between the second semiconductor material layer 42 in the deep groove 10 and the substrate 100 is reduced, thereby improving the uniformity and stability of the electrical connection.

[0099] In addition, the present invention adopts an epitaxial process to fill the through-groove 11 and the deep groove 10 , and there is no need to purchase an additional machine to fill the deep groove 10 , which reduces the process cost and improves the process compatibility.

[0100] At the same time, the through groove 11 penetrates the dielectric layer 20 and extends into the substrate 100 , so that the contact area between the first semiconductor material layer 41 and the substrate 100 becomes larger, thereby reducing the contact resistance.

[0101] In step S7 , a metal contact is formed on the second semiconductor material layer 42 at the top of the deep trench 10 .

[0102] In this embodiment, illustratively, a silicon oxide layer 22 is first formed on the second semiconductor material layer 42, and the silicon oxide layer 22 covers the second semiconductor material layer 42. Then, a portion of the silicon oxide layer 22 is etched away to expose a portion of the second semiconductor material layer 42. Then, a metal contact is formed on the exposed second semiconductor material layer 42 to ground the second semiconductor material layer 42.

[0103] In the manufacturing method of the deep trench isolation structure provided by the present invention, after removing part of the dielectric layer 20 at the bottom of the deep trench 10 to form a through trench 11 exposing the substrate 100 (specifically the P-type lightly doped epitaxial layer 102 or the P-type lightly doped substrate 101), a first semiconductor material layer 41 is formed in the through trench 11 and a second semiconductor material layer 42 is formed in the deep trench 10 by an epitaxial process, wherein the first semiconductor material layer 41 is a P-type epitaxial layer, thereby reducing the difficulty of filling the deep trench 10 and reducing the resistance of the electrical connection between the second semiconductor material layer 42 in the deep trench 10 and the substrate 100 (specifically the P-type lightly doped epitaxial layer 102 or the P-type lightly doped substrate 101), thereby improving the uniformity and stability of the electrical connection.

[0104] In addition, since the through trench 11 and the deep trench 10 are filled by the epitaxial process, there is no need to purchase an additional machine to fill the deep trench 10, which reduces the process cost and improves the process compatibility.

[0105] Similarly, a method similar to the above method can be used to form Figure 7 and Fig. 9 The deep trench isolation structure shown in FIG. 1 is different in that the dielectric layer 20 filling the sidewall and bottom of the deep trench 10 is only a single-layer structure, and the portion of the P-type lightly doped epitaxial layer 102 or the portion of the P-type lightly doped substrate 101 located at the bottom of the deep trench 10 is P + Epitaxial layer or P + Doping layer.

[0106] To summarize, in the deep trench isolation structure and its manufacturing method provided by the present invention, after the dielectric layer in a partial area of ​​the bottom of the deep trench is removed to form a through trench exposed and extending into the substrate, a first semiconductor material layer is formed in the through trench and a second semiconductor material layer is formed in the deep trench through an epitaxial process, and the first semiconductor material layer is a P-type epitaxial layer, thereby reducing the difficulty of filling the deep trench and reducing the resistance of the electrical connection between the second semiconductor material layer in the deep trench and the substrate, thereby improving the uniformity and stability of the electrical connection.

[0107] In addition, since the through-grooves and the deep grooves are filled with an epitaxial process, there is no need to purchase additional machines to fill the deep grooves, which reduces process costs and improves process compatibility.

[0108] At the same time, the through groove penetrates the dielectric layer and extends into the substrate, so that the contact area between the first semiconductor material layer and the substrate becomes larger, thereby reducing the contact resistance.

[0109] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A deep trench isolation structure, characterized in that: include: A substrate, comprising a P-type lightly doped substrate and a P-type lightly doped epitaxial layer located on the P-type lightly doped substrate; An N-type heavily doped layer, located on the P-type lightly doped epitaxial layer; A deep trench, penetrating the N-type heavily doped layer and extending into the substrate; a dielectric layer covering the sidewalls and the bottom of the deep trench; A through groove, penetrating the dielectric layer in a partial area at the bottom of the deep groove and extending into the substrate, wherein the cross-sectional dimension of the through groove in the substrate is greater than or equal to the cross-sectional dimension of the through groove in the dielectric layer; A first semiconductor material layer, wherein the first semiconductor material layer is a P-type epitaxial layer, the first semiconductor material layer fills the through groove and is connected to the substrate; as well as The second semiconductor material layer fills the deep trench and is connected to the first semiconductor material layer. The second semiconductor material layer at the top of the deep trench has a metal contact.

2. The deep trench isolation structure according to claim 1, characterized in that: When the deep trench penetrates the N-type heavily doped layer and extends into the P-type lightly doped epitaxial layer, the material of the first semiconductor material layer is the same as that of the P-type lightly doped epitaxial layer.

3. The deep trench isolation structure according to claim 2, characterized in that: The electrical conductivity of the first semiconductor material layer is between that of the second semiconductor material layer and the P-type lightly doped epitaxial layer.

4. The deep trench isolation structure according to claim 1, characterized in that: When the deep trench penetrates the N-type heavily doped layer and the P-type lightly doped epitaxial layer and extends into the P-type lightly doped substrate, the material of the first semiconductor material layer is the same as that of the P-type lightly doped substrate.

5. The deep trench isolation structure according to claim 4, characterized in that: The electrical conductivity of the first semiconductor material layer is between that of the second semiconductor material layer and the P-type lightly doped substrate.

6. The deep trench isolation structure according to claim 1, characterized in that: The second semiconductor material layer includes a polycrystalline state and / or an amorphous state.

7. The deep trench isolation structure according to claim 6, characterized in that: The polycrystalline state and / or amorphous state is heavily P-type doped, and the doping concentration is greater than or equal to 5x10 19 cm -3 , less than or equal to 2x10 22 cm -3 .

8. The deep trench isolation structure according to claim 1, wherein: The material of the second semiconductor material layer includes one of silicon, germanium, gallium arsenide and indium phosphide or a combination thereof.

9. The deep trench isolation structure according to claim 1, characterized in that: The doping concentration of the P-type lightly doped epitaxial layer is greater than the doping concentration of the P-type lightly doped substrate.

10. A method for manufacturing a deep trench isolation structure, characterized in that: The following steps are involved: Providing a substrate, the substrate comprising a P-type lightly doped substrate and a P-type lightly doped epitaxial layer located on the P-type lightly doped substrate; forming an N-type heavily doped layer on the P-type lightly doped epitaxial layer; forming a deep trench, wherein the deep trench penetrates the N-type heavily doped layer and extends into the substrate; forming a dielectric layer, wherein the dielectric layer covers the sidewalls and the bottom of the deep trench; Removing the dielectric layer from a portion of the bottom of the deep trench, and wet-cleaning the exposed substrate to form a through-groove, wherein the cross-sectional size of the through-groove in the substrate is greater than or equal to the cross-sectional size of the through-groove in the dielectric layer; forming a first semiconductor material layer in the through-groove and a second semiconductor material layer in the deep groove by an epitaxial process, wherein the first semiconductor material layer is a P-type epitaxial layer; as well as A metal contact is formed on the second semiconductor material layer at the top of the deep trench.

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