Inhibitor, regioselective deposition method, chip and manufacturing method thereof

Abstract

The invention provides an inhibitor, a regioselective deposition method and a chip manufacturing method. According to the regioselective deposition method, the inhibitor of a specific structure is used for shielding, and selective deposition of the dielectric material can be carried out. When region selective deposition is carried out, the dielectric material can be prevented from being deposited on the surface of the metal region, and the purpose of selective deposition is achieved.

Description

Technical Field

[0001] The present application relates to the field of chip processing and manufacturing, and in particular to an inhibitor, a regional selective deposition method, a chip and a manufacturing method thereof. Background Art

[0002] As chips become smaller and more complex, the manufacture of nanochips requires increasingly complex multi-layer wiring processes. In the multi-layer wiring process, as the size of the circuit board decreases, the width of the metal traces in the circuit board also becomes smaller and smaller. When connecting the metal traces of different circuit boards, the alignment between the upper and lower circuit boards becomes more and more difficult, and the alignment accuracy requirements become higher and higher. As the number of circuit board layers increases, the edge placement error becomes larger and larger in the back-end process of nanochips. The increase in edge placement error may affect the resistance (resistance, R)-capacitance (capacitance, C) delay, and even cause dielectric breakdown and device short circuit. In order to avoid the limitation of edge placement error, the design of fully self-aligned vias (FSAV) was invented.

[0003] Introducing dielectric supports is a strategy to achieve FSAV, which can increase the spacing between the via and the metal trace. In addition, the addition of dielectric supports allows for larger critical via sizes for better metal contact and lower via resistance. For the FSAV scheme, it has been proposed that it can be achieved through metal groove etching and regional selective deposition. Although metal groove etching has been widely adopted in production, it requires multiple steps. Moreover, metal groove etching relies on wet etching chemistry, so it is prone to uneven roughness after etching, resulting in reduced electrical performance of the via. Regional selective deposition is a better solution with the potential to precisely control the thickness of the topography. At the same time, there is no need to etch the surface of the metal trace in regional selective deposition, and there will be no problem of uneven surface roughness of the metal trace after etching. During the regional selective deposition process, it is usually necessary to use inhibitors to protect the metal trace so that the subsequent dielectric material is only deposited in the substrate area outside the metal trace. Existing inhibitors are usually halogen-containing compounds and amino-containing compounds. Among them, in halogen-containing compounds, the halogen group is easy to remain on the metal surface to increase the resistivity of the metal traces, and it is easy to corrode the substrate, thereby reducing the electrical performance of the chip. In amino-containing compounds, the amino group is easy to dissociate on the transition metal surface, thereby losing selectivity, causing the regional selective deposition process to fail. Summary of the invention

[0004] The present application provides an inhibitor, a regional selective deposition method, a chip and a method for manufacturing the same, so as to overcome the defects caused by edge alignment deviation in the traditional process and improve the electrical performance of the chip.

[0005] In a first aspect, the present application provides an inhibitor for a metal surface, wherein the molecular structure of the inhibitor is as shown in formula (I),

[0006]

[0007] Wherein, Ar is an aromatic ring group having 6 to 40 carbon atoms; R is selected from at least one of a hydroxyl group, a thiol group or a carboxyl group, and n is a natural number greater than or equal to 1; and the inhibitor does not contain a halogen group in its molecular structure.

[0008] The inhibitor provided by the present application has an aromatic ring group contained in its molecular structure, and the benzene ring in the aromatic ring group can provide π electrons to coordinate with the empty orbital of the transition metal in the metal coating. The R group in the molecular structure of the inhibitor, such as a hydroxyl, a thiol or a carboxyl group, can produce coordination with the transition metal, enhance the strength of binding to the metal surface, and can also provide a strong intermolecular hydrogen bond to improve the adsorption coverage of the inhibitor on the surface of the metal coating. Since the molecular structure of the inhibitor of the present application does not contain a halogen group, the benzene ring is used to achieve connection with the metal coating, and the R group is used to achieve a dense connection between molecules to cover the metal coating. Thus, when the circuit board is deposited with a dielectric material, the dielectric material can be avoided from being deposited on the surface of the metal coating to achieve the purpose of selective deposition. The selective deposition using the inhibitor can avoid the introduction of halogen groups in the chip, so that the corrosion of the substrate by the halogen group and the increase in the resistivity of the metal routing can be avoided, thereby improving the stability of the chip. In addition, since the R group in the inhibitor of the present application is relatively stable, no decomposition reaction will occur during the deposition process, so the inhibitor can maintain a stable selective deposition effect, thereby effectively inhibiting the deposition of dielectric materials in the metal region during the regional selective deposition process.

[0009] In an optional implementation, the number of benzene rings in the aromatic ring group is 1 to 5. By controlling the number of benzene rings, the molecular weight of the inhibitor can be reduced, which facilitates the removal of the inhibitor in the later stage.

[0010] In an optional implementation, the aromatic ring group is selected from one of phenyl, biphenyl, naphthyl, anthracenyl or phenanthryl. The above aromatic ring groups may have a relatively low molecular weight and can be easily removed by heating in the later stage.

[0011] In an optional implementation, the hydrogen in the aromatic ring group may be substituted by one of an alkyl group, an alkenyl group, an alkynyl group, a hydroxyl group, a thiol group or a carboxyl group. The aromatic ring group may be an unsubstituted aromatic ring group or a substituted aromatic ring group. When the aromatic ring group is a substituted aromatic ring group, the substituent may be one of the above substituents. The above substituents will not affect the selective deposition performance of the inhibitor.

[0012] In an optional implementation, the number of the R groups is two or more, and the different R groups are the same or different. In the molecule of the inhibitor of the present application, the number of R groups can be one, two, or more than two. The more the number of R groups, the denser the shielding layer can be formed between the inhibitor molecules, and the better the selective deposition effect.

[0013] In an optional implementation, the R group is directly connected to the ring-forming carbon atom in the aromatic ring group. The direct connection between the R group and the aromatic ring group can reduce the molecular weight of the inhibitor and facilitate the dissolution and removal of the inhibitor molecule.

[0014] In an optional implementation, the inhibitor includes at least one of the following substances:

[0015]

[0016] Among them, R 1 To R 8 At least one of the R groups is the R group, and the remaining groups are each independently selected from at least one of hydrogen, alkyl, alkoxy, alkenyl or alkynyl.

[0017] In an optional implementation, the inhibitor includes at least one of the following substances:

[0018]

[0019] In a second aspect, the compound represented by formula (I) of the present application is used as an inhibitor for metal surfaces. The structure of the compound represented by formula (I) is as follows:

[0020]

[0021] Wherein, Ar is an aromatic ring group having 6 to 40 carbon atoms; R is selected from at least one of a hydroxyl group, a thiol group or a carboxyl group, and n is an integer greater than or equal to 1; and the inhibitor does not contain a halogen group in its molecular structure.

[0022] In a third aspect, the present application provides a regional selective deposition method, the method comprising the following steps:

[0023] Placing a substrate in a vapor environment or a liquid environment containing the inhibitor described in the present application to adsorb the inhibitor; the substrate comprises at least one metal region and at least one dielectric region, different metal regions are separated by at least one dielectric region, and the inhibitor is adsorbed on the surface of the metal region;

[0024] A dielectric material is deposited on the surface of the dielectric region to form a dielectric support.

[0025] In the regional selective deposition method of the present application, by using the inhibitor of the present application to block the metal area, a dielectric support can be deposited on the surface of the dielectric area, and the inhibitor can be removed afterwards. In this process, the selective deposition of the dielectric material is achieved by the blocking effect of the inhibitor on the dielectric material, and the dielectric material is prevented from being deposited on the surface of the metal area. At the same time, since the inhibitor used in the present application does not contain a halogen group, there will be no halogen residue after removing the inhibitor, and the resistivity of the metal area will not be increased, nor will corrosion to the substrate be caused, which can help to obtain a chip with more stable and reliable electrical performance. In addition, since the R group in the inhibitor of the present application is relatively stable, no decomposition reaction will occur during the deposition process, and therefore, the inhibitor can maintain a stable selective deposition effect, thereby effectively inhibiting the deposition of dielectric materials in the metal area.

[0026] In an optional implementation, the dielectric constant of the dielectric support is less than or equal to 4.

[0027] In a fourth aspect, the present application provides a method for manufacturing a chip, the manufacturing method comprising:

[0028] Placing a substrate in a vapor environment or a liquid environment containing an inhibitor as described in the present application to adsorb the inhibitor; the substrate comprises at least one metal region and at least one dielectric region, different metal regions are separated by at least one dielectric region, and the inhibitor is adsorbed on the surface of the metal region;

[0029] Depositing a dielectric material on the surface of the dielectric region to form a dielectric support;

[0030] A conductive column is formed on at least a portion of the surface of at least one of the metal regions and a portion of the surface of an adjacent dielectric support, wherein the conductive column is used to connect to a conductive region of another substrate.

[0031] The effects that can be achieved by the third aspect of the present application can be referred to the description of the second aspect and will not be repeated here.

[0032] In a fifth aspect, the present application provides a chip, including:

[0033] A first wiring layer is provided with at least one first metal wiring and at least one first dielectric substrate, and different first metal wirings are separated by at least one first dielectric substrate; a dielectric support is provided on the surface of the first dielectric substrate, and an etching stop layer is provided on the surface of the dielectric support and the surface of the part of the first metal wiring;

[0034] The second wiring layer is stacked with the first wiring layer, and includes a second metal wiring and a second dielectric substrate; the second dielectric substrate is in contact with the etching stop layer; the second dielectric substrate is provided with at least one through hole, the hole wall surface of the through hole is provided with a barrier layer and an adhesive layer, the through hole is filled with a conductive medium to form a conductive column, and the conductive column connects at least part of the first metal wiring and at least part of the second metal wiring; wherein,

[0035] The conductive pillar is directly connected to a first metal region connected to the conductive pillar.

[0036] In the chip of the present application, a barrier layer and an adhesive layer are provided between the conductive column and the second dielectric matrix. The barrier layer is used to prevent the conductive medium in the conductive column from diffusing into the second dielectric matrix, and the adhesive layer is used to improve the bonding performance between the conductive column and the barrier layer. Since the conductive column and the first metal wiring are both conductive components, the diffusion problem of the conductive medium between the two does not need to be considered. In traditional chips, the barrier layer and the adhesive layer are often formed on the surface of the first metal wiring when the barrier layer and the adhesive layer are made. The conductivity of the barrier layer and the adhesive layer is much lower than that of the conductive column and the first metal wiring. Therefore, when the barrier layer and the adhesive layer are formed between the conductive column and the first metal wiring, the resistance between the two will increase, reducing the electrical performance of the chip. In the present application, the conductive column and the first metal wiring are directly contacted and connected, which can avoid the problem of increased resistivity caused by the barrier layer and the adhesive layer, thereby improving the electrical performance of the chip.

[0037] In a sixth aspect, the present application provides a method for manufacturing a chip, comprising:

[0038] Providing a first wiring layer, wherein the first wiring layer comprises at least one first metal wiring and at least one first dielectric substrate, wherein different first metal wirings are spaced apart by at least one first dielectric substrate; a dielectric support is provided on the surface of the first dielectric substrate, and an etching stop layer is provided on the surface of the dielectric support and the surface of the part of the first metal wiring;

[0039] Depositing a dielectric material on the surface of the first wiring layer to form a second dielectric matrix;

[0040] Performing patterned etching on the second dielectric substrate to form a groove for filling the second metal wiring, and etching in the groove region to form a through hole, wherein the through hole is arranged corresponding to at least a portion of the first metal wiring;

[0041] placing the tank body and the through hole in a vapor environment or a liquid environment of the inhibitor of the present application to adsorb the inhibitor, wherein the inhibitor is adsorbed on the surface of the first metal wiring;

[0042] After forming a barrier layer and an adhesion layer on the groove wall of the groove body and the hole wall of the through hole, the inhibitor is removed and a conductive medium is filled. The conductive medium filled in the groove body forms a second metal wiring, and the conductive medium filled in the through hole forms a conductive column. The conductive column corresponding to the first metal wiring is directly in contact with the first metal wiring.

[0043] The manufacturing method provided by the present application can form a barrier layer and an adhesive layer only on the hole wall of the through hole and the groove wall surface of the groove body for filling the second metal wiring after the inhibitor is adsorbed on the surface of the first metal wiring before forming the conductive column, so as to avoid forming a barrier layer and an adhesive layer on the surface of the first metal wiring, so that the conductive column can be directly connected to the first metal wiring. That is, there is no barrier layer and an adhesive layer between the conductive column and the first metal wiring, so as to ensure that the interface resistance between the conductive column and the first metal wiring is kept low, thereby helping to improve the electrical performance of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 It is a schematic diagram of a partial structure of a chip;

[0045] Figures 2 to 5 A schematic diagram of a process flow of forming a dielectric support by regional selective deposition according to an embodiment of the present application;

[0046] Figure 6 This is a schematic diagram of the structure of a chip with no barrier layer on the surface of the metal routing.

[0047] Reference numerals:

[0048] 01-wiring layer; 011-first wiring layer; 012-second wiring layer; 10-substrate; 11-dielectric region;

[0049] 111 - first dielectric substrate; 112 - second dielectric substrate; 12 - metal region; 121 - first metal wiring;

[0050] 122 - second metal wiring; 21 - dielectric support; 22 - etching stop layer; 23 - conductive column; 24 - barrier layer;

[0051] 20-Inhibitor. DETAILED DESCRIPTION

[0052] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings.

[0053] The terms used in the following embodiments are only for the purpose of describing specific embodiments and are not intended to be limiting of the present application. As used in the specification and appended claims of the present application, the singular expressions "a", "an", "above", "the" and "this" are intended to also include expressions such as "one or more", unless there is a clear contrary indication in the context.

[0054] References to "one embodiment" or "some embodiments" etc. described in this specification mean that a particular feature, structure or characteristic described in conjunction with the embodiment is included in one or more embodiments of the present application. Thus, the phrases "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear at different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0055] To facilitate understanding of this application, the application scenario is explained below.

[0056] Figure 1 Figure 1 is a schematic diagram of a partial structure of a chip. Figure 1 As shown, the chip may include a multi-layer wiring layer 01. Figure 1 The chip shown in FIG. 1 only shows two wiring layers 01. The number of wiring layers 01 can be two or more, which is not specifically limited here. Figure 1 As shown, a first wiring layer 011 is provided at the bottom, and a second wiring layer 012 is provided at the top. A first dielectric substrate 111 and a first metal wiring 121 are provided in the first wiring layer 011, and a second dielectric substrate 012 and a second metal wiring 122 are provided in the second wiring layer 012. The first metal wiring 121 and the second metal wiring 122 can be electrically connected through a conductive column 23, such as a metal column. The first metal wiring 121 is embedded in the first dielectric substrate 111, and the first dielectric substrate 111 can be a low dielectric material layer. The second metal wiring 122 is embedded in the second dielectric substrate 112. The second dielectric substrate 112 can also be a low dielectric material layer. Among them, a barrier layer 24 (such as Figure 1 In the embodiment shown in black lines in the figure, the metal elements in the first metal wiring 121 are prevented from entering the first dielectric 111. In addition, an adhesive layer (not shown in the figure) can be provided between the first metal wiring 121 and the barrier layer 24 to improve the bonding strength between the barrier layer 24 and the first metal wiring 121.

[0057] When connecting the first metal wiring 121 and the second metal wiring 122, since the size of the metal wiring in the first metal wiring 121 and the second metal wiring 122 is small, generally at the nanometer level, when manufacturing the conductive pillar 23, there is often a certain deviation in the connection position between the conductive pillar 23 and the first metal wiring 121 due to the error of the equipment system, such as Figure 1 The deviation dimension L is shown in the dotted line. When the positional relationship between the conductive column and the first metal wiring 121 deviates, the distance between the conductive column 23 and other adjacent areas of the first metal wiring 121 will be reduced. In order to prevent the problem of short circuit between the conductive column 23 and other areas of the first metal wiring 121, a dielectric support is generally provided on the surface of the substrate to increase the distance between the conductive column and the metal wiring, increase the resistance between the conductive column and the first metal wiring, and prevent short circuit or breakdown. Among them, the formation of the dielectric support needs to be carried out by a regional selective deposition method to avoid the deposition of the dielectric support on the surface of the first metal wiring, which affects the electrical performance of the first circuit board.

[0058] It can be understood that in the chip, an etch stop layer 22 may be provided on the surface of the first metal wiring 121 and the surface of the second metal wiring 122 to protect the metal region in the chip from being etched. Figure 1 The structure in the figure is only an exemplary description, mainly used to illustrate the connection relationship between the first metal wiring and the second metal wiring. The structure of a specific chip may include more and more complex connection circuit connection structures. No further description will be given here.

[0059] Figures 2 to 5 This is a schematic diagram of a process flow of forming a dielectric support by regional selective deposition in one embodiment of the present application. Figures 2 to 5 The area selective deposition method is further described in detail.

[0060] The area selective deposition method of the embodiment of the present application may include the following steps:

[0061] Step S11, providing a substrate, the structure of the substrate is as follows Figure 2 As shown. Figure 2 As shown, in one embodiment, the substrate 10 may include at least one dielectric region 11 and at least one metal region 12. A dielectric region 11 is provided between any two adjacent metal regions 12. The dielectric region 11 may be a dielectric matrix of the substrate 10, and the metal region 12 may be a metal trace embedded in the dielectric region 11. The metal traces may be interconnected to form a circuit connection structure with specific functions.

[0062] The first dielectric material forming the dielectric matrix may be a material with a low dielectric constant, such as a material with a dielectric constant less than or equal to 4. Exemplarily, the first dielectric material includes but is not limited to silicon dioxide or siloxane. The material of the metal trace may be a transition metal such as Cu, Co, Ru, or Mo.

[0063] Step S12: Figure 3 As shown, the substrate 10 is placed in a vapor environment or a liquid environment of the inhibitor 20 to deposit the inhibitor 20 . The inhibitor 20 is deposited on the surface of the metal region 12 , and no inhibitor is deposited on the surface of the dielectric region 11 .

[0064] Step S13: Figure 4 As shown, the substrate 10 with the inhibitor 20 deposited thereon is placed in a vapor environment of a second dielectric material, or in a vapor environment of a reaction raw material for forming the second dielectric material, and the second dielectric material is deposited on the surface of the substrate. Due to the shielding and inhibiting effect of the inhibitor 20, the second dielectric material will be deposited on the surface of the dielectric region 11, and a dielectric support 21 will be formed on the surface of the dielectric region 11.

[0065] The second dielectric material may be a material with a low dielectric constant, such as a siloxane dielectric material. Siloxane dielectric materials have a relatively low dielectric constant and can obtain a dielectric support with a low dielectric constant. In addition, it is found through experiments that when the inhibitor of the present application is used for regional selective deposition, when the second dielectric material is a siloxane dielectric material, the inhibitor has a better effect of inhibiting the deposition of such material, thereby effectively preventing the second dielectric material from being deposited on the surface of the metal region.

[0066] Step S14: Figure 5 As shown, the inhibitor on the surface of the metal region 12 is removed. The removal method includes but is not limited to a heating evaporation method, a solvent dissolution method, etc. In order to avoid the introduction of impurities, the removal method preferably uses a heating evaporation method to remove the inhibitor.

[0067] Among them, the inhibitor used in the examples of the present application has a molecular structure as shown in formula (I):

[0068]

[0069] Wherein, Ar is an aromatic ring group having 6 to 40 carbon atoms; the aromatic ring group is a substituted or unsubstituted aromatic ring group, and the substituent in the aromatic ring group may be at least one of an alkyl group, an alkoxy group, an alkenyl group or an alkynyl group. R is selected from at least one of a hydroxyl group, a thiol group or a carboxyl group, and n is a natural number greater than or equal to 1. The molecular structure of the inhibitor does not contain a halogen group, such as a Cl element.

[0070] In one embodiment, the number of benzene rings in the aromatic ring group may be 1-5. The number of benzene rings in the aromatic ring group is preferably 1-3, and more preferably 1-2. The fewer the number of benzene rings, the smaller the molecular weight of the inhibitor, and the more convenient it is to remove the inhibitor by heating evaporation. Exemplarily, the aromatic ring group in the inhibitor of the embodiment of the present application includes but is not limited to one of phenyl, biphenyl, naphthyl, anthracenyl or phenanthrenyl. Among them, the aromatic ring group may be an unsubstituted aromatic ring group or a substituted aromatic ring group. When the aromatic ring group is a substituted aromatic ring group, the hydrogen in the aromatic ring group may be replaced by one of a C1-C5 alkyl, a C1-C5 alkenyl, a C1-C5 alkynyl, a hydroxyl, a thiol or a carboxyl group.

[0071] The number of R groups in the molecular structure of the inhibitor in the embodiment of the present application may be one, or two or more. When there are two or more R groups, different R groups may be the same or different. The R group may be directly connected to the ring-forming carbon atoms in the aromatic ring group to reduce the molecular weight of the inhibitor. When the inhibitor is deposited on the surface of the metal area, the R group not only increases the binding strength between the inhibitor and the metal, but also can generate intermolecular hydrogen bonding between the R groups of different molecules, so that the molecules of different inhibitors are closely adsorbed together to form a dense shielding layer.

[0072] In one embodiment, the inhibitor comprises at least one of the following substances:

[0073]

[0074] Among them, R 1 To R 8 At least one of them is said R group, R 1 To R 8 The remaining non-R groups in may each be independently selected from at least one of hydrogen, alkyl, alkoxy, alkenyl or alkynyl.

[0075] Exemplarily, the inhibitor includes but is not limited to at least one of the following substances:

[0076]

[0077]

[0078] The inhibitor and the selective deposition method of the present application will be further described in detail below in conjunction with specific embodiments.

[0079] Example 1

[0080] This embodiment is a method for area selective deposition. The wiring layer includes a substrate and metal wiring. The substrate is SiO 2, the metal trace is Co. The inhibitor is 3,5-dimethylphenol, and the dielectric material precursor used to form the dielectric support is trivinyltrimethylcyclotrisiloxane (1,3,5-trivinyltrimethylcyclotrisiloxane, V 3 D 3 ) and a mixture of tert-butyl peroxide (TBPO).

[0081] The specific deposition method includes the following steps:

[0082] Step S11, 3,5-dimethylphenol is selected as an inhibitor, and the inhibitor is adsorbed on the surface of the metal wiring in the circuit board of the low vacuum cavity by low vacuum pressure control adsorption. In the adsorption process, the heating temperature of the inhibitor is 40-120°C, the ventilation pipe temperature of the inhibitor is 50-150°C, the partial pressure in the low vacuum adsorption cavity is 50-1000mTorr, and the introduction time of the inhibitor is 0.1-300s.

[0083] Step S12: purge with Ar gas for 0.5-30 min, then perform V 3 D 3 The deposition of V is circulated in the deposition chamber in sequence. 3 D 3 and TBPO, V 3 D 3 The heating temperature of TBPO is 40-80℃, and the carrier gas flow rate is 1-20sccm; the heating temperature of TBPO is 25-45℃, and the carrier gas flow rate is 1-20sccm; the plasma power during deposition is 50-500W, and the substrate temperature is 30-120℃; during the deposition process, TBPO and V 3 D 3 The single-pass order and time are as follows: ① 0.5-30s-TBPO (Ar plasma carrier gas), ② 10-300s-Ar, ③ 0.5-120s-V 3 D 3 、④10-600s-Ar; repeat this cycle.

[0084] Example 2

[0085] This embodiment is a regional selective deposition method. Compared with Embodiment 1, step S11 is different from Embodiment 1, and step S12 is the same as Embodiment 1.

[0086] The process of depositing the inhibitor in this embodiment is as follows: phenol is selected as the inhibitor, and the inhibitor is adsorbed on the surface of the metal traces in the circuit board by low vacuum pressure control adsorption. In the adsorption process, the heating temperature of the inhibitor is 40-120°C, the temperature of the ventilation pipe of the inhibitor is 50-150°C, the partial pressure in the deposition chamber is 10-500mTorr, and the introduction time of the inhibitor is 0.5-30s.

[0087] Example 3

[0088] This embodiment is a selective deposition method. Compared with Embodiment 1, step S11 is different from Embodiment 1, and step S12 is the same as Embodiment 1.

[0089] The process of depositing the inhibitor in this embodiment is as follows: benzoic acid is selected as the inhibitor, and the inhibitor is adsorbed on the surface of the metal traces in the circuit board by low vacuum pressure control adsorption. In the adsorption process, the heating temperature of the inhibitor is 40-120°C, the temperature of the ventilation pipe of the inhibitor is 50-150°C, the partial pressure in the deposition chamber is 20-1000mTorr, and the introduction time of the inhibitor is 0.5-30s.

[0090] Example 4

[0091] This embodiment is a selective deposition method. Compared with Embodiment 1, step S11 is different from Embodiment 1, and step S12 is the same as Embodiment 1.

[0092] The process of depositing the inhibitor in this embodiment is as follows: 4-toluene thiophenol is selected as the inhibitor, and the inhibitor is adsorbed on the surface of the metal traces in the circuit board by low vacuum pressure control adsorption. In the adsorption process, the heating temperature of the inhibitor is 40-120°C, the temperature of the ventilation pipe of the inhibitor is 50-150°C, the partial pressure in the deposition chamber is 20-1000mTorr, and the introduction time of the inhibitor is 0.5-30s.

[0093] Comparative Example 1

[0094] This comparative example is a deposition method, and compared with Example 1, this comparative example does not include step S11, that is, no inhibitor is used to cover the surface of the metal wiring. The dielectric support is directly deposited.

[0095] Comparative Example 2

[0096] This comparative example is a regional selective deposition method. Compared with Example 1, step S11 of this comparative example is different from Example 1, and step S12 is the same as Example 1.

[0097] The process of depositing the inhibitor in this embodiment is as follows: aniline is selected as the inhibitor, and the inhibitor is adsorbed on the surface of the metal traces in the circuit board by low vacuum pressure control adsorption. In the adsorption process, the heating temperature of the inhibitor is 40°C, the temperature of the ventilation pipe of the inhibitor is 45°C, the partial pressure in the deposition chamber is 50mTorr, and the introduction time of the inhibitor is 20s.

[0098] The adsorption amount of the inhibitors of each embodiment and comparative example on the metal surface and the substrate surface was tested respectively. The test results are listed in Table 1.

[0099] The method for testing the surface adsorption amount is to use an in-situ quartz crystal microbalance (QCM).

[0100] Table 1

[0101]

[0102] It can be seen from the relevant data in Table 1 that the inhibitors of each embodiment of the present application can be selectively adsorbed on the surface of the metal area, and are basically not adsorbed on the surface of the dielectric area, thereby achieving the effect of selective adsorption.

[0103] In addition, the inhibitor of the present application can obtain a higher adsorption capacity relative to the adsorbent of aniline. Mainly because, the inhibitor of aniline, the amine group on its surface relative to the R group in the inhibitor of the present application, the hydrogen bond binding energy (about 11kJ / mol) between the amine groups is relatively low, resulting in its intermolecular self-binding energy being relatively low, and the denseness of adsorption is low, so the adsorption capacity of aniline is less. And the inhibitor of each embodiment of the present application, it has a higher adsorption capacity on the surface of Co, and relative to aniline, the adsorption capacity has increased by about one time. The inhibitor of each embodiment of the present application, the binding energy between the R groups is higher, generally greater than 30kJ / mol, and the high binding energy between molecules can promote the combination between the inhibitor molecules to be tighter, so that more inhibitors are deposited on the surface of the metal.

[0104] The thickness of the dielectric support under different cycle times in different embodiments and comparative examples was tested respectively, and the test data are listed in Table 2.

[0105] The dielectric support thickness is measured by using an ellipsometry (ES) spectrometer.

[0106] Table 2

[0107]

[0108] From the data of Comparative Example 1 in Table 2, it can be seen that the dielectric support V deposited by PEALD 3 D 3After 30 cycles of deposition, the thickness of the deposited film on the Co surface is 2.57 nm. 2 The thickness of the surface is 16.39nm. 3 D 3 The precursor itself is in the metal Co, matrix SiO 2 There is a certain selective deposition effect on both surfaces.

[0109] From the data of Example 1 in Table 2, it can be seen that after the surface of Co was treated with the inhibitor 3,5-dimethylphenol, V 3 D 3 After 30 cycles of deposition, the Co surface is V compared with the sample V of Comparative Example 1. 3 D 3 The deposition thickness decreased by 1.42nm, a decrease of 55.0%. SiO 2 Surface comparison with sample V of comparative example 1 3 D 3 The deposition thickness decreased by 0.15 nm, a decrease of 0.9%. This indicates that after the application of 3,5-dimethylphenol, V 3 D 3 The deposition of 3,5-dimethylphenol on the Co surface 3 D 3 In SiO 2 The surface deposition has little effect.

[0110] From the data of Example 2 in Table 2, it can be seen that after the surface precipitation of Co was treated with the inhibitor phenol, V 3 D 3 After 30 cycles of deposition, the Co surface is V compared with the sample V of Comparative Example 1. 3 D 3 The deposition thickness is reduced by 1.54nm, a 60% decrease. SiO 2 Surface comparison with sample V of comparative example 1 3 D 3 The deposition thickness decreased by 0.42 nm, a decrease of 2.56%. This indicates that after the application of phenol, V 3 D 3 The deposition of phenol on the Co surface 3 D 3 In SiO 2 The surface deposition has little effect.

[0111] From the data of Example 3 in Table 2, it can be seen that after the surface precipitation of Co was treated with inhibitor benzoic acid, V 3 D 3 After 30 cycles of deposition, the Co surface is V compared with the sample V of Comparative Example 1. 3 D 3The deposition thickness is reduced by 1.39nm, a 54% decrease. SiO 2 Surface comparison with sample V of comparative example 1 3 D 3 The deposition thickness decreased by 0.75 nm, a decrease of 4.6%. This indicates that after the application of benzoic acid, V 3 D 3 The deposition of benzoic acid on the Co surface 3 D 3 In SiO 2 Surface deposition has a slight effect.

[0112] From the data of Example 4 in Table 2, it can be seen that after the surface precipitation of Co was treated with the inhibitor 4-toluene thiophenol, V 3 D 3 After 30 cycles of deposition, the Co surface is V compared with the sample V of Comparative Example 1. 3 D 3 The deposition thickness is reduced by 1.47nm, a 57% decrease. SiO 2 Surface comparison with sample V of comparative example 1 3 D 3 The deposition thickness decreased by 0.14 nm, a decrease of 0.85%. This indicates that after the application of 4-toluenethiophenol, V 3 D 3 The deposition on the Co surface was 4-methylthiophenol. 3 D 3 In SiO 2 The surface deposition has little effect.

[0113] From the data of Comparative Example 2 in Table 2, it can be seen that after the surface precipitation of Co was treated with inhibitor aniline, V 3 D 3 After 30 cycles of deposition, the Co surface is V compared with the sample V of Comparative Example 1. 3 D 3 The deposition thickness is reduced by 1.14nm, a 44% decrease. SiO 2 Surface comparison with sample V of comparative example 1 3 D 3 The deposition thickness decreased by 0.65 nm, a decrease of 4.0%. This indicates that after aniline treatment, aniline can inhibit the 3 D 3 While Co is deposited on the surface, V 3 D 3 In SiO 2 Surface deposition has a slight effect.

[0114] From the above analysis, it can be seen that the inhibitor of the embodiment of the present application can be closely adsorbed on the surface of the transition metal during the selective deposition process, thereby inhibiting the deposition of the dielectric material and achieving the purpose of selective deposition. The inhibitor and the selective deposition method of the embodiment of the present application can be applied to the chip manufacturing process to improve the reliability of the chip.

[0115] A method for manufacturing a chip according to an embodiment of the present application may include the following steps:

[0116] S21, placing a substrate in a vapor environment or a liquid environment containing an inhibitor according to an embodiment of the present application to deposit the inhibitor; the substrate comprises at least one metal region and at least one dielectric region mainly formed by a first dielectric material, different metal regions are separated by at least one dielectric region, and the inhibitor is deposited on the surface of the metal region;

[0117] S22, depositing a second dielectric material on the surface of the dielectric region to form a dielectric support;

[0118] S23, forming a conductive column on at least a portion of the surface of at least one of the metal regions and a portion of the surface of an adjacent dielectric support, wherein the conductive column is used to connect to another conductive region of the substrate.

[0119] Reference Figure 1 The manufacturing method of the embodiment of the present application comprises the following steps:

[0120] S31, a first wiring layer 011 having a first metal wiring 121 and a first dielectric substrate 111 is obtained by using the selective deposition method of an embodiment of the present application; a dielectric support 21 is formed on a part of the surface of the first wiring layer;

[0121] S32, forming an etching stop layer 22 on the surface of the first dielectric substrate 111 and a portion of the first metal wiring 121;

[0122] S33, forming a conductive pillar 23 on the surface of the first metal wiring 121 where the etching stop layer 22 is not deposited, wherein the end surface of the conductive pillar 23 facing the first metal wiring 121 is a stepped surface, and is respectively connected to the first metal wiring 121 and the dielectric support 21;

[0123] S34 , connecting the conductive pillar 23 to the second metal wiring 122 of the second wiring layer 012 .

[0124] It is understandable that the inhibitor and selective deposition method of the present application can be applied to the process of selectively depositing a barrier layer or an adhesion layer in the semiconductor chip manufacturing process, in addition to being applied to the FSAV application scenario of making a dielectric support on the surface of a substrate, for example Figure 6As shown, barrier-free through-hole manufacturing. Through-hole manufacturing without barrier layer can be achieved by depositing an inhibitor on the metal surface, inhibiting the metal surface, and then selectively depositing a barrier layer on the surface of the dielectric layer to prevent the barrier layer from being deposited on the surface of the metal layer, so as to achieve barrier-free connection between the upper and lower interconnect metal layers when filling the interconnect metal in the subsequent process, thereby reducing the interconnect resistance.

[0125] Specifically, refer to Figure 6 A method for manufacturing a chip without a barrier layer mentioned in an embodiment of the present application comprises the following steps:

[0126] S31, providing a first wiring layer 011, wherein the first wiring layer 011 comprises a first metal wiring 121 and a first dielectric substrate 111, a dielectric support 21 is provided on the surface of the first dielectric substrate 111, and an etching stop layer 22 is provided on the surface of the dielectric support 21 and a portion of the first metal wiring 121;

[0127] S32, depositing a dielectric material on the surface of the first wiring layer 011 to form a second dielectric matrix 112;

[0128] S33, performing patterned etching on the second dielectric substrate 112 to form a groove for filling the second metal wiring 122, and etching at the bottom of the groove area to form a through hole, wherein the through hole is arranged corresponding to at least the first metal wiring 121;

[0129] S34, placing the tank body and the through hole in a vapor environment or a liquid environment of the inhibitor of the present application to adsorb the inhibitor, wherein the inhibitor is adsorbed on the surface of the first metal wiring 121;

[0130] S35. After forming a barrier layer and an adhesion layer on the groove wall of the groove body and the hole wall of the through hole, the inhibitor is removed and a conductive medium is filled. The conductive medium filled in the groove body forms a second metal wiring 122, and the conductive medium filled in the through hole forms a conductive column 23. The conductive column 23 corresponding to the first metal wiring 121 is directly in contact with the first metal wiring 121.

[0131] The chip obtained by the preparation method of the embodiment of the present application includes: a first wiring layer and a second wiring layer. The first wiring layer is provided with at least one first metal wiring and at least one first dielectric substrate, and different first metal wirings are separated by at least one first dielectric substrate; a dielectric support is provided on the surface of the first dielectric substrate, and an etching stop layer is provided on the surface of the dielectric support and the part of the first metal wiring. The second wiring layer is stacked with the first wiring layer, including a second metal wiring and a second dielectric substrate; the second dielectric substrate is in contact with the etching stop layer; the second dielectric substrate is provided with at least one through hole, and the wall surface of the through hole is provided with a barrier layer and an adhesive layer, and the through hole is filled with a conductive medium to form a conductive column, and the conductive column connects at least part of the first metal wiring and at least part of the second metal wiring; wherein the conductive column is directly contacted and connected with the first metal region connected to the conductive column.

[0132] In the chip of the embodiment of the present application, there is no barrier layer and bonding layer between the conductive column and the first metal wiring, and there is no additional interface resistance between the conductive column and the first metal wiring. The interface impedance between the two is low, and the conductivity efficiency is high. The problem of increased resistivity caused by the barrier layer and bonding layer can be avoided, thereby improving the electrical performance of the chip.

[0133] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. An inhibitor for metal surface, characterized in that The molecular structure of the inhibitor is shown in formula (I), Wherein, Ar is an aromatic ring group having 6 to 40 carbon atoms; R is selected from at least one of a hydroxyl group, a thiol group or a carboxyl group, and n is a natural number greater than or equal to 1; and the inhibitor does not contain a halogen group in its molecular structure.

2. The inhibitor according to claim 1, characterized in that In the aromatic ring group, the number of benzene rings is 1-5.

3. The inhibitor according to claim 2, characterized in that The aromatic ring group is selected from one of phenyl, biphenyl, naphthyl, anthracenyl or phenanthryl.

4. The inhibitor according to any one of claims 1 to 3, characterized in that The number of the R groups is two or more, and different R groups are the same or different.

5. The inhibitor according to any one of claims 1 to 4, characterized in that The R group is directly connected to a ring-forming carbon atom in the aromatic ring group.

6. The inhibitor according to any one of claims 1 to 5, characterized in that The inhibitor comprises at least one of the following substances: Among them, at least one of R1 to R8 is the R group, and the remaining groups are each independently selected from at least one of hydrogen, alkyl, alkoxy, alkenyl or alkynyl.

7. The inhibitor according to claim 6, characterized in that The inhibitor comprises at least one of the following substances:

8. Use of the compound represented by formula (I) as an inhibitor for metal surfaces, in, The Ar is an aromatic ring group with 6 to 40 carbon atoms; the R is selected from at least one of a hydroxyl group, a thiol group or a carboxyl group, and n is an integer greater than or equal to 1; and the molecular structure of the inhibitor does not contain a halogen group.

9. A regional selective deposition method, characterized in that: include: Placing a substrate in a vapor environment or a liquid environment containing the inhibitor according to any one of claims 1 to 7 to adsorb the inhibitor; the substrate comprises at least one metal region and at least one dielectric region mainly formed by a first dielectric material, different metal regions are separated by at least one dielectric region, and the inhibitor is adsorbed on the surface of the metal region; A second dielectric material is deposited on the surface of the dielectric region to form a dielectric support.

10. The area selective deposition method according to claim 9, characterized in that: The dielectric constant of the dielectric support is less than or equal to 4.

11. A method for manufacturing a chip, characterized in that: include: Placing a substrate in a vapor environment or a liquid environment containing the inhibitor according to any one of claims 1 to 7 to adsorb the inhibitor; the substrate comprises at least one metal region and at least one dielectric region mainly formed by a first dielectric material, different metal regions are separated by at least one dielectric region, and the inhibitor is adsorbed on the surface of the metal region; Depositing a second dielectric material on the surface of the dielectric region to form a dielectric support; A conductive column is formed on at least a portion of the surface of at least one of the metal regions and a portion of the surface of an adjacent dielectric support, wherein the conductive column is used to connect to a conductive region of another substrate.

12. A method for manufacturing a chip, characterized in that: include: Providing a first wiring layer, wherein the first wiring layer comprises at least one first metal wiring and at least one first dielectric substrate, wherein different first metal wirings are spaced apart by at least one first dielectric substrate; a dielectric support is provided on the surface of the first dielectric substrate, and an etching stop layer is provided on the surface of the dielectric support and the surface of the part of the first metal wiring; Depositing a dielectric material on the surface of the first wiring layer to form a second dielectric matrix; Performing patterned etching on the second dielectric substrate to form a groove for filling the first metal wiring, and etching in the groove region to form a through hole, wherein the through hole is arranged corresponding to at least a portion of the first metal wiring; Placing the groove body and the through hole in a vapor environment or a liquid environment of the inhibitor according to any one of claims 1 to 7 to adsorb the inhibitor, wherein the inhibitor is adsorbed on the surface of the first metal wiring; After forming a barrier layer and an adhesion layer on the groove wall of the groove body and the hole wall of the through hole, the inhibitor is removed and a conductive medium is filled. The conductive medium filled in the groove body forms a second metal wiring, and the conductive medium filled in the through hole forms a conductive column. The conductive column corresponding to the first metal wiring is directly in contact with the first metal wiring.

13. A chip, characterized in that: Obtained by the production method as claimed in claim 12.

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