Field effect transistor, trench MOS type diode and insulated gate bipolar transistor

Abstract

The invention belongs to the technical field of semiconductors, and provides a field effect transistor with high on-state through-current capability and lower off-state electric leakage capability based on structural innovation of a Schottky source-drain MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). An n-channel normally-closed MOSFET is taken as an example, on the basis that a Schottky junction formed by a source electrode and an n-type semiconductor region is originally utilized to deplete electron carriers in the n-type semiconductor region from one side, a Schottky gate or a p-type gate is introduced to deplete the electron carriers in the n-type semiconductor region from the other side, so that the influence effect of double-side depletion is realized, and the reliability of the device is improved. Thus, in the aspect of electrical performance, the on-state through-current capability is maintained, off-state electric leakage is further reduced, and meanwhile adjustment of the starting voltage is facilitated; in the aspect of the manufacturing process, the key width dimension requirement can be relaxed, and the photoetching amp is reduced; the requirements of the etching technology and equipment are met, the process window is expanded, and the batch production yield is improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular, relates to a field effect transistor, a trench MOS diode and an insulated gate bipolar transistor. Background Art

[0002] The Schottky source-drain MOSFET structure was proposed in the 1960s. It uses metal source-drain to replace the semiconductor-doped source-drain of the traditional pn junction MOSFET, and a Schottky contact barrier is formed between the metal source-drain and the semiconductor. For Schottky source-drain MOSFET, when a positive voltage is applied between the drain and the source, the Schottky barrier formed between the source and the semiconductor material is reverse biased, causing the depletion layer to widen to achieve shutdown. Based on this, the Schottky source-drain MOSFET is a normally-off device; the conduction of the Schottky source-drain MOSFET is achieved by forming a conductive channel under the action of a positive gate bias, and the carriers at the source end directly tunnel through the barrier into the channel.

[0003] Since the birth of Schottky source-drain MOSFET, there have been two significant disadvantages: First, the on-state current is small. When the drain-source voltage V of Schottky source-drain MOSFET DS When >0, the Schottky contact barrier formed by the Schottky source electrode and the semiconductor is reverse biased to widen the depletion region, so that even if a positive gate-source voltage V is applied between the gate electrode and the Schottky source electrode GS When the voltage is high, a complete and high-concentration electron conduction channel cannot be formed between the drain electrode and the Schottky source electrode. There is always a certain Schottky barrier height in the area close to the Schottky source electrode. This limited Schottky barrier height inhibits the transport of electron carriers, so that only a small number of electron carriers form current through the tunneling effect. According to the conductivity calculation formula σ=nqu (where n is the concentration of electron carriers participating in conduction, q is the electron charge, and u is the mobility under certain carrier concentration conditions), the lower the carrier concentration n participating in conduction, the lower the conductivity σ. According to current density J = σE (where E represents the electric field strength), the lower the conductivity σ, the lower the current density J. This is why the on-state current of a Schottky source-drain MOSFET is smaller than the on-state current of a pn junction MOSFET under the same conditions. The on-state current of a conventional pn junction MOSFET can reach tens to hundreds of amperes, while the on-state current of a Schottky source-drain MOSFET under the same conditions can only reach milliamperes or even lower. Second, the off-state leakage is large, and the leakage current includes the thermal electron emission current from the source junction transmitted through the substrate and the tunneling current from the source junction.

[0004] In the patent application number 202310325051.0, the applicant adjusts the pure Schottky source in the Schottky source-drain MOSFET to a combination of an ohmic source and a Schottky source, wherein the ohmic source is between the gate insulating film and the Schottky source. Through the design improvement of this structural detail, the problem of low on-state current of the Schottky source-drain MOSFET is completely solved, making its on-state current capacity comparable to that of the pn junction MOSFET under the same conditions. At the same time, in the equilibrium state (when V DS =0&V GS =0), the normally-off function can be realized by utilizing the local depletion effect of electron carriers on the Schottky junction formed by the Schottky source and the n-type semiconductor layer.

[0005] However, in the equilibrium state (when V DS =0&V GS =0), the normally-off effect is achieved only by relying on the unilateral depletion effect of the electron carriers in the n-type semiconductor layer between the Schottky source and the gate insulating film layer produced by the Schottky junction formed by the Schottky source and the n-type semiconductor layer. It is necessary that the width of the n-type semiconductor layer between the gate insulating film and the Schottky source and the ohmic source in contact therewith be as small as possible. Taking silicon semiconductor material as an example, the width of the ohmic source needs to be ≤100nm to ensure a good normally-off effect. This places extremely high demands on the wafer manufacturing process, especially the lithography & etching technology and equipment. The process window is narrow, the fault tolerance is small, and it is easy to exceed the width size and cause large off-state leakage of the device. Summary of the invention

[0006] In view of this, the present invention introduces a metal material or a p-type gate electrode material that can form a Schottky barrier with the semiconductor layer into the gate electrode, so that the gate electrode has a depletion effect on the electron carriers in the semiconductor layer, thereby achieving a double-sided pinch-off effect. This can relax the precision control of the key width dimension, reduce the requirements for lithography & etching technology and equipment, and solve the problem of large off-state leakage of the device due to the narrow process window, which easily causes the width dimension to exceed the limit.

[0007] In order to solve the above technical problems, the present invention provides a field effect transistor having:

[0008] a semiconductor layer of a first conductivity type;

[0009] Electrodes, including a drain electrode, a source electrode and a gate electrode;

[0010] a gate insulating film disposed between the gate electrode and the first conductive type semiconductor layer;

[0011] There is a Schottky barrier between the first portion of the source electrode and the first conductive type semiconductor layer, and the first portion of the source electrode is not in contact with the gate insulating film; the second portion of the source electrode forms an ohmic contact with the first conductive type semiconductor layer;

[0012] The gate electrode at least includes a metal material having a Schottky barrier with the semiconductor layer of the first conductivity type, and the metal material is in contact with a gate insulating film; or the gate electrode at least includes an electrode material of a second conductivity type, and the electrode material of the second conductivity type is in contact with a gate insulating film, wherein the conductivity types of the second conductivity type and the first conductivity type are different.

[0013] Preferably, the first conductivity type semiconductor layer is an n-type semiconductor layer.

[0014] Preferably, the width of the first portion of the source electrode from the gate insulating film is in the range of 3 nm to 400 nm.

[0015] Furthermore, the width of the first portion of the source electrode from the gate insulating film is in a range of 3 nm to 200 nm.

[0016] Preferably, when the first conductive type semiconductor layer is an n-type semiconductor layer, the work function of the metal material is greater than the work function of a corresponding material of the first conductive type semiconductor layer.

[0017] Furthermore, the metal material is Pt, Ni, Co, or Au.

[0018] Preferably, when the first conductivity type semiconductor layer is an n-type semiconductor layer, the second conductivity type electrode material is p-type conductive polysilicon.

[0019] Preferably, the drain electrode is formed on the first main surface of the first conductivity type semiconductor layer, and the source electrode is located on the second main surface side of the first conductivity type semiconductor layer.

[0020] Furthermore, the field effect transistor is a vertical MOSFET.

[0021] Furthermore, the vertical MOSFET is a planar gate MOSFET, a trench gate MOSFET, a shielded gate MOSFET, or a super junction MOSFET.

[0022] Preferably, the material of the semiconductor layer is silicon, silicon carbide, gallium nitride, gallium oxide, or tin oxide.

[0023] The present invention also provides a field effect transistor having:

[0024] A first semiconductor layer including an n-type semiconductor region;

[0025] A second semiconductor layer including an n-type semiconductor region and a high-resistance semiconductor region;

[0026] Electrodes, including a drain electrode, a source electrode and a gate electrode;

[0027] a gate insulating film, which is interposed between the gate electrode and the semiconductor layer;

[0028] The drain electrode is formed on a surface of the first semiconductor layer opposite to the second semiconductor layer;

[0029] The source electrode is formed on a surface of the second semiconductor layer opposite to the first semiconductor layer, a Schottky barrier exists between a portion of the source electrode and the n-type semiconductor region of the second semiconductor layer, a first portion of the source electrode is not in contact with the gate insulating film, and a second portion of the source electrode is in contact with the n-type semiconductor region of the second semiconductor layer to form an ohmic contact;

[0030] The high-resistance semiconductor region of the second semiconductor layer is disposed in a region close to a surface layer of the second semiconductor layer and is formed between the gate insulating film and a first portion of the source electrode;

[0031] The gate electrode at least includes a metal material having a Schottky barrier with the second semiconductor layer, and the metal material is in contact with the gate insulating film; or the gate electrode uses a p-type conductive electrode material, and the p-type conductive electrode material is in contact with the gate insulating film.

[0032] Preferably, the first portion of the source electrode contacts the n-type semiconductor region of the second semiconductor layer to form a Schottky barrier contact.

[0033] Preferably, the work function of the metal material is greater than the work function of the corresponding material of the semiconductor layer.

[0034] Preferably, the p-type conductive electrode material is p-type conductive polysilicon.

[0035] Preferably, the material of the semiconductor layer is gallium oxide, and the material of the high-resistance semiconductor region is nitrogen (N)-doped gallium oxide.

[0036] In view of the above invention contents, the present invention has the following beneficial effects:

[0037] The present invention introduces a metal material that can generate a Schottky barrier between the gate electrode and the semiconductor layer or a semiconductor material that can deplete the carriers in the semiconductor layer. Taking an n-channel enhancement MOSFET as an example, on the basis of the original use of the source electrode and the n-type semiconductor region to form a Schottky junction to generate depletion effect on the electron carriers of the n-type semiconductor region from one side, a Schottky gate or a p-type gate is introduced to generate depletion on the electron carriers of the n-type semiconductor region from the other side, thereby achieving the effect of double-side depletion. In this way, from the perspective of electrical performance, the on-state current capacity is maintained and the off-state leakage is further reduced, and it is also beneficial to the regulation of the turn-on voltage; from the perspective of process technology, the key width dimension requirements can be relaxed, the requirements for photolithography & etching technology and equipment can be reduced, the process window can be expanded, and the mass production yield can be improved.

[0038] The present invention further provides a trench MOS diode having:

[0039] An n-type semiconductor layer having a first main surface on one side and a second main surface on the other side opposite thereto, and having a groove, the groove opening inward from the first main surface of the n-type semiconductor layer;

[0040] a cathode electrode formed on the second main surface of the n-type semiconductor layer;

[0041] an anode electrode formed on the first main surface of the n-type semiconductor layer;

[0042] A trench MOS gate, which is buried in the trench and wrapped by the gate insulating film, is separated from the n-type semiconductor layer by the gate insulating film, and is in contact with the anode electrode;

[0043] The first portion of the anode electrode forms a Schottky contact with the first main surface of the n-type semiconductor layer, and the second portion of the anode electrode forms an ohmic contact with the first main surface of the n-type semiconductor layer;

[0044] The trench MOS gate at least includes a metal material having a Schottky barrier with the n-type semiconductor layer, and the metal material is in contact with the gate insulating film; or the trench MOS gate at least includes a p-type conductive electrode material, and the p-type conductive electrode material is in contact with the gate insulating film.

[0045] The width of the first portion of the anode electrode from the gate insulating film is in the range of 3 nm to 400 nm.

[0046] Preferably, the width of the first portion of the anode electrode from the gate insulating film is in the range of 3 nm to 200 nm.

[0047] The trench MOS diode of the present invention has the following beneficial effects:

[0048] Compared with the conventional trench MOS Schottky diode, the trench MOS diode of the present invention can further reduce the turn-on voltage and conduction loss when forward conducting; and can reduce the off-state leakage when reverse cutting off.

[0049] The present invention also provides an insulated gate bipolar transistor having:

[0050] p-type semiconductor layer;

[0051] an n-type semiconductor layer stacked on the p-type semiconductor layer;

[0052] An electrode including a collector, an emitter, and a gate electrode, wherein the collector is formed on a surface of the p-type semiconductor layer opposite to the n-type semiconductor layer;

[0053] a gate insulating film, which is interposed between the gate electrode and the n-type semiconductor layer;

[0054] There is a Schottky barrier between the first part of the emitter and the n-type semiconductor layer, the first part of the emitter is not in contact with the gate insulating film, and the second part of the emitter forms an ohmic contact with the n-type semiconductor layer;

[0055] The gate electrode at least includes a metal material having a Schottky barrier with the n-type semiconductor layer, and the metal material is in contact with the gate insulating film; or the gate electrode is made of a p-type conductive electrode material, and the p-type conductive electrode material is in contact with the gate insulating film.

[0056] Preferably, the first portion of the emitter contacts the n-type semiconductor layer to form a Schottky barrier contact.

[0057] Preferably, the width of the first portion of the emitter from the gate insulating film ranges from 3 nm to 400 nm.

[0058] Furthermore, the width of the first portion of the emitter from the gate insulating film ranges from 3 nm to 200 nm.

[0059] Preferably, the metal material is Pt, Ni, Au, or Co.

[0060] Preferably, the p-type conductive electrode material is p-type conductive polysilicon.

[0061] The insulated gate bipolar transistor of the present invention introduces a metal material capable of generating a Schottky barrier with the semiconductor layer or a p-type conductive electrode material capable of depleting the electron carriers in the semiconductor layer into the gate electrode, and introduces a Schottky gate or a p-type gate to deplete the electron carriers in the n-type semiconductor region, so that the off-state leakage can be further reduced in terms of electrical performance; and the process window can be expanded in terms of process technology, thereby improving the mass production yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] In order to more clearly illustrate the technical solution of the present invention, the following will briefly introduce the drawings required by the embodiments or prior art descriptions. Obviously, some of the drawings in the following description are only illustrations of some embodiments of the present invention, and the protection scope required by the present invention is not limited to the embodiments. For ordinary technicians in this field, other drawings can also be obtained based on these drawings without creative work.

[0063] Attached Figure 1 FIG. 1 is a vertical cross-sectional view of an embodiment of a conventional Schottky junction trench gate MOSFET.

[0064] Attached Figure 2 It is a vertical cross-sectional view of an embodiment of a trench gate MOSFET applied for by the applicant in patent application number 202310325051.0.

[0065] Attached Figure 3a FIG. 1 is a vertical cross-sectional view of a first example of a trench gate MOSFET according to an embodiment of the present invention.

[0066] Attached Figure 3b FIG. 1 is a vertical cross-sectional view of a second example of a trench gate MOSFET according to an embodiment of the present invention.

[0067] Attached Figure 3c FIG. 1 is a vertical cross-sectional view of a third example of a trench gate MOSFET according to an embodiment of the present invention.

[0068] Attached Figure 4a FIG. 1 is a vertical cross-sectional view of a first example of a planar gate MOSFET according to an embodiment of the present invention.

[0069] Attached Figure 4b It is a vertical cross-sectional view of a second example of a planar gate MOSFET according to an embodiment of the present invention.

[0070] Attached Figure 5a 1 is a vertical cross-sectional view of a first example of a shielded gate MOSFET according to an embodiment of the present invention.

[0071] Attached Figure 5bIt is a vertical cross-sectional view of a second example of a shielded gate MOSFET according to an embodiment of the present invention.

[0072] Attached Figure 5c It is a vertical cross-sectional view of a third example of a shielded gate MOSFET according to an embodiment of the present invention.

[0073] Attached Figure 5d It is a vertical cross-sectional view of a fourth example of a shielded gate MOSFET according to an embodiment of the present invention.

[0074] Attached Figure 5e It is a vertical cross-sectional view of a fifth example of a shielded gate MOSFET according to an embodiment of the present invention.

[0075] Attached Figure 5f 1 is a vertical cross-sectional view of a sixth example of a shielded gate MOSFET according to an embodiment of the present invention.

[0076] Attached Figure 5g 1 is a vertical cross-sectional view of a seventh example of a shielded gate MOSFET according to an embodiment of the present invention.

[0077] Attached Figure 6a It is a vertical cross-sectional view of a first example of a super junction MOSFET according to an embodiment of the present invention.

[0078] Attached Figure 6b It is a vertical cross-sectional view of a second example of a super junction MOSFET according to an embodiment of the present invention.

[0079] Attached Figure 7a It is a vertical cross-sectional view of a first example of a trench MOS diode according to an embodiment of the present invention.

[0080] Attached Figure 7b It is a vertical cross-sectional view of a second example of a trench MOS diode according to an embodiment of the present invention.

[0081] Attached Figure 8a It is a vertical cross-sectional view of a first example of an insulated gate bipolar transistor according to an embodiment of the present invention.

[0082] Attached Figure 8b It is a vertical cross-sectional view of a second example of an insulated gate bipolar transistor according to an embodiment of the present invention.

[0083] The technical features corresponding to the marks in the accompanying drawings are:

[0084] 11Drain electrode (collector)

[0085] 12 Source electrode (emitter)

[0086] 12a Ohmic source electrode (Ohmic emitter)

[0087] 12b Schottky source electrode (Schottky emitter)

[0088] 12c shield source electrode

[0089] 12d p-type polysilicon

[0090] 13 Gate electrode

[0091] 13a n-type gate electrode

[0092] 13b p-type gate electrode

[0093] 13c Schottky gate electrode

[0094] 21Semiconductor District

[0095] 21a n+ type semiconductor

[0096] 21b n-type semiconductor

[0097] 21c n+ type semiconductor

[0098] 211 First main surface

[0099] 212 Second main surface

[0100] 31a p+ type semiconductor

[0101] 31b p-type semiconductor

[0102] 41 High resistance semiconductor

[0103] 51a Gate insulating film

[0104] 51b Non-gate insulating film

[0105] 61 cathode electrode

[0106] 62 Anode electrode

[0107] 62a ohm anode

[0108] 62b Schottky anode

[0109] 63 Trench MOS Gate

[0110] 63a n-type gate

[0111] 63b p-type gate

[0112] 63c Schottky gate DETAILED DESCRIPTION

[0113] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present invention. However, it should be clear to those skilled in the art that the present invention may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, and methods are omitted to prevent unnecessary details from obstructing the description of the present invention.

[0114] Attached Figure 1 1 is a vertical cross-sectional view of an embodiment of a conventional Schottky junction trench gate MOSFET. The Schottky junction trench gate MOSFET comprises: a drain electrode 11, an n+ type semiconductor 21a, an n-type semiconductor 21b, and a trench in the n-type semiconductor 21b, a gate electrode 13 in the trench and wrapped by a gate insulating film 51a, a Schottky source electrode 12b in contact with the n-type semiconductor 21b to form a Schottky barrier, and a source electrode 12 thereon.

[0115] Attached Figure 1 In the Schottky junction trench gate MOSFET shown in FIG. 1 , due to the presence of the Schottky junction formed between the Schottky source electrode 12 b and the n-type semiconductor layer 21 b, when only a forward voltage is applied between the drain electrode 11 and the source electrode 12, the Schottky junction is reverse biased to widen the depletion region, so that a complete electronic conductive channel is not formed between the drain electrode 11 and the source electrode 12, and no current flows between the drain and the source. Based on this principle, the attached Figure 1 The Schottky junction trench gate MOSFET shown is a normally-off device.

[0116] When a positive voltage is applied between the gate electrode 13 and the source electrode 12, due to the presence of the Schottky barrier between the Schottky source electrode 12b and the n-type semiconductor 21b, a complete and high-concentration electron conduction channel cannot be formed between the drain electrode 11 and the Schottky source electrode 12b. At this time, even when a positive voltage is applied between the drain electrode 11 and the source electrode 12, the reverse-biased depletion layer of the Schottky barrier formed between the Schottky source electrode 12b and the n-type semiconductor 21b is widened, which inhibits the transport of electron carriers, so that only a small number of electron carriers between the drain and the source form current through the tunneling effect, resulting in poor on-state current conduction capacity of the existing Schottky junction trench gate MOSFET, and its on-state current is much smaller than the on-state current of the pn junction MOSFET under the same conditions, which has led to the Schottky junction trench gate MOSFET not being commercially available so far.

[0117] Attached Figure 2 202310325051.0 is a vertical cross-sectional view of an embodiment of a trench gate MOSFET applied for by the present applicant in the patent application number 202310325051.0. The trench gate MOSFET in this embodiment is in the attached Figure 1On the basis of the Schottky junction trench gate MOSFET shown in the figure, the Schottky source electrode 12b in contact with the n-type semiconductor 21b is changed to the ohmic source electrode 12a and the Schottky source electrode 12b. Figure 2 In the embodiment, the ohmic source electrode 12a forms an ohmic contact with the n-type semiconductor 21b, and the Schottky source electrode 12b forms a Schottky contact with the n-type semiconductor 21b.

[0118] Attached Figure 2 In the MOSFET shown, when the voltage V between the drain electrode 11 and the source electrode 12 DS =0 and the voltage V between the gate electrode 13 and the source electrode 12 GS = 0, the Schottky junction formed by the contact between the Schottky source electrode 12b and the n-type semiconductor 21b will deplete the electron carriers in the n-type semiconductor 21b between the gate insulating film 51a and the Schottky source electrode 12b. When the width of the n-type semiconductor 21b between the gate insulating film 51a and the Schottky source electrode 12b is between 3nm and 250nm, the attached Figure 2 The MOSFET shown can realize the normally-off function; when the voltage V between the drain electrode 11 and the source electrode 12 DS >0 and the voltage V between the gate electrode 13 and the source electrode 12 GS = 0, the Schottky junction formed by the contact between the Schottky source electrode 12b and the n-type semiconductor 21b in contact therewith is reverse biased, so that the depletion region continues to widen. At this time, the MOSFET is in the off state; when the voltage V between the drain electrode 11 and the source electrode 12 DS >0, and a voltage V is applied between the gate electrode 13 and the source electrode 12 GS >0, as V GS > increases, reaching the turn-on voltage V GS(th) When the turn-on voltage V GS(th) As a result, a high-concentration electron conduction channel is formed in the region of the n-type semiconductor 21b adjacent to the gate insulating film 51a. At this time, a current flows between the drain electrode 11 and the source electrode 12, and the device is turned on. Figure 2 The MOSFET shown is a normally-off device that can be designed to have a large current-carrying capability.

[0119] Attached Figure 3a1 is a vertical cross-sectional view of a first embodiment of a trench gate MOSFET according to an embodiment of the present invention. The MOSFET includes a drain electrode 11, an n+ type semiconductor 21a stacked on the drain electrode 11, an n- type semiconductor 21b stacked on the n+ type semiconductor 21a (the n+ type semiconductor 21a and the n- type semiconductor 21b are both semiconductor layers of the first conductivity type), a trench located in the n- type semiconductor 21b, a gate electrode 13 located in the trench and wrapped by a gate insulating film 51a, a semiconductor region 21 located between the gate insulating film 51a and the Schottky source electrode 12b (the semiconductor region 21 may be an n- type semiconductor). conductor 21b, which may also be a high-resistance semiconductor 41), a Schottky source electrode 12b forming a Schottky barrier contact with the n-type semiconductor 21b, an ohmic source electrode 12a forming an ohmic contact with the semiconductor region 21, and a source electrode 12 located thereon; wherein the gate electrode 13 includes a Schottky gate electrode 13c and an n-type gate electrode 13a, the n-type gate electrode 13a may be phosphorus-doped n-type conductive polysilicon; the Schottky gate electrode 13c is in contact with the gate insulating film 51a, and the Schottky gate electrode 13c is composed of a metal material.

[0120] Attached Figure 3a In the MOSFET shown in the figure, a Schottky gate electrode 13c with a Schottky barrier between the gate electrode 13 and the semiconductor region 21 is introduced. The MIS (metal insulator semiconductor) junction composed of the Schottky gate electrode 13c, the gate insulating film 51a and the semiconductor region 21 will deplete the electron carriers in the semiconductor region 21 between the gate insulating film 51a and the Schottky source electrode 12b. In addition, the Schottky junction composed of the Schottky source electrode 12b and the semiconductor region 21 will also deplete the electron carriers in the semiconductor region 21 between the gate insulating film 51a and the Schottky source electrode 12b. When the width of the Schottky source electrode 12b from the gate insulating film 51a is in the range of 3nm to 250nm, under the combined effect of these two depletion effects, the electron carriers in the semiconductor 21 between the gate insulating film 51a and the Schottky source electrode 12b are completely depleted, thereby blocking the electron conduction channel between the drain electrode 11 and the source electrode 12. Figure 3a The MOSFET shown is normally off and has a Figure 2 The MOSFET shown in the figure has the same width of the semiconductor region 21, and the electrical performance is better than that of the MOSFET shown in the figure. Figure 3a The MOSFET shown has lower off-state leakage. From the process technology, to make a normally-off MOSFET, the attached Figure 3a In the embodiment, the width of the semiconductor region 21 between the gate insulating film 51a and the Schottky source electrode 12b can be compared to Figure 2 The design is relatively wider, which can reduce the requirements for lithography & etching technology and equipment, expand the process window, and improve the yield of mass production.

[0121] Attached Figure 3b is a vertical cross-sectional view of a second embodiment of a trench gate MOSFET according to an embodiment of the present invention. Figure 3a The difference between the MOSFET shown in the figure is that the gate electrode 13 in this embodiment includes a P-type conductive electrode material (an electrode material of the second conductive type), that is, the gate electrode 13 includes a p-type gate electrode 13b, and the p-type gate electrode 13b can be a boron-doped p-type conductive polysilicon. The p-type gate electrode 13b will also have a depletion effect on the electron carriers in the semiconductor region 21. In addition, the Schottky junction formed by the Schottky source electrode 12b and the semiconductor region 21 will also have a depletion effect on the electron carriers in the semiconductor region 21 located between the gate insulating film 51a and the Schottky source electrode 12b. When the width of the Schottky source electrode 12b from the gate insulating film 51a ranges from 3nm to 250nm, under the combined effect of these two depletion effects, the electron carriers in the semiconductor 21 located between the gate insulating film 51a and the Schottky source electrode 12b are completely depleted, thereby blocking the electron conduction channel between the drain electrode 11 and the source electrode 12, so that the attached Figure 3b The MOSFET shown is normally off and has a Figure 2 The MOSFET shown in the figure has the same width of the semiconductor region 21, and the electrical performance is better than that of the MOSFET shown in the figure. Figure 3a The MOSFET shown has lower off-state leakage. From the process technology, to make a normally-off MOSFET, the attached Figure 3b In the embodiment, the width of the semiconductor 21 between the gate insulating film 51a and the Schottky source electrode 12b can be compared to Figure 2 The design is relatively wider, which can reduce the requirements for lithography & etching technology and equipment, expand the process window, and improve the yield of mass production.

[0122] Attached Figure 3c FIG. 1 is a vertical cross-sectional view of a third example of a trench gate MOSFET according to an embodiment of the present invention. Figure 3c The MOSFET shown is in the attached Figure 3a On the basis of the MOSFET structure shown, an n+ type semiconductor 21c is added between the semiconductor region 21 and the ohmic source electrode 12a. Such a design can make the ohmic contact effect better and reduce the contact resistance between the ohmic source electrode 12a and the semiconductor.

[0123] Attached Figure 4a1 is a vertical cross-sectional view of a first embodiment of a planar gate MOSFET according to an embodiment of the present invention. The MOSFET comprises a drain electrode 11, an n+ type semiconductor 21a, an n- type semiconductor 21b and a semiconductor region 21, a Schottky source electrode 12b, an ohmic source electrode 12a and a source electrode 12 thereon, a gate insulating film 51a and a gate electrode 13 thereon, the gate electrode 13 comprising a Schottky gate electrode 13c, and the Schottky gate electrode 13c is composed of a metal material.

[0124] Attached Figure 4b is a vertical cross-sectional view of a second embodiment of a planar gate MOSFET according to an embodiment of the present invention. Figure 4a The difference of the MOSFET shown is that the gate electrode 13 in this embodiment includes a P-type conductive electrode material, that is, the gate electrode 13 includes a p-type gate electrode 13 b, and the p-type gate electrode 13 b can be boron-doped p-type conductive polysilicon.

[0125] For the attached Figure 4a and attached Figure 4b The MOSFET shown in the figure can also be made into a normally-off device by the joint depletion effect of the gate electrode 13 and the Schottky source electrode 12b on the electron carriers in the semiconductor region 21. It has a large on-state current carrying capacity and a low off-state leakage.

[0126] Attached Figure 5a FIG. 1 is a vertical cross-sectional view of a first example of a shielded gate MOSFET according to an embodiment of the present invention. Figure 5a The MOSFET shown is a top-bottom gate structure, having: a drain electrode 11, an n+ type semiconductor 21a, an n-type semiconductor 21b, a semiconductor region 21 (the semiconductor region 21 may be an n-type semiconductor 21b or a high-resistance semiconductor 41), a trench in the n-type semiconductor 21b, a gate electrode 13 and a shielding source electrode 12c in the trench and wrapped by a gate insulating film 51a, a Schottky source electrode 12b forming a Schottky barrier contact with the n-type semiconductor 21b, an ohmic source electrode 12a forming an ohmic contact with the semiconductor region 21, and a source electrode 12 thereon. The gate electrode 13 includes a Schottky gate electrode 13c and an n-type gate electrode 13a, the n-type gate electrode 13a may be phosphorus-doped n-type conductive polysilicon; the Schottky gate electrode 13c is composed of a metal material.

[0127] Attached Figure 5b FIG. 2 is a vertical cross-sectional view of a second embodiment of a shielded gate MOSFET according to an embodiment of the present invention. Figure 5aThe difference of the MOSFET shown is that, in this embodiment, the gate electrode 13 includes a P-type conductive electrode material, that is, the gate electrode 13 includes a p-type gate electrode 13b, and the p-type gate electrode 13b can be boron-doped p-type conductive polysilicon.

[0128] Attached Figure 5c FIG. 2 is a vertical cross-sectional view of a third example of a shielded gate MOSFET according to an embodiment of the present invention. Figure 5c The MOSFET shown is a shielded gate MOSFET with left and right split gate structures. Figure 5a Based on the shielded gate MOSFET with upper and lower gate structures shown, the structure of the shielded gate area is designed and adjusted.

[0129] Attached Figure 5d FIG. 4 is a vertical cross-sectional view of a fourth embodiment of a shielded gate MOSFET according to an embodiment of the present invention. The MOSFET in this embodiment is a shielded gate MOSFET with a left-right split gate structure. Figure 5c The difference between the shielded gate MOSFET with the left and right split-gate structure shown is that, in this embodiment, the gate electrode 13 includes a P-type conductive electrode material, that is, the gate electrode 13 includes a p-type gate electrode 13b, and the p-type gate electrode 13b can be boron-doped p-type conductive polysilicon.

[0130] Attached Figure 5e FIG. 2 is a vertical cross-sectional view of a fifth example of a shielded gate MOSFET according to an embodiment of the present invention. Figure 5e The MOSFET shown is another shielded gate MOSFET with left and right split gate structure. Figure 5c Based on the shielded gate MOSFET with left and right split gate structure shown, the structure of the shielded gate area is designed and adjusted.

[0131] Attached Figure 5f FIG. 2 is a vertical cross-sectional view of a sixth example of a shielded gate MOSFET according to an embodiment of the present invention. Figure 5e The MOSFET shown in the figure is another shielded gate MOSFET with left and right split gate structures. The MOSFET in this embodiment is similar to the Figure 5e The difference of the MOSFET shown is that the gate electrode 13 in this embodiment includes a P-type conductive electrode material, that is, the gate electrode 13 includes a p-type gate electrode 13 b, and the p-type gate electrode 13 b can be boron-doped p-type conductive polysilicon.

[0132] Attached Figure 5g FIG. 2 is a vertical cross-sectional view of a seventh example of a shielded gate MOSFET according to an embodiment of the present invention. Figure 5gThe MOSFET shown has: a drain electrode 11, an n+ type semiconductor 21a in contact with the drain electrode 11, an n-type semiconductor 21b, a semiconductor region 21 (the semiconductor region 21 can be an n-type semiconductor 21b or a high-resistance semiconductor 41), an n+ type semiconductor 21c located on the semiconductor region 21, and a groove located in the n-type semiconductor 21b, a gate electrode 13 and a shielding source electrode 12c located in the groove and wrapped by a gate insulating film 51a, a Schottky source electrode 12b forming a Schottky barrier contact with the n-type semiconductor 21b, an ohmic source electrode 12a located thereon forming an ohmic contact with the n+ type semiconductor 21c, and a source electrode 12 located thereon; wherein the gate electrode 13 includes a Schottky gate electrode 13c and an n-type gate electrode 13a, the n-type gate electrode can be phosphorus-doped n-type conductive polysilicon, and the Schottky gate electrode 13c is composed of a metal material.

[0133] Attached Figure 5g The MOSFET shown is in the attached Figure 5a On the basis of the MOSFET shown, the structural design of the source electrode region is adjusted so that the ohmic source electrode 12a is not in contact with the gate insulating film 51a. This structural design can also achieve the function of reducing off-state leakage.

[0134] Attachment Figures 5a to 5g In the shielded gate MOSFET shown, whether the gate electrode 13 is a Schottky gate electrode 13c or a p-type gate electrode 13b, the gate electrode 13 and the Schottky source electrode 12b can jointly deplete the electron carriers in the semiconductor region 21 (the semiconductor region 21 can be an n-type semiconductor 21b or a high-resistance semiconductor 41) to achieve a better normally-off effect and smaller off-state leakage; in addition, the requirements for key dimensions in the process technology, such as the width of the semiconductor region 21, can be relaxed, the process window can be expanded, and the process yield can be improved.

[0135] For the attached Figures 5a to 5g For the shielded gate MOSFET shown, when the work function of the metal material used for the Schottky source electrode 12b and the Schottky gate electrode 13c is higher, the width of the semiconductor region 21 is relatively wider while maintaining the normally-off function. For example, metal materials with high work functions such as Pt, Ni, Au, Co, Cu, and Fe can be used.

[0136] Attached Figure 6a FIG. 1 is a vertical cross-sectional view of a first example of a super junction MOSFET according to an embodiment of the present invention. Figure 6aThe superjunction MOSFET shown has: a drain electrode 11, an n+ type semiconductor 21a, an n- type semiconductor 21b, a semiconductor region 21 (the semiconductor region 21 can be an n-type semiconductor 21b or a high-resistance semiconductor 41), a deep trench located in the n-type semiconductor 21b and a p-type polysilicon 12d located in the deep trench, a Schottky source electrode 12b, an ohmic source electrode 12a and a source electrode 12, a gate insulating film 51a and a Schottky gate electrode 13c located thereon, and the Schottky gate electrode 13c is composed of a metal material.

[0137] Attached Figure 6b 2 is a vertical cross-sectional view of a second embodiment of a super junction MOSFET according to an embodiment of the present invention. Figure 6a The difference of the shown super junction MOSFET is that the gate electrode 13 in this embodiment includes a P-type conductive electrode material, that is, the gate electrode 13 includes a p-type gate electrode 13 b.

[0138] Attachment Figure 6a and attached Figure 6b The superjunction MOSFET shown, whether using a Schottky gate electrode 13c or a p-type gate electrode 13b, can achieve a better normally-off effect and smaller off-state leakage by virtue of the joint depletion effect of the gate electrode 13 and the Schottky source electrode 12b on the electron carriers in the semiconductor region 21 (the semiconductor region 21 can be an n-type semiconductor 21b or a high-resistance semiconductor 41); in addition, the requirements for key dimensions in the process technology, such as the width of the semiconductor region 21, can be relaxed, the process window can be expanded, and the process yield can be improved.

[0139] Attached Figure 7a: is a vertical cross-sectional view of the first embodiment of the trench MOS diode involved in the embodiment of the present invention. It includes: a cathode electrode 61, an n-type semiconductor layer (including an n+ type semiconductor 21a and an n-type semiconductor 21b), a semiconductor region 21 (the semiconductor region 21 can be an n-type semiconductor or a high-resistance semiconductor), a trench located in the n-type semiconductor 21b, a trench MOS gate 63 located in the trench and wrapped by a gate insulating film 51a, a Schottky anode 62b in contact with the n-type semiconductor 21b to form a Schottky barrier contact, an ohmic anode 62a in contact with the semiconductor region 21 to form an ohmic contact, and an anode electrode 62 located thereon, wherein the trench MOS gate 63 is electrically connected to the anode electrode 62. Among them, the trench MOS gate 63 of the n-type semiconductor 21b includes an n-type gate 63a and a Schottky gate 63c, the n-type gate 63a can be n-type conductive polysilicon, the Schottky gate 63c is in contact with the gate insulating film 51a, and the Schottky gate electrode 63c is composed of a metal material. In this embodiment, the n-type semiconductor layer has a first main surface 211 on one side and a second main surface 212 on the other side opposite thereto, and the trench opens inward from the first main surface 211 of the n-type semiconductor layer.

[0140] Attached Figure 7a In the trench MOS diode shown, when a positive voltage is applied between the anode electrode 62 and the cathode electrode 61, a current will flow between the anode electrode 62 and the cathode electrode 61, and the diode is forward-conducted. There are two paths for the current: the first current path is along the anode electrode 62—ohmic anode 62a—semiconductor region 21—n-type semiconductor 21b—n+ type semiconductor 21a—cathode electrode 61; the second current path is along the anode electrode 62—Schottky anode 62b—n-type semiconductor 21b—n+ type semiconductor 21a—cathode electrode 61. In the first current path, there is no contact barrier between the ohmic anode 62a and the semiconductor region 21; in the second current path, there is a Schottky barrier between the Schottky anode 62b and the n-type semiconductor 21b; when the diode is forward-conducted, since the first current path has relatively less obstruction and requires a lower turn-on voltage than the second current path, the current flows preferentially through the first current path. Compared with the traditional trench MOS Schottky diode, it is obvious that the trench MOS diode based on the present invention has lower turn-on voltage and conduction loss.

[0141] Attached Figure 7aIn the trench MOS diode shown, when a reverse voltage is applied between the anode electrode 62 and the cathode electrode 61, there are two types of depletion effects on electron carriers: the first type is that the Schottky barrier formed by the Schottky anode 62b, the n-type semiconductor 21b and the semiconductor region 21 is reversely biased and widened, which produces a longitudinal depletion effect on the electron carriers of the n-type semiconductor 21b and a lateral depletion effect on the electron carriers in the semiconductor region 21; the second type is that the trench MOS gate 63 produces a lateral depletion effect on the electron carriers in the semiconductor region 21. Under the combined effect of these two types of depletion effects, only a small leakage current passes between the cathode electrode 61 and the anode electrode 62, and the diode is reversely cut off.

[0142] Attached Figure 7b FIG. 2 is a vertical cross-sectional view of a second embodiment of a trench MOS diode according to an embodiment of the present invention. Figure 7a The difference of the trench MOS diode shown is that the trench MOS gate 63 in this embodiment includes a P-type conductive electrode material, that is, the trench MOS gate 63 includes a p-type gate 63b. When forward conducting, there are also two current paths, and compared with the traditional trench MOS Schottky diode, there is also a relatively lower turn-on voltage and conduction loss.

[0143] Attached Figure 8a : is a vertical cross-sectional view of the first embodiment of the insulated gate bipolar transistor involved in the embodiment of the present invention. It has: a collector 11, a p+ type semiconductor 31a, an n+ type semiconductor 21a, an n-type semiconductor 21b, a semiconductor region 21 (the semiconductor region 21 can be an n-type semiconductor 21b or a high-resistance semiconductor 41), a trench located in the n-type semiconductor 21b, a gate electrode 13 located in the trench and wrapped by a gate insulating film, a Schottky emitter 12b that contacts the n-type semiconductor 21b to form a Schottky barrier contact, an ohmic emitter 12a that contacts the n-type semiconductor 21b to form an ohmic contact, and an emitter 12 located thereon. Among them, the gate electrode 13 includes a Schottky gate electrode 13c and an n-type gate electrode 13a, and the Schottky gate electrode 13c is composed of a metal material.

[0144] In the attached Figure 8aIn the insulated gate bipolar transistor shown in the figure, a Schottky gate electrode 13c with a Schottky barrier between the gate electrode 13 and the semiconductor region 21 is introduced. The MIS (metal insulator semiconductor) junction composed of the Schottky gate electrode 13c, the gate insulating film 51a and the semiconductor region 21 will deplete the electron carriers in the semiconductor 21 between the gate insulating film 51a and the Schottky emitter 12b. In addition, the Schottky junction composed of the Schottky emitter 12b and the semiconductor region 21 will also deplete the electron carriers in the semiconductor 21 between the gate insulating film 51a and the Schottky source. The electron carriers in the semiconductor region 21 between the electrodes 12b produce a depletion effect. When the width range of the Schottky emitter 12b from the gate insulating film 51a is between 3nm and 250nm, under the combined effect of these two depletion effects, the electron carriers in the semiconductor region 21 between the gate insulating film 51a and the Schottky emitter 12b are completely depleted, thereby blocking the electron carrier conduction channel between the collector 11 and the emitter 12. Such a design through the combined effect of the two depletion effects can reduce the off-state leakage of the device.

[0145] Attached Figure 8b 2 is a vertical cross-sectional view of a second embodiment of an insulated gate bipolar transistor according to an embodiment of the present invention. Figure 8a The difference between the insulated gate bipolar transistor shown is that, in this embodiment, the gate electrode 13 includes a P-type conductive electrode material, that is, the electrode 13 includes a p-type gate electrode 13b, and the p-type gate electrode 13b can be boron-doped p-type conductive polysilicon. The p-type gate electrode 13b will also have a depletion effect on the electron carriers in the semiconductor region 21. In addition, the Schottky junction formed by the Schottky emitter 12b and the semiconductor region 21 will also have a depletion effect on the electron carriers in the semiconductor region 21 located between the gate insulating film 51a and the Schottky emitter 12b. When the width range of the Schottky emitter 12b from the gate insulating film 51a is between 3nm and 250nm, under the combined action of these two depletion effects, the carriers in the semiconductor region 21 are completely depleted, thereby blocking the electron carrier conduction channel between the collector 11 and the emitter 12. The design of the combined action of the two depletion effects can reduce the off-state leakage of the device.

[0146] The MOSFETs shown in the various embodiments of the present invention are all n-channel MOSFETs based on the participation of electron carriers in conduction. The essence of the technical solution of the present invention is also applicable to p-channel MOSFETs based on the participation of hole carriers in conduction.

[0147] In the present invention, there is no specific limitation on the material of the semiconductor. The material of the semiconductor may be a single element semiconductor such as germanium, silicon, etc.; the material of the semiconductor may be a compound semiconductor such as silicon carbide, gallium nitride, gallium oxide, tin oxide, etc.

[0148] It should be understood that the embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the essence and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. A field effect transistor, comprising: a semiconductor layer of a first conductivity type; Electrodes, including a drain electrode, a source electrode and a gate electrode; a gate insulating film disposed between the gate electrode and the first conductive type semiconductor layer; Features: There is a Schottky barrier between the first portion of the source electrode and the first conductive type semiconductor layer, and the first portion of the source electrode is not in contact with the gate insulating film; the second portion of the source electrode forms an ohmic contact with the first conductive type semiconductor layer; The gate electrode at least includes a metal material having a Schottky barrier with the semiconductor layer of the first conductivity type, and the metal material is in contact with the gate insulating film; or the gate electrode at least includes an electrode material of the second conductivity type, and the electrode material of the second conductivity type is in contact with the gate insulating film, wherein the conductivity types of the second conductivity type and the first conductivity type are different.

2. The field effect transistor according to claim 1, characterized in that The first conductivity type is n-type, and the second conductivity type is p-type.

3. The field effect transistor according to claim 1, characterized in that: The first portion of the source electrode contacts the first conductivity type semiconductor layer to form a Schottky contact.

4. The field effect transistor according to claim 1, characterized in that The width of the first portion of the source electrode from the gate insulating film is in the range of 3 nm to 400 nm.

5. The field effect transistor according to claim 1, characterized in that: The width of the first portion of the source electrode from the gate insulating film is in the range of 3 nm to 200 nm.

6. The field effect transistor according to claim 1, characterized in that The field effect transistor is a horizontal semiconductor element or a vertical semiconductor element.

7. A trench MOS diode, comprising: An n-type semiconductor layer having a first main surface on one side and a second main surface on the other side opposite thereto, wherein the n-type semiconductor layer is provided with a groove, and the groove opens inward from the first main surface of the n-type semiconductor layer; a cathode electrode formed on the second main surface of the n-type semiconductor layer; an anode electrode formed on the first main surface of the n-type semiconductor layer; A trench MOS gate, which is buried in the trench and wrapped by a gate insulating film, wherein the trench MOS gate and the n-type semiconductor layer are separated by the gate insulating film and the trench MOS gate is in contact with the anode electrode; Features: The first portion of the anode electrode forms a Schottky contact with the first main surface of the n-type semiconductor layer, and the second portion of the anode electrode forms an ohmic contact with the first main surface of the n-type semiconductor layer; The trench MOS gate at least includes a metal material having a Schottky barrier with the n-type semiconductor layer, and the metal material is in contact with the gate insulating film; or the trench MOS gate at least includes a p-type conductive electrode material, and the p-type conductive electrode material is in contact with the gate insulating film; The width of the first portion of the anode electrode from the gate insulating film is in the range of 3 nm to 400 nm.

8. The trench MOS diode according to claim 7, characterized in that: The width of the first portion of the anode electrode from the gate insulating film is in the range of 3 nm to 200 nm.

9. An insulated gate bipolar transistor, comprising: p-type semiconductor layer; an n-type semiconductor layer stacked on the p-type semiconductor layer; An electrode including a collector, an emitter, and a gate electrode, wherein the collector is formed on a surface of the p-type semiconductor layer opposite to the n-type semiconductor layer; a gate insulating film, which is interposed between the gate electrode and the n-type semiconductor layer; Features: There is a Schottky barrier between the first part of the emitter and the n-type semiconductor layer, the first part of the emitter is not in contact with the gate insulating film, and the second part of the emitter forms an ohmic contact with the n-type semiconductor layer; The gate electrode at least includes a metal material having a Schottky barrier with the n-type semiconductor layer, and the metal material is in contact with the gate insulating film; or the gate electrode is made of a p-type conductive electrode material, and the p-type conductive electrode material is in contact with the gate insulating film.

10. The insulated gate bipolar transistor according to claim 9, characterized in that: The first portion of the emitter contacts the n-type semiconductor layer to form a Schottky contact.

11. The insulated gate bipolar transistor according to claim 9, characterized in that: The width range of the first portion of the emission from the gate insulating film is between 3nm and 400nm.

12. The insulated gate bipolar transistor according to claim 9, characterized in that: The width range of the first portion of the emission from the gate insulating film is between 3nm and 200nm.

13. A field effect transistor comprising: A first semiconductor layer including an n-type semiconductor region; A second semiconductor layer including an n-type semiconductor region and a high-resistance semiconductor region; Electrodes, including a drain electrode, a source electrode and a gate electrode; a gate insulating film, which is interposed between the gate electrode and the semiconductor layer; Features: The drain electrode is formed on a surface of the first semiconductor layer opposite to the second semiconductor layer; The source electrode is formed on a surface of the second semiconductor layer opposite to the first semiconductor layer, a Schottky barrier exists between a first portion of the source electrode and the n-type semiconductor region of the second semiconductor layer, and the first portion of the source electrode is not in contact with the gate insulating film; and a second portion of the source electrode is in contact with the n-type semiconductor region of the second semiconductor layer to form an ohmic contact; The high-resistance semiconductor region of the second semiconductor layer is disposed in a region close to a surface layer of the second semiconductor layer and is formed between the gate insulating film and a first portion of the source electrode; The gate electrode at least includes a metal material having a Schottky barrier with the second semiconductor layer, and the metal material is in contact with the gate insulating film; or the gate electrode is made of a p-type conductive electrode material, and the p-type conductive electrode material is in contact with the gate insulating film.

14. The field effect transistor according to claim 13, characterized in that: A first portion of the source electrode contacts the n-type semiconductor region of the second semiconductor layer to form a Schottky barrier.

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