Semiconductor device

Abstract

A semiconductor device may include: a substrate including an active pattern; a channel pattern on the active pattern and including a plurality of semiconductor patterns, the plurality of semiconductor patterns being vertically stacked in a manner spaced apart from each other; a gate electrode on the plurality of semiconductor patterns; a gate contact electrically connected to the gate electrode; a first metal layer on the gate contact and including a first conductive path and a first interconnect pattern on the first conductive path; a second metal layer on the first metal layer and including a second conductive via and a second interconnect pattern on the second conductive via; and a diffusion prevention pattern between the first interconnection pattern and the second conductive path. A height of a bottom surface of the diffusion prevention pattern may be lower than a height of a topmost surface of the first interconnect pattern.

Description

Technical Field

[0001] The present disclosure relates generally to semiconductor devices, and in particular, to a semiconductor device including a field effect transistor. Background Art

[0002] Semiconductor devices often include integrated circuits composed of metal oxide semiconductor field effect transistors (MOSFETs). In order to meet the increasing demand for semiconductor devices with small pattern sizes and reduced design rules, MOSFETs have been actively reduced in size. The scaling down of MOSFETs may cause degradation of the operating characteristics of semiconductor devices. Various studies are being conducted to overcome the technical limitations associated with the scaling down of semiconductor devices and to achieve high-performance semiconductor devices. Summary of the invention

[0003] Embodiments of the inventive concept provide a semiconductor device having improved reliability.

[0004] Embodiments of the inventive concept provide a semiconductor device having improved electrical characteristics.

[0005] According to an embodiment of the inventive concept, a semiconductor device may include: a substrate including an active pattern; a channel pattern located on the active pattern and including a plurality of semiconductor patterns, the plurality of semiconductor patterns being stacked in a vertical direction perpendicular to an upper surface of the substrate and spaced apart from each other in the vertical direction; a gate electrode located on the plurality of semiconductor patterns; a gate contact electrically connected to the gate electrode; a first metal layer located on the gate contact and including a first conductive path and a first interconnection pattern located on the first conductive path; a second metal layer located on the first metal layer and including a second conductive path and a second interconnection pattern located on the second conductive path; and a diffusion prevention pattern located between the first interconnection pattern and the second conductive path. A bottom surface of the diffusion prevention pattern may have a height lower than a height of a topmost surface of the first interconnection pattern.

[0006] According to an embodiment of the inventive concept, a semiconductor device may include: a substrate including an active pattern; a channel pattern located on the active pattern and including a plurality of semiconductor patterns, the plurality of semiconductor patterns being stacked in a vertical direction perpendicular to an upper surface of the substrate and spaced apart from each other in the vertical direction; a source / drain pattern connected to the channel pattern; a gate electrode located on the plurality of semiconductor patterns; an active contact electrically connected to the source / drain pattern; a metal interconnect structure located on the active contact and including a conductive path and an interconnect pattern located on the conductive path; and a diffusion prevention pattern located between the interconnect pattern and the conductive path. A top surface of the diffusion prevention pattern may have a height different from a bottommost surface of the interconnect pattern in contact with the diffusion prevention pattern, and the diffusion prevention pattern may include ruthenium oxide.

[0007] According to an embodiment of the inventive concept, a semiconductor device may include: a substrate including an active pattern; a device isolation layer defining the active pattern; a channel pattern located on the active pattern and including a plurality of semiconductor patterns, the plurality of semiconductor patterns being stacked in a vertical direction perpendicular to an upper surface of the substrate and spaced apart from each other in the vertical direction; a gate electrode located on the plurality of semiconductor patterns; a gate insulating layer located between the gate electrode and an adjacent semiconductor pattern in the semiconductor pattern; a gate contact electrically connected to the gate electrode; a first metal layer located on the substrate and including a first conductive path, a first interconnection pattern located on the first conductive path, and a first path insulating layer surrounding the first conductive path (i.e., extending around it); a second metal layer disposed on the first metal layer and including a second conductive path and a second interconnection pattern located on the second conductive path; a diffusion prevention pattern located between the first conductive path and the first interconnection pattern; and a selection barrier pattern surrounding a portion of a bottom surface of the first interconnection pattern and a side surface of the first interconnection pattern. The side surface of the diffusion prevention pattern may contact the first interconnection pattern, the selection barrier pattern, and the first path insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, are presented by way of example only and not limitation, wherein like reference numerals, when used, designate corresponding elements throughout the several views, and wherein:

[0009] Figures 1 to 3 is a conceptual top view illustrating a logic unit of a semiconductor device according to an embodiment of the inventive concept;

[0010] Figure 4is a top view illustrating a semiconductor device according to an embodiment of the inventive concept;

[0011] FIG. 5A to FIG. 5D Along the Figure 4 sectional views taken along lines A-A', B-B', CC' and D-D';

[0012] FIG. 6A to FIG. 6D are enlarged cross-sectional views of embodiments according to the inventive concept, each of which illustrates Figure 5C part "P";

[0013] FIG. 7A to FIG. 7C is a diagram illustrating the manufacturing process of one or more embodiments according to the present inventive concept Fig. 6A A cross-sectional view of an intermediate process in an example method of a semiconductor device;

[0014] FIG. 8A to FIG. 8C is a diagram illustrating the manufacturing process of one or more embodiments according to the present inventive concept Figure 6B A cross-sectional view of an intermediate process in an example method of a semiconductor device;

[0015] 9A to 9D is a diagram illustrating the manufacturing process of one or more embodiments according to the present inventive concept Figure 6C A cross-sectional view of an intermediate process in an example method of a semiconductor device; and

[0016] FIG. 10A to FIG. 10C is a diagram illustrating the manufacturing process of one or more embodiments according to the present inventive concept Fig.6D A cross-sectional view of an intermediate process in an example method of a semiconductor device. DETAILED DESCRIPTION

[0017] Figures 1 to 3 is a conceptual top view illustrating a logic cell of a semiconductor device according to an embodiment of the inventive concept.

[0018] refer to Figure 1 , a single height cell SHC can be provided. In detail, the first power line M1_R1 and the second power line M1_R2 can be disposed on the substrate 100. The first power line M1_R1 can be a conductive path provided with a source voltage (VSS) (e.g., a ground voltage). The second power line M1_R2 can be a conductive path provided with a drain voltage (VDD) (e.g., a power supply voltage). Each of the first power line M1_R1 and the second power line M1_R2 can extend in a second direction D2 parallel to the upper surface of the substrate 100, and can be separated from each other in a first direction parallel to the upper surface of the substrate 100 and perpendicular to the second direction D2.

[0019] The single height cell SHC may be defined between the first power line M1_R1 and the second power line M1_R2. The single height cell SHC may include a first active region AR1 and a second active region AR2. One of the first active region AR1 and the second active region AR2 may be a p-channel metal oxide semiconductor field effect transistor (PMOSFET) region, and the other of the first active region AR1 and the second active region AR2 may be an n-channel metal oxide semiconductor field effect transistor (NMOSFET) region. In other words, the single height cell SHC may have a complementary metal oxide semiconductor (CMOS) structure disposed between the first power line M1_R1 and the second power line M1_R2.

[0020] Each of the first active region AR1 and the second active region AR2 may have a first width W1 in the first direction D1. The length of the single height cell SHC in the first direction D1 may be defined as a first height HE1. The first height HE1 may be substantially equal to a distance (eg, a pitch) between the first power line M1_R1 and the second power line M1_R2.

[0021] The single height cell SHC may constitute a single logic unit. In this specification, a logic unit may mean a logic device configured to perform a specific function (e.g., AND, OR, XOR, XNOR, inverter, etc.). In other words, a logic unit may include transistors constituting the logic device and interconnection lines connecting the transistors to each other.

[0022] refer to Figure 2 , a double height cell DHC may be provided. In detail, a first power line M1_R1, a second power line M1_R2, and a third power line M1_R3 may be disposed on the substrate 100. The first power line M1_R1 may be disposed between the second power line M1_R2 and the third power line M1_R3. The third power line M1_R3 may be a conductive path provided with a source voltage (VSS). Each of the first power line M1_R1, the second power line M1_R2, and the third power line M1_R3 may extend in the second direction D2 and may be separated from each other in the first direction D1.

[0023] The double height cell DHC may be defined between the second power line M1_R2 and the third power line M1_R3 The double height cell DHC may include a pair of first active regions AR1 and a pair of second active regions AR2.

[0024] One of the second active regions AR2 may be adjacent to the second power line M1_R2. Another of the second active regions AR2 may be adjacent to the third power line M1_R3. The paired first active regions AR1 may be adjacent to the first power line M1_R1. When viewed in a top view, the first power line M1_R1 may be disposed between the paired first active regions AR1.

[0025] The length of the double height unit DHC in the first direction D1 may be defined as a second height HE2. The second height HE2 may be Figure 1 The paired first active regions AR1 of the double-height cell DHC may be combined to be used as a single active region.

[0026] In an embodiment, Figure 2 The double height cell DHC shown may be defined as a multi-height cell. Although not shown, the multi-height cell may include a triple height (or higher) cell having a cell height approximately three times that of the single height cell SHC.

[0027] refer to Figure 3 , the first single height cell SHC1, the second single height cell SHC2, and the double height cell DHC may be two-dimensionally arranged on the substrate 100. The first single height cell SHC1 may be disposed between the first power line M1_R1 and the second power line M1_R2. The second single height cell SHC2 may be disposed between the first power line M1_R1 and the third power line M1_R3. The second single height cell SHC2 may be adjacent to the first single height cell SHC1 in the first direction D1.

[0028] The double height cell DHC may be disposed between the second power line M1_R2 and the third power line M1_R3 . The double height cell DHC may be adjacent to the first and second single height cells SHC1 and SHC2 in the second direction D2 .

[0029] A partition structure DB may be provided between the first single height cell SHC1 and the double height cell DHC and between the second single height cell SHC2 and the double height cell DHC. An active region of the double height cell DHC may be electrically separated from an active region of each of the first single height cell SHC1 and the second single height cell SHC2 by the partition structure DB.

[0030] Figure 4 is a top view illustrating at least a portion of an example semiconductor device according to an embodiment of the inventive concept. FIG. 5A to FIG. 5D Along the Figure 4 Cross-sectional views taken along lines AA', BB', CC' and DD'. FIG. 6A to FIG. 6Dare enlarged cross-sectional views of embodiments according to the inventive concept, each of which illustrates Figure 5C part "P". Figure 4 and FIG. 5A to FIG. 5D The semiconductor device can be Figure 1 This is an example of a single-height unit SHC, but the embodiment is not limited thereto.

[0031] refer to Figure 4 and FIG. 5A to FIG. 5D , a single height cell SHC may be disposed on the substrate 100. A logic transistor constituting a logic circuit may be disposed on the single height cell SHC. The substrate 100 may be a semiconductor substrate formed of or including silicon, germanium, silicon germanium, a compound semiconductor material, etc., but the embodiment is not limited thereto. In an embodiment, the substrate 100 may be a silicon wafer.

[0032] The substrate 100 may include a first active region AR1 and a second active region AR2. Each of the first active region AR1 and the second active region AR2 may extend in the second direction D2. In an embodiment, the first active region AR1 may be an NMOSFET region, and the second active region AR2 may be a PMOSFET region.

[0033] The first active pattern AP1 and the second active pattern AP2 may be defined by a trench TR formed in an upper portion of the substrate 100 and extending into the substrate 100 in the third direction D3. The first active pattern AP1 may be disposed on the first active region AR1, and the second active pattern AP2 may be disposed on the second active region AR2. The first active pattern AP1 and the second active pattern AP2 may extend in the second direction D2. Each of the first active pattern AP1 and the second active pattern AP2 may be a vertical protrusion of the substrate 100.

[0034] The device isolation layer ST may be disposed on the substrate 100. The device isolation layer ST may be disposed to fill the trench TR. The term "fill" (or "filling", "filled" or similar terms) as may be used herein is intended to refer broadly to completely filling a defined space (e.g., trench TR) or partially filling a defined space; that is, the defined space does not need to be completely filled, but may, for example, be partially filled or have a void or other space in the entire space. The device isolation layer ST may include a silicon oxide layer. The device isolation layer ST may not cover the first channel pattern CH1 and the second channel pattern CH2 to be described below. The term "cover" (or "covering" or similar terms) as may be used herein is intended to refer broadly to a material, layer or structure on or above another material, layer or structure, but does not require that a material, layer or structure completely covers another material, layer or structure.

[0035] A first channel pattern CH1 may be disposed on the first active pattern AP1. A second channel pattern CH2 may be disposed on the second active pattern AP2. Each of the first channel pattern CH1 and the second channel pattern CH2 may include a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 sequentially stacked along a third direction D3. The first to third semiconductor patterns SP1, SP2, and SP3 may be spaced apart from each other in a vertical direction (i.e., the third direction D3).

[0036] Each of the first to third semiconductor patterns SP1, SP2, and SP3 may be formed of or include silicon (Si), germanium (Ge), or silicon germanium (SiGe). For example, each of the first to third semiconductor patterns SP1, SP2, and SP3 may be formed of or include crystalline silicon (e.g., single crystal silicon). In an embodiment, the first to third semiconductor patterns SP1, SP2, and SP3 may be stacked nanosheets.

[0037] A plurality of first source / drain patterns SD1 may be disposed on the first active pattern AP1. A plurality of first recesses RS1 may be formed in an upper portion of the first active pattern AP1. The first source / drain patterns SD1 may be disposed in the first recesses RS1, respectively. The first source / drain patterns SD1 may be impurity regions of a first conductivity type (e.g., n-type). The first channel pattern CH1 may be between the paired first source / drain patterns SD1. That is, each pair of first source / drain patterns SD1 may be connected to each other by the stacked first to third semiconductor patterns SP1, SP2, and SP3.

[0038] A plurality of second source / drain patterns SD2 may be disposed on the second active pattern AP2. A plurality of second recesses RS2 may be formed in an upper portion of the second active pattern AP2. The second source / drain patterns SD2 may be disposed in the second recesses RS2, respectively. The second source / drain patterns SD2 may be impurity regions of a second conductivity type (e.g., p-type). The second channel pattern CH2 may be between the paired second source / drain patterns SD2. That is, each pair of second source / drain patterns SD2 may be connected to each other by the stacked first to third semiconductor patterns SP1, SP2, and SP3.

[0039] The first source / drain pattern SD1 and the second source / drain pattern SD2 may be epitaxial patterns formed by a selective epitaxial growth (SEG) process. In an embodiment, a top surface of each of the first source / drain pattern SD1 and the second source / drain pattern SD2 may be higher than a top surface of the third (topmost) semiconductor pattern SP3. In another embodiment, a top surface of at least one of the first source / drain pattern SD1 and the second source / drain pattern SD2 may be at substantially the same height as a top surface of the third semiconductor pattern SP3; that is, with respect to an upper surface of the substrate 100 as a reference layer, a top surface of at least one of the first source / drain pattern SD1 and the second source / drain pattern SD2 may be substantially coplanar with a top surface of the third semiconductor pattern SP3 in a third direction D3.

[0040] In an embodiment, the first source / drain pattern SD1 may be formed of or include the same semiconductor element (e.g., Si) as the substrate 100. The second source / drain pattern SD2 may include a semiconductor material (e.g., SiGe) having a lattice constant greater than that of the substrate 100. In this case, the pair of second source / drain patterns SD2 may apply compressive stress on the second channel pattern CH2 therebetween.

[0041] In an embodiment, the second source / drain pattern SD2 may have an uneven or embossed side surface. That is, the side surface of the second source / drain pattern SD2 may have a wavy profile in the third direction D3. The side surface of the second source / drain pattern SD2 may protrude toward the first to third internal electrodes PO1, PO2, and PO3 of the gate electrode GE to be described below.

[0042] The gate electrode GE may be disposed on the first channel pattern CH1 and the second channel pattern CH2. Each gate electrode GE may extend in the first direction D1 to intersect the first channel pattern CH1 and the second channel pattern CH2. Each gate electrode GE may overlap vertically with the first channel pattern CH1 and the second channel pattern CH2. The term "overlapped" (or "overlapping" or similar terms) as used herein is intended to broadly refer to a first element that intersects at least a portion of a second element in a vertical direction (i.e., a third direction D3), but does not require that the first element and the second element be completely aligned with each other in a horizontal plane (i.e., in the first direction D1 and / or the second direction D2). The gate electrode GE may be arranged at a first pitch along the second direction D2. The gate electrode GE may extend in the first direction D1 and may be arranged along a second direction D2 that intersects the first direction D1.

[0043] The gate electrode GE may include a first internal electrode PO1 between the active pattern AP1 or AP2 and the first semiconductor pattern SP1, a second internal electrode PO2 between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, a third internal electrode PO3 between the second semiconductor pattern SP2 and the third semiconductor pattern SP3, and an external electrode PO4 on the third semiconductor pattern SP3.

[0044] refer to Figure 5D , the gate electrode GE may be disposed on the top surface TS, the bottom surface BS, and the opposite side surface SW of each of the first to third semiconductor patterns SP1, SP2, and SP3. That is, the transistor according to the present embodiment may be a three-dimensional field effect transistor (e.g., a multi-bridge channel field effect transistor (MBCFET) or a full surround gate field effect transistor (GAAFET)), in which the gate electrode GE is disposed to three-dimensionally surround the channel pattern. The term "surround" (or "surrounding" or similar terms) as used herein is intended to broadly refer to an element, structure, or layer that extends, encapsulates, surrounds, or encloses another element, structure, or layer on all sides, but interruptions or gaps may also exist. Thus, for example, a material layer having a gap therein may still "surround" another layer that it surrounds.

[0045] On the first active region AR1, an inner spacer ISP may be interposed between the first to third inner electrodes PO1, PO2, and PO3 of the gate electrode GE and the first source / drain pattern SD1, respectively. Each of the first to third inner electrodes PO1, PO2, and PO3 of the gate electrode GE may be spaced apart from the first source / drain pattern SD1, and the inner spacer ISP is interposed between each of the first to third inner electrodes PO1, PO2, and PO3 of the gate electrode GE and the first source / drain pattern SD1. The inner spacer ISP may prevent leakage current from the gate electrode GE.

[0046] Return to reference Figure 4 and FIG. 5A to FIG. 5D , the paired gate spacers GS may be respectively disposed on the opposite side surfaces of the external electrode PO4 of the gate electrode GE. The gate spacer GS may extend along the gate electrode GE and in the first direction D1. The top surface of the gate spacer GS may be higher than the top surface of the gate electrode GE. The top surface of the gate spacer GS may be coplanar with the top surface of the first interlayer insulating layer 110 to be described below in the third direction D3. In an embodiment, the gate spacer GS may be formed of at least one of SiCN, SiCON or SiN or include at least one of SiCN, SiCON or SiN. In another embodiment, the gate spacer GS may be a multilayer structure formed of at least two different materials selected from SiCN, SiCON and SiN or include at least two different materials selected from SiCN, SiCON and SiN. In an embodiment, the gate spacer GS may be formed of an insulating material containing Si or include an insulating material containing Si. The gate spacer GS may be used as an etching stop layer in the process of forming the active contact AC to be described below. The active contact AC may be formed by a self-alignment process using the gate spacer GS.

[0047] The gate capping pattern GP may be disposed on the gate electrode GE. The gate capping pattern GP may extend along the gate electrode GE and in the first direction D1. The gate capping pattern GP may be formed of or include a material having an etching selectivity with respect to the first interlayer insulating layer 110 and the second interlayer insulating layer 120, which will be described below. In detail, the gate capping pattern GP may be formed of or include at least one of SiON, SiCN, SiCON, or SiN.

[0048] The gate insulating layer GI may be interposed between the gate electrode GE and the first channel pattern CH1 and between the gate electrode GE and the second channel pattern CH2. The gate insulating layer GI may cover a top surface TS, a bottom surface BS, and opposite side surfaces SW of each of the first to third semiconductor patterns SP1, SP2, and SP3. The gate insulating layer GI may cover a top surface of a device isolation layer ST located under the gate electrode GE.

[0049] In an embodiment, the gate insulating layer GI may include a silicon oxide layer, a silicon oxynitride layer and / or a high-k dielectric layer. For example, the gate insulating layer GI may have a structure in which a silicon oxide layer and a high-k dielectric layer are stacked. The high-k dielectric layer may be formed of at least one high-k dielectric material having a dielectric constant higher than that of silicon oxide or include at least one high-k dielectric material having a dielectric constant higher than that of silicon oxide. For example, the high-k dielectric material may include at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium oxide silicon, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0050] In another embodiment, the semiconductor device may include a negative capacitance (NC) FET using a negative capacitor.For example, the gate insulating layer GI may include a ferroelectric layer exhibiting a ferroelectric property and a paraelectric layer exhibiting a paraelectric property.

[0051] The ferroelectric layer may have a negative capacitance, while the paraelectric layer may have a positive capacitance. In the case where two or more capacitors are connected in series and each capacitor has a positive capacitance, the total capacitance may be reduced to a value less than the capacitance of each capacitor. In contrast, in the case where at least one of the series-connected capacitors has a negative capacitance, the total capacitance of the series-connected capacitors may have a positive value and may be greater than the absolute value of each capacitance.

[0052] In the case where a ferroelectric layer having a negative capacitance and a paraelectric layer having a positive capacitance are connected in series, the total capacitance of the ferroelectric layer and the paraelectric layer connected in series can be increased. Due to such an increase in the total capacitance, a transistor including the ferroelectric layer can have a subthreshold swing (SS) of less than 60 mV / decade at room temperature.

[0053] The ferroelectric layer may have ferroelectric properties. The ferroelectric layer may be formed of, for example, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and / or lead zirconium titanium oxide or include, for example, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and / or lead zirconium titanium oxide. Here, hafnium zirconium oxide may be hafnium oxide doped with zirconium (Zr). Alternatively, hafnium zirconium oxide may be a compound composed of hafnium (Hf), zirconium (Zr), and / or oxygen (O).

[0054] The ferroelectric layer may further include a dopant. The dopant may include, for example, at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), or tin (Sn). The type of dopant in the ferroelectric layer may vary depending on the ferroelectric material included in the ferroelectric layer.

[0055] In the case where the ferroelectric layer includes hafnium oxide, the dopant in the ferroelectric layer may include, for example, at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and / or yttrium (Y).

[0056] In the case where the dopant is aluminum (Al), the content of aluminum in the ferroelectric layer may be in the range of about 3 at% (atomic percentage) to 8 at%. Here, the content of the dopant (eg, aluminum atoms) may be a ratio of the number of aluminum atoms to the number of hafnium and aluminum atoms.

[0057] In the case where the dopant is silicon (Si), the content of silicon in the ferroelectric layer may be in the range of about 2 at% to 10 at%. In the case where the dopant is yttrium (Y), the content of yttrium in the ferroelectric layer may be in the range of about 2 at% to 10 at%. In the case where the dopant is gadolinium (Gd), the content of gadolinium in the ferroelectric layer may be in the range of about 1 at% to 7 at%. In the case where the dopant is zirconium (Zr), the content of zirconium in the ferroelectric layer may be in the range of about 50 at% to 80 at%.

[0058] The paraelectric layer may have paraelectric properties. The paraelectric layer may be formed of or include, for example, at least one of silicon oxide and / or a high-k metal oxide. Metal oxides that can be used as paraelectric layers may include, for example, at least one of hafnium oxide, zirconium oxide, and / or aluminum oxide, but the inventive concept is not limited to these examples.

[0059] The ferroelectric layer and the paraelectric layer may be formed of or include the same material. The ferroelectric layer may have ferroelectric properties, but the paraelectric layer may not have ferroelectric properties. For example, in the case where the ferroelectric layer and the paraelectric layer contain hafnium oxide, the crystal structure of the hafnium oxide in the ferroelectric layer may be different from the crystal structure of the hafnium oxide in the paraelectric layer.

[0060] The ferroelectric layer can exhibit ferroelectric properties only when the thickness of the ferroelectric layer is within a specific range. In an embodiment, the thickness of the ferroelectric layer can be in the range of about 0.5 nanometers (nm) to 10 nm, but the inventive concept is not limited to this example. Since the critical thickness associated with the occurrence of ferroelectric properties varies depending on the type of ferroelectric material, the thickness of the ferroelectric layer can vary depending on the type of ferroelectric material.

[0061] As an example, the gate insulating layer GI may include a single ferroelectric layer. As another example, the gate insulating layer GI may include a plurality of ferroelectric layers spaced apart from each other. The gate insulating layer GI may have a multilayer structure in which a plurality of ferroelectric layers and a plurality of paraelectric layers are alternately stacked.

[0062] Return to reference Figure 4 and FIG. 5A to FIG. 5D , the gate electrode GE may include a first metal pattern and a second metal pattern located on the first metal pattern. The first metal pattern may be disposed on the gate insulating layer GI and may be adjacent to the first to third semiconductor patterns SP1, SP2, and SP3. The first metal pattern may include a work function metal, which can be used to adjust the threshold voltage of the transistor. By adjusting the cross-sectional thickness and composition of the first metal pattern, a transistor with a desired threshold voltage may be realized. For example, the first to third inner electrodes PO1, PO2, and PO3 of the gate electrode GE may be composed of the first metal pattern or the work function metal.

[0063] The first metal pattern may include a metal nitride layer. For example, the first metal pattern may include a layer composed of at least one metal material selected from the group consisting of titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), molybdenum (Mo) and nitrogen (N). In an embodiment, the first metal pattern may also include carbon (C). The first metal pattern may include a plurality of stacked work function metal layers.

[0064] The second metal pattern may be formed of a metal material having a lower resistance than the first metal pattern or include a metal material having a lower resistance than the first metal pattern. For example, the second metal pattern may include at least one metal material selected from the group consisting of tungsten (W), aluminum (Al), titanium (Ti), and tantalum (Ta). In an embodiment, the external electrode PO4 of the gate electrode GE may include a first metal pattern and a second metal pattern located on the first metal pattern.

[0065] The first interlayer insulating layer 110 may be disposed on the substrate 100. The first interlayer insulating layer 110 may cover the gate spacer GS and the first source / drain pattern SD1 and the second source / drain pattern SD2. The top surface of the first interlayer insulating layer 110 may be substantially coplanar with the top surface of the gate capping pattern GP and the top surface of the gate spacer GS in the third direction D3. The second interlayer insulating layer 120 may be disposed on the first interlayer insulating layer 110 to cover the gate capping pattern GP. The third interlayer insulating layer 130 may be disposed on the second interlayer insulating layer 120. The fourth interlayer insulating layer 140 may be disposed on the third interlayer insulating layer 130. In an embodiment, at least one of the first to fourth interlayer insulating layers 110 to 140 may include a silicon oxide layer.

[0066] The single height cell SHC may have a first boundary BD1 and a second boundary BD2 opposite to each other in the second direction D2. The first boundary BD1 and the second boundary BD2 may extend in the first direction D1. The single height cell SHC may have a third boundary BD3 and a fourth boundary BD4 opposite to each other in the first direction D1. The third boundary BD3 and the fourth boundary BD4 may extend in the second direction D2.

[0067] Pairs of partition structures DB opposite to each other in the second direction D2 may be disposed on both sides of the single height cell SHC. For example, the pair of partition structures DB may be disposed on the first boundary BD1 and the second boundary BD2 of the single height cell SHC, respectively. The partition structure DB may extend in the first direction D1 to be parallel to the gate electrode GE. The pitch between the partition structure DB and the gate electrode GE adjacent thereto may be equal to the first pitch.

[0068] The separation structure DB may penetrate (i.e., extend into or through) the first interlayer insulating layer 110 and the second interlayer insulating layer 120, and may extend into the active pattern AP1 or AP2. The separation structure DB may penetrate an upper portion of each of the first active pattern AP1 and the second active pattern AP2. The separation structure DB may electrically separate the active region of each single height cell SHC from the active region of an adjacent cell.

[0069] The active contacts AC may be disposed to penetrate the first interlayer insulating layer 110 and the second interlayer insulating layer 120 and be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2, respectively. The paired active contacts AC may be disposed at both sides of the gate electrode GE, respectively. When viewed in a top view, the active contacts AC may be stripe patterns extending in the first direction D1.

[0070] The active contact AC may be a self-aligned contact. For example, the active contact AC may be formed by a self-aligned process using the gate capping pattern GP and the gate spacer GS. For example, the active contact AC may cover at least a portion of the side surface of the gate spacer GS. Although not shown, the active contact AC may be provided to cover a portion of the top surface of the gate capping pattern GP.

[0071] A metal semiconductor compound layer SC (e.g., a silicide layer) may be interposed between the first active contact AC1 and the first source / drain pattern SD1 and between the second active contact AC2 and the second source / drain pattern SD2, respectively. The first active contact AC1 and the second active contact AC2 may be electrically connected to the source / drain pattern SD1 or SD2 through the metal semiconductor compound layer SC. For example, the metal semiconductor compound layer SC may be formed of or include at least one of titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, or cobalt silicide, but the embodiment is not limited thereto. Reference will be made to FIG. 5A to FIG. 5C , Fig. 6A and Figure 6B The first active contact AC1 and the second active contact AC2 are described in more detail.

[0072] The gate contact GC may be disposed to penetrate the second interlayer insulating layer 120 and the gate capping pattern GP, ​​and may be electrically connected to the gate electrode GE, respectively. When viewed in a top view, the gate contact GC may overlap the first active region AR1 and the second active region AR2, respectively. In an embodiment, the gate contact GC may be disposed on the second active pattern AP2 (for example, see Figure 5B ).

[0073] In the embodiments, reference Figure 5B , the area placed on the second active contact AC2 adjacent to the gate contact GC may be filled with the upper insulating pattern UIP. The bottom surface of the upper insulating pattern UIP may be lower than the bottom surface of the gate contact GC. That is, the top surface of the second active contact AC2 adjacent to the gate contact GC may be formed at a height lower than the bottom surface of the gate contact GC by the upper insulating pattern UIP. Therefore, it may be possible to prevent the gate contact GC and the second active contact AC2 adjacent to each other from contacting each other, thereby preventing a short circuit problem from occurring between the gate contact GC and the second active contact AC2.

[0074] The first active contact AC1 may include a first conductive pattern FM1 and a first barrier pattern BM1 surrounding the first conductive pattern FM1 (i.e., extending around it), and the second active contact AC2 may include a second conductive pattern FM2 and a second barrier pattern BM2 surrounding the second conductive pattern FM2 (i.e., extending around it). The gate contact GC may include a conductive pattern FM and a barrier pattern BM surrounding the conductive pattern FM (i.e., extending around it). For example, each of the conductive patterns FM1, FM2, and FM may be formed of at least one of metal materials (e.g., aluminum, copper, tungsten, molybdenum, and cobalt) or include at least one of metal materials (e.g., aluminum, copper, tungsten, molybdenum, and cobalt). Each of the barrier patterns BM1, BM2, and BM may cover the side surface and bottom surface of each of the conductive patterns FM1, FM2, and FM. Each of the barrier patterns BM1, BM2, and BM may include a metal layer or a metal nitride layer. The metal layer may be formed of at least one of titanium, tantalum, tungsten, nickel, cobalt, or platinum or include at least one of titanium, tantalum, tungsten, nickel, cobalt, or platinum. The metal nitride layer may be formed of or include at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), or platinum nitride (PtN).

[0075] The metal interconnection structure MST may be disposed in the third interlayer insulating layer 130 and the fourth interlayer insulating layer 140. The metal interconnection structure MST may include a first metal layer M1 and a second metal layer M2.

[0076] A first metal layer M1 may be provided. In an embodiment, the first metal layer M1 may include a first power line M1_R1, a second power line M1_R2, and a first interconnection pattern M1_I. Each of the interconnection lines M1_R1, M1_R2, and M1_I of the first metal layer M1 may extend in the second direction D2 and be parallel to each other.

[0077] In detail, the first power line M1_R1 and the second power line M1_R2 may be disposed on the third boundary BD3 and the fourth boundary BD4 of the single height cell SHC, respectively. The first power line M1_R1 may extend along the third boundary BD3 and in the second direction D2. The second power line M1_R2 may extend along the fourth boundary BD4 and in the second direction D2.

[0078] The first interconnection pattern M1_I of the first metal layer M1 may be disposed between the first power line M1_R1 and the second power line M1_R2. The first interconnection pattern M1_I of the first metal layer M1 may be arranged at a second pitch along the first direction D1. The second pitch may be smaller than the first pitch. The line width of each of the first interconnection patterns M1_I may be smaller than the line width of each of the first power line M1_R1 and the second power line M1_R2.

[0079] The first metal layer M1 may further include a first conductive path VI1. The first conductive path VI1 may be disposed under the interconnections M1_R1, M1_R2, and M1_I of the first metal layer M1, respectively. The active contact AC and the interconnections of the first metal layer M1 may be electrically connected to each other through the first conductive path VI1. The gate contact GC and the interconnections of the first metal layer M1 may be electrically connected to each other through the first conductive path VI1.

[0080] The interconnection line of the first metal layer M1 and the first conductive path VI1 thereunder may be formed by separate processes. That is, each of the interconnection line of the first metal layer M1 and the first conductive path VI1 may be formed by a single damascene process. The semiconductor device according to the present embodiment may be manufactured using a sub-20nm process.

[0081] The second metal layer M2 may be disposed in the fourth interlayer insulating layer 140. The second metal layer M2 may include a plurality of second interconnection patterns M2_I. Each second interconnection pattern M2_I of the second metal layer M2 may be a linear pattern or a stripe pattern extending in the first direction D1. That is, the second interconnection patterns M2_I may extend in the first direction D1 and be parallel to each other.

[0082] The second metal layer M2 may further include second conductive paths VI2 respectively disposed under the second interconnection patterns M2_I. The interconnection lines of the first metal layer M1 and the second metal layer M2 may be electrically connected to each other through the second conductive paths VI2. The interconnection lines of the second metal layer M2 and the second conductive paths VI2 thereunder may be formed together through a dual damascene process.

[0083] The interconnection line of the first metal layer M1 may be formed of a conductive material that is the same as or different from the conductive material of the second metal layer M2 or include a conductive material that is the same as or different from the conductive material of the second metal layer M2. For example, the interconnection line of the first metal layer M1 and the second metal layer M2 may be formed of at least one of a metal material (e.g., aluminum, copper, tungsten, ruthenium, molybdenum, and cobalt) or include at least one of a metal material (e.g., aluminum, copper, tungsten, ruthenium, molybdenum, and cobalt). Although not shown, a plurality of metal layers (e.g., M3, M4, M5, etc.) may be additionally stacked on the fourth interlayer insulating layer 140. Each stacked metal layer may include an interconnection line used as a routing path between cells.

[0084] Will refer to FIG. 5A to FIG. 5D The first active contact AC1 and the second active contact AC2 are described in more detail. The first active contact AC1 may include a first conductive pattern FM1 and a first barrier pattern BM1 surrounding the first conductive pattern FM1 (i.e., extending around it). The first active contact AC1 may vertically overlap the first source / drain pattern SD1 (in the third direction D3). The first active contact AC1 may be electrically connected to the first source / drain pattern SD1. For example, a lower portion of the first active contact AC1 may be inserted into the first source / drain pattern SD1 (i.e., contacting the first source / drain pattern SD1), and the first active contact AC1 and the first source / drain pattern SD1 may contact each other through the inserted lower portion.

[0085] The silicide layer SC may be interposed between the first active contact AC1 and the first source / drain pattern SD1. The silicide layer SC may be a metal semiconductor compound layer. The silicide layer SC may reduce the contact resistance between the first active contact AC1 and the first source / drain pattern SD1. That is, the first active contact AC1 may be electrically connected to the first source / drain pattern SD1 through the silicide layer SC.

[0086] Will refer to Figure 5C and Fig. 6A The metal interconnection structure MST including the first metal layer M1 and the second metal layer M2 is described in more detail The metal interconnection structure MST may include interconnection patterns M1_I and M2_I, etch stop layers EST1 and EST2, conductive vias VI1 and VI2, and interlayer insulating layers 130 and 140.

[0087] The first metal layer M1 may include a first etch stop layer EST1, a third interlayer insulating layer 130 on the first etch stop layer EST1, a first conductive via VI1 penetrating the first etch stop layer EST1, and a first interconnection pattern M1_I electrically connected to the first conductive via VI1.

[0088] The first etch stop layer EST1 may be disposed on the second interlayer insulating layer 120. The first etch stop layer EST1 may be formed of or include, for example, silicon nitride. The first etch stop layer EST1 may be interposed between the second interlayer insulating layer 120 and the third interlayer insulating layer 130.

[0089] The third interlayer insulating layer 130 may include a first via insulating layer 1301 and a first pattern insulating layer 1302 on the first via insulating layer 1301. The first via insulating layer 1301 may be disposed on the first etch stop layer EST1. The first via insulating layer 1301 may include an insulating material. The first pattern insulating layer 1302 may include an insulating material.

[0090] The first conductive via VI1 may penetrate the first etch stop layer EST1 and the first via insulating layer 1301. The first conductive via VI1 may contact the first etch stop layer EST1 and the first via insulating layer 1301. The first conductive via VI1 may include a conductive material.

[0091] The first interconnection pattern M1_I may penetrate the first pattern insulating layer 1302. The first interconnection pattern M1_I may be electrically connected to the first conductive via VI1. The first interconnection pattern M1_I may include a conductive material.

[0092] The second metal layer M2 may include a second etch stop layer EST2, a fourth interlayer insulating layer 140 on the second etch stop layer EST2, a second conductive via VI2 penetrating the second etch stop layer EST2, and a second interconnection pattern M2_I electrically connected to the second conductive via VI2.

[0093] The second etch stop layer EST2 may be disposed on the third interlayer insulating layer 130. The second etch stop layer EST2 may be formed of or include, for example, silicon nitride. The second etch stop layer EST2 may be interposed between the third interlayer insulating layer 130 and the fourth interlayer insulating layer 140.

[0094] The fourth interlayer insulating layer 140 may include a second via insulating layer 1401 and a second pattern insulating layer 1402 on the second via insulating layer 1401. The second via insulating layer 1401 may be disposed on the second etch stop layer EST2. The second via insulating layer 1401 may include an insulating material. The second pattern insulating layer 1402 may include an insulating material.

[0095] The second conductive via VI2 may penetrate the second etch stop layer EST2 and the second via insulating layer 1401. The second conductive via VI2 may contact the second etch stop layer EST2 and the second via insulating layer 1401. The second conductive via VI2 may include a conductive material.

[0096] The second interconnection pattern M2_I may penetrate the second pattern insulation layer 1402. The second interconnection pattern M2_I may be electrically connected to the second conductive via VI2. The second interconnection pattern M2_I may include a conductive material. The second interconnection pattern M1_I may include copper.

[0097] Will refer to Fig. 6A The embodiments according to the present invention are described in more detail. Figure 5C The structure of the part "P" (Pa). Fig. 6A , the diffusion prevention pattern ISTA may be interposed between the first interconnection pattern M1_Ia and the second conductive via VI2a.

[0098] A second interconnect pattern M2_Ia and a selection barrier pattern BSLa surrounding the second conductive path VI2a (i.e., extending around it) may be provided. The selection barrier pattern BSLa may contact the bottom surface of the second interconnect pattern M2_Ia that is not in contact with the second conductive path VI2a. The selection barrier pattern BSLa may cover the side surface of the second conductive path VI2a. The selection barrier pattern BSLa may include tantalum nitride (TaN). The selection barrier pattern BSLa may contact the second path insulating layer 1401. A portion of the selection barrier pattern BSLa may be between the bottom surface of the second interconnect pattern M2_Ia that is not in contact with the second conductive path VI2a and the second path insulating layer 1401.

[0099] The bottom surface BSLa_BS of the selection barrier pattern BSLa may contact the top surface ISTA_TS of the diffusion prevention pattern ISTA. The top surface ISTA_Ta of the diffusion prevention pattern ISTA may contact the selection barrier pattern BSLa and the second conductive path VI2a. The side surface of the diffusion prevention pattern ISTA may contact the second etch stop layer EST2 and the first interconnection pattern M1_Ia.

[0100] With respect to the substrate 100 ( Figure 5C ), the height of the bottom surface ISTA_BS of the diffusion prevention pattern ISTA may be lower than the height of the topmost surface M1_IaTS of the first interconnection pattern M1_Ia in the third direction D3. The topmost surface M1_IaTS of the first interconnection pattern M1_Ia may be defined as the first interconnection pattern M1_Ia in contact with the second etch stop layer EST2. With respect to the substrate 100( Figure 5C ), the height of the bottom surface ISTA_BS of the diffusion prevention pattern ISTA may be lower than the height of the bottom surface EST2_BS of the second etch stop layer EST2 in the third direction D3. The bottom surface EST2_BS of the second etch stop layer EST2 may be coplanar with the topmost surface M1_IaTS of the first interconnection pattern M1_Ia in the third direction D3.

[0101] The top surface ISTA_TS of the diffusion prevention pattern ISTA may be lower in height than the top surface EST2_TS of the second etch stop layer EST2 in the third direction D3. The top surface ISTA_TS of the diffusion prevention pattern ISTA may be higher in height than the topmost surface M1_IaTS of the first interconnection pattern M1_Ia in the third direction D3.

[0102] A width M1_IaW of the first interconnection pattern M1_Ia in the first direction D1 may be greater than a width ISTA_BSW of a bottom surface ISTA_BS of the diffusion prevention pattern ISTA in the first direction D1.

[0103] The diffusion prevention pattern ISTA may be formed by performing an oxidation process on a portion of the top surface of the first interconnection pattern M1_Ia. The diffusion prevention pattern ISTA may be formed of or include ruthenium oxide. The first interconnection pattern M1_Ia may be formed of or include ruthenium. The second conductive path VI2a may include copper or molybdenum. In an embodiment, the first conductive path VI1a may include ruthenium, and the second interconnection pattern M2_Ia may include copper.

[0104] Will refer to Figure 6B The embodiments according to the present invention are described in more detail. Figure 5C For brevity of description, previously described elements may be identified by the same reference numerals without repeating their repeated descriptions.

[0105] refer to Figure 6B , the diffusion preventing pattern ISTb may be interposed between the second interconnection pattern M2_Ib and the second conductive via VI2b.

[0106] The selection barrier pattern BSLb may be disposed on the bottom surface M2_IbBS of the second interconnection pattern M2_Ib. For example, the selection barrier pattern BSLb may be disposed on the bottom surface M2_IbBS of the second interconnection pattern M2_Ib that does not contact the second conductive via VI2b. The selection barrier pattern BSLb may be interposed between the second interconnection pattern M2_Ib and the second via insulating layer 1401.

[0107] The bottom surface BSLb_BS of the selection barrier pattern BSLb may be in contact with the second via insulating layer 1401. The bottom surface BSLb_BS of the selection barrier pattern BSLb may be in contact with the top surface 1401_TS of the second via insulating layer 1401. The top surface BSLb_TS of the selection barrier pattern BSLb may be in contact with the second interconnection pattern M2_Ib. The top surface BSLb_TS of the selection barrier pattern BSLb may be in contact with the bottommost surface M2_IbBS of the second interconnection pattern M2_Ib. The bottommost surface M2_IbBS of the second interconnection pattern M2_Ib may be defined as a surface of the second interconnection pattern M2_Ib in contact with the selection barrier pattern BSLb. The top surface ISTb_TS of the diffusion prevention pattern ISTb may be in contact with the second interconnection pattern M2_Ib. The side surface of the diffusion prevention pattern ISTb may be in contact with the selection barrier pattern BSLb, the second via insulating layer 1401, and the second interconnection pattern M2_Ib.

[0108] With respect to the substrate 100 as a reference layer (see Figure 5C ), the height of the bottom surface ISTb_BS of the diffusion prevention pattern ISTb may be lower than the height of the bottom surface BSLb_BS of the selection blocking pattern BSLb in the third direction D3. Figure 5C ), the height of the bottom surface ISTb_BS of the diffusion prevention pattern ISTb may be lower than the height of the top surface 1401_TS of the second via insulating layer 1401 in the third direction D3. Figure 5C ), a height of the bottom surface ISTb_BS of the diffusion prevention pattern ISTb may be lower than a height of the bottommost surface M2_IbBS of the second interconnection pattern M2_Ib in the third direction D3.

[0109] With respect to the substrate 100 (see Figure 5C ), the height of the top surface ISTb_TS of the diffusion prevention pattern ISTb may be higher than the height of the top surface BSLb_TS of the selection blocking pattern BSLb in the third direction D3. Figure 5C ), a height of the top surface ISTb_TS of the diffusion prevention pattern ISTb may be higher than a height of the bottommost surface M2_IbBS of the second interconnection pattern M2_Ib in the third direction D3.

[0110] The diffusion prevention pattern ISTb may be formed by performing an oxidation process on a portion of the top surface of the second conductive path VI2b. The diffusion prevention pattern ISTb may include ruthenium oxide. The second interconnection pattern M2_Ib may include copper. The second conductive path VI2b may include ruthenium. In an embodiment, the first interconnection pattern M1_Ia and the first conductive path VI1b may be formed of or include ruthenium.

[0111] Will refer to Figure 6C The embodiments according to the present invention are described in more detail. Figure 5C For brevity of description, previously described elements may be identified by the same reference numerals without repeating their repeated descriptions.

[0112] refer to Figure 6C , the diffusion prevention pattern ISTc may be interposed between the first interconnection pattern M1_Ic and the first conductive path VI1c. The selection barrier pattern BSLc may be interposed between the first pattern insulation layer 1302 and the first interconnection pattern M1_Ic and between the first path insulation layer 1301 and the first interconnection pattern M1_Ic. The side surface of the diffusion prevention pattern ISTc may contact the first interconnection pattern M1_Ic, the selection barrier pattern BSLc, and the first path insulation layer 1301. The selection barrier pattern BSLc may be disposed on the side surface of the first interconnection pattern M1_Ic and on the bottom surface of the first interconnection pattern M1_Ic that is not in contact with the first conductive path VI1c.

[0113] A bottom surface BSLc_BS of the selection barrier pattern BSLc may be in contact with the first via insulating layer 1301. A topmost surface BSLc_TMS of the selection barrier pattern BSLc may be in contact with the second etch stop layer EST2. A topmost surface BSLc_TMS of the selection barrier pattern EST2 may be coplanar with a bottom surface of the second etch stop layer EST2 in the third direction D3. A topmost surface BSLc_TMS of the selection barrier pattern BSLc may be coplanar with a top surface of the first interconnection pattern M1_Ic in the third direction D3.

[0114] The bottommost surface M1_IcBS of the first interconnection pattern M1_Ic may be defined as a surface of the first interconnection pattern M1_Ic in contact with the selection barrier pattern BSLc. The top surface ISTc_TS of the diffusion prevention pattern ISTc may be in contact with the first interconnection pattern M1_Ic. The side surface of the diffusion prevention pattern ISTc may be in contact with the selection barrier pattern BSLc, the first pattern insulation layer 1302, and the first interconnection pattern M1_Ic.

[0115] With respect to the substrate 100 as a reference layer (see Figure 5C), the height of the bottom surface ISTc_BS of the diffusion prevention pattern ISTc may be lower than the height of the bottom surface BSLc_BS of the selection blocking pattern BSLc in the third direction D3. Figure 5C ), the height of the bottom surface ISTc_BS of the diffusion prevention pattern ISTc may be lower than the height of the top surface 1301_TS of the first via insulating layer 1301 in the third direction D3. Figure 5C ), a height of the bottom surface ISTc_BS of the diffusion prevention pattern ISTc may be lower than a height of the bottommost surface M1_IcBS of the first interconnection pattern M1_Ic in the third direction D3.

[0116] With respect to the substrate 100 (see Figure 5C ), the height of the top surface ISTc_TS of the diffusion prevention pattern ISTc may be higher than the height of the bottom surface BSLc_BS of the selection blocking pattern BSLc in the third direction D3. Figure 5C ), a height of the top surface ISTc_TS of the diffusion prevention pattern ISTc may be higher than a height of the bottommost surface M1_IcBS of the first interconnection pattern M1_Ic in the third direction D3.

[0117] A width M1_IcW of the first interconnection pattern M1_Ic in the first direction D1 may be greater than a width ISTc_TSW of the diffusion prevention pattern ISTc in the first direction D1 measured at a height of a top surface ISTc_TS of the diffusion prevention pattern ISTc.

[0118] The diffusion prevention pattern ISTc may be formed by performing an oxidation process on a portion of the top surface of the first conductive path VI1c. The diffusion prevention pattern ISTc may include ruthenium oxide. The first interconnection pattern M1_Ic may include copper. The first conductive path VI1c may include ruthenium or molybdenum. In an embodiment, the second interconnection pattern M2_Ic and the second conductive path VI2c may be formed of or include copper.

[0119] Will refer to Fig.6D The embodiments according to the present invention are described in more detail. Figure 5C For brevity of description, previously described elements may be identified by the same reference numerals without repeating their duplicate descriptions.

[0120] refer to Fig.6DThe diffusion prevention pattern ISTd may be interposed between the first interconnection pattern M1_Id and the second conductive via VI2d. In an embodiment, the second interconnection pattern M2_Id and a selection barrier pattern (not shown) surrounding the second conductive via VI2d may be provided, but are not shown.

[0121] The bottom surface M1_IdBS of the first interconnection pattern M1_Id may be coplanar with the top surface 1301_TS of the first via insulating layer 1301 in the third direction D3 .

[0122] A top surface ISTd_TS of the diffusion prevention pattern ISTd may be in contact with the second conductive via VI2d. A side surface of the diffusion prevention pattern ISTd may be in contact with the second etch stop layer EST2 and the first interconnection pattern M1_Id.

[0123] With respect to the substrate 100 as a reference layer (see Figure 5C ), the height of the bottom surface ISTd_BS of the diffusion prevention pattern ISTd may be lower than the height of the topmost surface M1_IdTS of the first interconnection pattern M1_Id in the third direction D3. The topmost surface M1_IdTS of the first interconnection pattern M1_Id may be defined as a surface of the first interconnection pattern M1_Id in contact with the second etch stop layer EST2. With respect to the substrate 100 (see Figure 5C ), the height of the bottom surface ISTd_BS of the diffusion prevention pattern ISTd may be lower than the height of the bottom surface of the second etch stop layer EST2 in the third direction D3. The bottom surface of the second etch stop layer EST2 may be coplanar with the topmost surface M1_IdTS of the first interconnection pattern M1_Id in the third direction D3.

[0124] With respect to the substrate 100 (see Figure 5C ), the height of the top surface ISTd_TS of the diffusion prevention pattern ISTd may be lower than the height of the top surface EST2_TS of the second etch stop layer EST2 in the third direction D3. Figure 5C ), a height of the top surface ISTd_TS of the diffusion prevention pattern ISTd may be higher than a height of the topmost surface M1_IdTS of the first interconnection pattern M1_Id in the third direction D3.

[0125] A width M1_IdW of the first interconnection pattern M1_Id in the first direction D1 may be greater than a width ISTd_TSW of a top surface ISTd_TS of the diffusion prevention pattern ISTd in the first direction D1 .

[0126] The diffusion prevention pattern ISTd may be formed by depositing ruthenium on the top surface of the first interconnection pattern M1_Ia. The diffusion prevention pattern ISTd may include ruthenium oxide. In an embodiment, the diffusion prevention pattern ISTd may be composed of Ru / RuO 2 Forming or including Ru / RuO 2 The first interconnection pattern M1_Id and the first conductive via VI1d may include copper. The second conductive via VI2d and the second interconnection pattern M2_Id may be formed of or include ruthenium.

[0127] FIG. 7A to FIG. 7C is a diagram illustrating a method of manufacturing a Fig. 6A A cross-sectional view of an intermediate process in an exemplary method of a semiconductor device. In detail, FIG. 7A to FIG. 7C is a cross-sectional view illustrating a method of fabricating a metal interconnection structure of a semiconductor device according to an embodiment of the inventive concept.

[0128] refer to Figure 5C , Fig. 6A and Fig. 7A After forming the active contact AC and the gate contact GC, respectively, a first etch stop layer EST1 may be formed on the second interlayer insulating layer 120. A first via insulating layer 1301 located on the first etch stop layer EST1, a first pattern insulating layer 1302 located on the first via insulating layer 1301, a first conductive via VI1 penetrating (i.e., extending through) the first via insulating layer 1301, a first interconnection pattern M1_Ia located on the first conductive via VI1, a second etch stop layer EST2 located on the first interconnection pattern M1_Ia, a second via insulating layer 1401 located on the second etch stop layer EST2, and a first trench TR1 extending into the second etch stop layer EST2 and the second via insulating layer 1401 in the third direction D3 may be provided. The first interconnection pattern M1_Ia may include ruthenium (Ru). The first conductive via VI1 and the first interconnection pattern M1_Ia may be formed by a semi-damascene process and a ruthenium etching process.

[0129] With respect to the substrate 100 (see Figure 5C), the bottom surface EST2_BS of the second etch stop layer EST2 may be coplanar with the topmost surface M1_IaTS of the first interconnect pattern M1_Ia in the third direction D3. A portion of the topmost surface M1_IaTS of the first interconnect pattern M1_Ia may be exposed through the first trench TR1. The term "exposed" (or "exposed" or similar terms) may be used herein to describe the relationship between elements and / or with reference to intermediate processes in manufacturing semiconductor devices, but may not require that specific elements in the completed device be exposed. Similarly, the term "unexposed" may be used to describe the relationship between elements and / or with reference to intermediate processes in manufacturing semiconductor devices, but may not require that specific elements be unexposed in the completed device. The side surface of the first trench TR1 may be inclined at an angle. A portion of the topmost surface M1_IaTS of the first interconnect pattern M1_Ia may be exposed through the bottom surface TR1_BS of the first trench TR1.

[0130] refer to Figure 7B and Figure 7C , the first interconnection pattern M1_Ia can be connected through the first trench TR1 ( Fig. 7A ) is subjected to an oxidation process or RuO selectively performed on the topmost surface M1_IaTS exposed by the bottom surface TR1_BS. 2 As a result, the diffusion preventing pattern ISTA may be partially formed in the first trench TR1. The diffusion preventing pattern ISTA may be formed of or include ruthenium oxide. The diffusion preventing pattern ISTA may be formed of RuO 2 Forming or including RuO 2 .

[0131] During the formation of the diffusion prevention pattern ISTA, a portion of the first interconnection pattern M1_Ia adjacent to the exposed topmost surface M1_IaTS may be oxidized. Figure 5C ), the bottommost surface ISTA_BS of the diffusion prevention pattern ISTA may be located at a height lower than the topmost surface M1_IaTS of the first interconnection pattern M1_Ia in the third direction D3. Figure 5C ), the height of the bottommost surface ISTA_BS of the diffusion prevention pattern ISTA may be lower than the height of the bottom surface EST2_BS of the second etch stop layer EST2 in the third direction D3. The diffusion prevention pattern ISTA may be formed so that relative to the substrate 100 (see Figure 5C ), a height of a top surface ISTA_TS of the diffusion prevention pattern ISTA is lower than a height of a top surface EST2_TS of the second etch stop layer EST2 in the third direction D3.

[0132] refer to Figure 7C , the selection barrier pattern BSLa may be formed to conformally cover the side surfaces and top surfaces of the first trench TR1. The term "conformally" (or "conformal" or similar terms) as used herein in the context of a material layer or coating is intended to broadly refer to a material layer or coating having a substantially uniform cross-sectional thickness relative to the profile of the surface coated with the material layer. The top surface ISTA_TS of the diffusion prevention pattern ISTA may be in contact with the bottom surface BSLa_BS of the selection barrier pattern BSLa. As a result of the formation of the diffusion prevention pattern ISTA, a second trench TR2 may be formed.

[0133] Return to reference Fig. 6A , the second conductive via VI2a may be formed to fill the second trench TR2. The second interconnection pattern M2_Ia may be formed on the second conductive via VI2a. In an embodiment, the second conductive via VI2a and the second interconnection pattern M2_Ia may be formed by forming a copper seed layer and performing an electroplating process.

[0134] FIG. 8A to FIG. 8C is a diagram illustrating a method of manufacturing a Figure 6B A cross-sectional view of an intermediate process in an exemplary method of a semiconductor device. In detail, FIG. 8A to FIG. 8C is a cross-sectional view illustrating a method of manufacturing a metal interconnection structure of a semiconductor device according to an embodiment of the inventive concept. For brevity of description, previously described elements may be identified by the same reference numerals without repeating their repeated descriptions.

[0135] refer to Fig. 8A , a third interlayer insulating layer 130 including a first via insulating layer 1301 and a first pattern insulating layer 1302 may be formed on the first etch stop layer EST1. Thereafter, a first via VI1b may be formed to penetrate (i.e., extend through) the first via insulating layer 1301 in a third direction D3. The first interconnection pattern M1_Ib may be formed to penetrate the first pattern insulating layer 1302 in the third direction D3. A second etch stop layer EST2 may be formed on the first interconnection pattern M1_Ib and the first pattern insulating layer 1302. A second via insulating layer 1401 may be formed on the second etch stop layer EST2. A groove (not shown) may be formed to penetrate the second via insulating layer 1401, and then, a second via VI2b may be formed in the groove. A top surface of the second via VI2b may be exposed to the outside of the second via insulating layer 1401. The second via VI2b and the first interconnection pattern M1_Ib may be formed of or include ruthenium (Ru).

[0136] refer to Figure 8BThe diffusion prevention pattern ISTb may be formed on the exposed second via VI2b. For example, the upper portion of the exposed second via VI2b may be selectively oxidized, or RuO may be deposited on the second via VI2b. 2 As a result, the diffusion preventing pattern ISTb may be formed on the second via VI2b. The diffusion preventing pattern ISTb may include ruthenium oxide. In an embodiment, the diffusion preventing pattern ISTb may be made of RuO 2 Forming or including RuO 2 .

[0137] The upper portion of the second via VI2b exposed in the process of forming the diffusion prevention pattern ISTb may be selectively oxidized. In this case, the top surface VI2b_TS of the second via VI2b may be in contact with the bottom surface ISTb_BS of the diffusion prevention pattern ISTb. Figure 5C ), the height of the top surface 1401_TS of the second via insulating layer 1401 may be higher than the height of the top surface VI2b_TS of the second via VI2b in the third direction D3. Figure 5C ), the height of the top surface 1401_TS of the second via insulating layer 1401 may be higher than the height of the bottom surface ISTb_BS of the diffusion prevention pattern ISTb in the third direction D3. Figure 5C ), a height of a top surface 1401_TS of the second via insulating layer 1401 may be lower than a height of a top surface ISTb_TS of the diffusion preventing pattern ISTb in the third direction D3.

[0138] refer to Figure 8C , the selection barrier pattern BSLb may be conformally formed on the second via insulating layer 1401. A bottom surface BSLb_BS of the selection barrier pattern BSLb may be in contact with a top surface 1401_TS of the second via insulating layer 1401. Figure 5C ), the height of the bottom surface BSLb_BS of the selection blocking pattern BSLb may be higher than the height of the bottom surface ISTb_BS of the diffusion prevention pattern ISTb in the third direction D3. The selection blocking pattern BSLb may be deposited so that relative to the substrate 100 (see Figure 5C ), a height of the top surface BSLb_TS is lower than a height of the top surface ISTb_TS of the diffusion prevention pattern ISTb in the third direction D3.

[0139] Return to reference Figure 6B, the second interconnection pattern M2_Ib may be formed to cover the diffusion prevention pattern ISTb and the selection barrier pattern BSLb. In an embodiment, the second interconnection pattern M2_Ib may be formed by depositing copper.

[0140] 9A to 9D is a diagram illustrating a method of manufacturing a Figure 6C A cross-sectional view of an intermediate process in an exemplary method of a semiconductor device. In detail, 9A to 9D is a cross-sectional view illustrating a method of manufacturing a metal interconnection structure of a semiconductor device according to an embodiment of the inventive concept. For brevity of description, previously described elements may be identified by the same reference numerals without repeating their repeated descriptions.

[0141] refer to Fig. 9A , a first via insulating layer 1301 may be formed on the first etch stop layer EST1. A groove (not shown) may be formed on the first etch stop layer EST1 to penetrate the first via insulating layer 1301. A first via VI1c may be formed to fill the groove (not shown). The first via VI1c may be formed of or include a metal material. The first via VI1c may be formed of or include, for example, at least one of W, Ru, Mo, or Co. A diffusion prevention pattern ISTc may be formed on the first via VI1c. The diffusion prevention pattern ISTc may be formed of, for example, Ru / RuO 2 Forming or including, for example, Ru / RuO 2 . With respect to the substrate 100 (see Figure 5C ), the height of the top surface ISTc_TS of the diffusion prevention pattern ISTc may be higher than the height of the top surface 1301_TS of the first via insulating layer 1301 in the third direction D3. Figure 5C ), a height of a bottom surface ISTc_BS of the diffusion preventing pattern ISTc may be lower than a height of a top surface 1301_TS of the first via insulating layer 1301 in the third direction D3.

[0142] refer to Fig. 9B, a first pattern insulating layer 1302 may be formed on the first via insulating layer 1301. In an embodiment, an etch stop layer (not shown) may be formed on the first via insulating layer 1301, and then, the first pattern insulating layer 1302 may be formed thereon. Thereafter, a pattern trench PTR may be formed by patterning the first pattern insulating layer 1302. In an embodiment, the formation of the pattern trench PTR may include selectively etching the first pattern insulating layer 1302 without etching the diffusion prevention pattern ISTc. As a result, a portion of a top surface 1302_TS of the first pattern insulating layer 1302 and a top surface ISTc_TS of the diffusion prevention pattern ISTc may be exposed to the outside.

[0143] A preliminary selection barrier pattern pBSLc may be formed to conformally cover the top surface 1302_TS of the first pattern insulation layer 1302 exposed to the outside and the side surface of the first pattern insulation layer 1302. The preliminary selection barrier pattern pBSLc may contact the side surface of the diffusion prevention pattern ISTc. The preliminary selection barrier pattern pBSLc may be deposited to expose the top surface ISTc_TS of the diffusion prevention pattern ISTc. As a result of forming the preliminary selection barrier pattern pBSLc, a blocking trench BTR may be defined. The diffusion prevention pattern ISTc may have a width ISTc_TSW at a height of the exposed top surface ISTc_TS of the diffusion prevention pattern ISTc in the first direction D1.

[0144] refer to Fig. 9C , a preliminary first interconnection pattern pM1_Ic may be formed on the preliminary selection barrier pattern pBSLc. The preliminary first interconnection pattern pM1_Ic may be formed to fill the barrier trench BTR and cover the preliminary selection barrier pattern pBSLc. The barrier trench BTR filled with the preliminary first interconnection pattern pM1_Ic may define a width M1_IcW of the preliminary first interconnection pattern pM1_Ic to be formed in a subsequent step in the first direction D1. The preliminary first interconnection pattern pM1_Ic may include copper. The width M1_IcW of the preliminary first interconnection pattern pM1_Ic in the first direction D1 may be greater than a width ISTc_TSW of the diffusion prevention pattern ISTc in the first direction D1 measured at a height of the top surface ISTc_TS.

[0145] refer to Fig.9D, the preliminary selection barrier pattern pBSLc and the preliminary first interconnection pattern pM1_Ic may be etched to the height of the top surface 1302_TS of the first pattern insulation layer 1302. The preliminary first interconnection pattern pM1_Ic may be etched to fill the blocking trench BTR. The preliminary first interconnection pattern pM1_Ic and the selection barrier pattern BSLc may be formed. In this case, the top surface 1302_TS of the first pattern insulation layer 1302, the top surface BSLc_TS of the selection barrier pattern BSLc, and the top surface of the preliminary first interconnection pattern pM1_Ic may be exposed.

[0146] Return to reference Figure 6C , a second etch stop layer EST2, a second via insulating layer 1401, a second via VI2c and a second interconnection pattern M2_Ic may be formed on the exposed top surface 1302_TS of the first pattern insulating layer 1302, the exposed top surface BSLc_TS of the selection blocking pattern BSLc and the exposed top surface of the preliminary first interconnection pattern pM1_Ic.

[0147] FIG. 10A to FIG. 10C is a diagram illustrating a method of manufacturing a Fig.6D A cross-sectional view of an intermediate process in an exemplary method of a semiconductor device. In detail, FIG. 10A to FIG. 10C is a cross-sectional view illustrating a method of manufacturing a metal interconnection structure of a semiconductor device according to an embodiment of the inventive concept. For brevity of description, previously described elements may be identified by the same reference numerals without repeating their repeated descriptions.

[0148] refer to Fig. 10A , a first etch stop layer EST1 may be formed on the second interlayer insulating layer 120. A first via insulating layer 1301 located on the first etch stop layer EST1, a first pattern insulating layer 1302 located on the first via insulating layer 1301, a first via VI1d penetrating the first via insulating layer 1301, a first interconnection pattern M1_Id located on the first via VI1d, a second etch stop layer EST2 located on the first interconnection pattern M1_Id, a second via insulating layer 1401 located on the second etch stop layer EST2, and a first hole (i.e., opening) H1 penetrating (i.e., extending into or through) the second etch stop layer EST2 and the second via insulating layer 1401 in a third direction D3 may be provided. The first interconnection pattern M1_Id may be formed of or include copper. The formation of the first via VI1 and the first interconnection pattern M1_Ia may be formed by a damascene process and an electroplating process. The first interconnection pattern M1_Id may be formed to have a bottom surface M1_IdBS coplanar with the top surface 1301_TS of the first via insulating layer 1301 in the third direction D3 .

[0149] A portion of the topmost surface M1_IdTS of the first interconnection pattern M1_Id may be exposed through the first hole H1. A side surface of the first hole H1 may be inclined at an angle.

[0150] refer to Fig. 10B , a ruthenium layer may be selectively deposited on the topmost surface M1_IdTS of the first interconnection pattern M1_Id. In this case, the diffusion prevention pattern ISTd may be formed in the first hole H1. The diffusion prevention pattern ISTd may be formed to have a relative thickness to the substrate 100 ( Figure 5C ) is lower than the top surface of the top surface EST2_TS of the second etch stop layer EST2 in the third direction D3. The diffusion prevention pattern ISTd may be formed of or include ruthenium oxide. In an embodiment, the diffusion prevention pattern ISTd may be formed of Ru / RuO 2 Forming or including Ru / RuO 2 .

[0151] In the process of forming the diffusion prevention pattern ISTd, a portion of the first interconnection pattern M1_Id adjacent to the exposed topmost surface M1_IdTS may be oxidized and then removed. Figure 5C ), the height of the bottommost surface ISTd_BS of the diffusion prevention pattern ISTd may be lower than the height of the topmost surface M1_IdTS of the first interconnection pattern M1_Id in the third direction D3. Figure 5C ), a height of the top surface ISTA_TS of the diffusion prevention pattern ISTA may be lower than a height of the top surface EST2_TS of the second etch stop layer EST2 in the third direction D3.

[0152] refer to Fig. 10C , the second conductive via VI2d may be formed to fill the first hole H1. The top surface ISTd_TS of the diffusion prevention pattern ISTd may be covered by the second conductive via VI2d. The second conductive via VI2d may be formed of or include ruthenium (Ru).

[0153] Return to reference Fig.6D , the second interconnection pattern M2_Id may be formed on the second conductive via VI2d. The second interconnection pattern M2_Id may be formed by performing a ruthenium etching process.

[0154] According to an embodiment of the present invention, a three-dimensional field effect transistor may include a diffusion prevention pattern, which is between a metal pattern and a conductive path and contains ruthenium oxide. Therefore, diffusion between the metal pattern and the conductive path can be prevented. In addition, since the diffusion prevention pattern has a low resistance, the electrical characteristics and reliability characteristics of the semiconductor device can be improved.

[0155] While example embodiments of the inventive concepts have been particularly shown and described, it will be understood by those skilled in the art that changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: a substrate comprising an active pattern; a channel pattern located on the active pattern and including a plurality of semiconductor patterns stacked in a vertical direction perpendicular to an upper surface of the substrate and spaced apart from each other in the vertical direction; a gate electrode, the gate electrode being located on the plurality of semiconductor patterns; a gate contact electrically connected to the gate electrode; a first metal layer, the first metal layer being located on the gate contact and comprising a first conductive path and a first interconnect pattern located on the first conductive path; a second metal layer, the second metal layer being located on the first metal layer and comprising a second conductive path and a second interconnection pattern located on the second conductive path; as well as a diffusion prevention pattern located between the first interconnection pattern and the second conductive path, Wherein, with respect to the upper surface of the substrate, a height of a bottom surface of the diffusion prevention pattern is lower than a height of a topmost surface of the first interconnection pattern in the vertical direction.

2. The semiconductor device according to claim 1, wherein The diffusion preventing pattern includes RuO 2 or Ru / RuO 2 .

3. The semiconductor device according to claim 1, wherein The first interconnect pattern includes ruthenium, and The second conductive path includes copper or molybdenum.

4. The semiconductor device according to claim 1, wherein The first interconnect pattern includes copper, and The second conductive path includes ruthenium.

5. The semiconductor device according to claim 1, wherein A width of the first interconnection pattern in a horizontal direction parallel to the upper surface of the substrate is greater than a width of the bottom surface of the diffusion prevention pattern in the horizontal direction.

6. The semiconductor device according to claim 1, wherein The first metal layer includes a first etch stop layer in contact with the first conductive path, The second metal layer includes a second etch stop layer located on the first interconnect pattern, and With respect to the upper surface of the substrate, a height of a top surface of the diffusion prevention pattern is lower than a height of a top surface of the first etch stop layer in the vertical direction.

7. The semiconductor device according to claim 6, further comprising a selection barrier pattern extending around the second interconnection pattern and the second conductive path, in, The selection blocking pattern is located on a side surface of the second conductive via.

8. The semiconductor device according to claim 7, wherein: A bottom surface of the selection barrier pattern contacts a top surface of the diffusion prevention pattern.

9. The semiconductor device according to claim 7, wherein: A top surface of the diffusion prevention pattern contacts the selection barrier pattern and the second conductive path, and A side surface of the diffusion prevention pattern contacts the second etch stop layer and the first interconnection pattern.

10. A semiconductor device, comprising: a substrate comprising an active pattern; a channel pattern located on the active pattern and including a plurality of semiconductor patterns stacked in a vertical direction perpendicular to an upper surface of the substrate and spaced apart from each other in the vertical direction; a source / drain pattern connected to the channel pattern; a gate electrode, the gate electrode being located on the plurality of semiconductor patterns; an active contact electrically connected to the source / drain pattern; a metal interconnect structure located on the active contact and comprising a conductive path and an interconnect pattern located on the conductive path; as well as a diffusion preventing pattern located between the interconnection pattern and the conductive path, wherein, relative to the upper surface of the substrate, a height of a top surface of the diffusion prevention pattern is different in the vertical direction from a height of a bottommost surface of the interconnection pattern in contact with the diffusion prevention pattern, and The diffusion preventing pattern includes ruthenium oxide.

11. The semiconductor device according to claim 10, further comprising: a via insulation layer extending around the conductive via; as well as a selection barrier pattern, the selection barrier pattern being located between the via insulating layer and the interconnection pattern, Wherein, with respect to the upper surface of the substrate, a height of the top surface of the diffusion prevention pattern is lower than a height of the top surface of the selection blocking pattern in the vertical direction.

12. The semiconductor device according to claim 11, wherein The selection barrier pattern includes tantalum nitride, and The interconnection pattern and the conductive via include materials different from each other.

13. The semiconductor device according to claim 10, wherein: The metal interconnect structure comprises a first metal layer and a second metal layer located on the first metal layer, The conductive path includes a first conductive path located in the first metal layer and a second conductive path located in the second metal layer, The interconnection pattern includes a first interconnection pattern located in the first metal layer and a second interconnection pattern located in the second metal layer, and The diffusion prevention pattern is located between the second conductive via and the second interconnection pattern.

14. The semiconductor device according to claim 13, further comprising a selection barrier pattern in contact with a side surface of the diffusion prevention pattern, in, A top surface of the selection blocking pattern has a height lower than a height of the top surface of the diffusion preventing pattern in the vertical direction with respect to the upper surface of the substrate.

15. The semiconductor device according to claim 10, wherein The metal interconnect structure comprises a first metal layer and a second interconnect layer located on the first metal layer, The conductive path includes a first conductive path located in the first metal layer and a second conductive path located in the second metal layer, The interconnection pattern includes a first interconnection pattern located in the first metal layer and a second interconnection pattern located in the second metal layer, and The diffusion prevention pattern is located between the first conductive via and the first interconnection pattern.

16. The semiconductor device according to claim 15, further comprising: a first pattern insulation layer, the first pattern insulation layer extending around the first interconnection pattern; a first via insulating layer extending around the first conductive via; as well as a selection barrier pattern, the selection barrier pattern being located between the first pattern insulation layer and the first interconnection pattern and between the first via insulation layer and the first interconnection pattern, Wherein, a side surface of the diffusion prevention pattern contacts the first interconnection pattern, the selection barrier pattern, and the first via insulating layer.

17. The semiconductor device according to claim 15, further comprising: a selection barrier pattern extending around a portion of a bottom surface of the first interconnection pattern and a side surface of the first interconnection pattern; as well as an etch stop layer, the etch stop layer being located on the first interconnect pattern, Wherein, the topmost surface of the selection blocking pattern is coplanar with the bottom surface of the etching stop layer in the vertical direction.

18. A semiconductor device, comprising: a substrate comprising an active pattern; a device isolation layer, wherein the device isolation layer defines the active pattern; a channel pattern located on the active pattern and including a plurality of semiconductor patterns stacked in a vertical direction perpendicular to an upper surface of the substrate and spaced apart from each other in the vertical direction; a gate electrode, the gate electrode being located on the plurality of semiconductor patterns; a gate insulating layer, the gate insulating layer being located between the gate electrode and an adjacent semiconductor pattern among the semiconductor patterns; a gate contact electrically connected to the gate electrode; a first metal layer located on the substrate and comprising a first conductive path, a first interconnection pattern located on the first conductive path, and a first path insulating layer extending around the first conductive path; a second metal layer, the second metal layer being located on the first metal layer and comprising a second conductive path and a second interconnection pattern located on the second conductive path; a diffusion prevention pattern located between the first conductive path and the first interconnection pattern; as well as a selection barrier pattern extending around a portion of a bottom surface of the first interconnection pattern and a side surface of the first interconnection pattern, Wherein, a side surface of the diffusion prevention pattern contacts the first interconnection pattern, the selection barrier pattern, and the first via insulating layer.

19. The semiconductor device according to claim 18, wherein: The selection barrier pattern includes tantalum nitride.

20. The semiconductor device according to claim 18, wherein The diffusion preventing pattern includes ruthenium oxide, The first conductive path includes ruthenium, and The first interconnection pattern includes copper.

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