Semiconductor structure and preparation method thereof

Abstract

The embodiment of the invention discloses a semiconductor structure and a preparation method thereof, and the semiconductor structure comprises a substrate, the surface of which is provided with a plurality of grooves which are arranged along a first direction and extend along a second direction; wherein the second direction is the channel length direction, the first direction and the second direction intersect, and the first direction and the second direction are parallel to the substrate plane; the channel layer is located on the substrate and covers the side wall and the bottom of the groove; and the gate structure is located on the channel layer and fills the groove.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] As the size of liquid crystal displays continues to increase, the driving frequency continues to increase, and the requirements for the electron mobility of traditional amorphous silicon thin film transistors are also increasing, and at the same time, a larger saturation current Idsat is also required. To increase the saturation current, the width of the gate oxide layer can be increased or the length of the gate oxide layer can be reduced, but due to the short channel effect, the length of the gate oxide layer is difficult to reduce. Summary of the invention

[0003] In view of this, an embodiment of the present disclosure provides a semiconductor structure and a method for manufacturing the same.

[0004] According to a first aspect of an embodiment of the present disclosure, there is provided a semiconductor structure, including:

[0005] A substrate, wherein a plurality of grooves arranged along a first direction and extending along a second direction are formed on a surface of the substrate; wherein the second direction is a channel length direction, the first direction intersects with the second direction, and the first direction and the second direction are parallel to the substrate plane;

[0006] A channel layer, located on the substrate and covering the sidewall and bottom of the groove;

[0007] The gate structure is located on the channel layer and fills the groove.

[0008] In some embodiments, the gate structure includes: a gate oxide layer and a gate conductive layer located on the gate oxide layer;

[0009] The sum of the heights of the gate oxide layer and the channel layer along a direction perpendicular to the substrate plane is smaller than the height of the groove along a direction perpendicular to the substrate plane.

[0010] In some embodiments, along the first direction, the distance between two adjacent grooves is in the range of 10-20 nm.

[0011] In some embodiments, the height of the groove along the direction perpendicular to the substrate ranges from 5 to 10 nm, and the width of the groove along the first direction ranges from 10 to 20 nm.

[0012] In some embodiments, it also includes:

[0013] A first source / drain region and a second source / drain region are respectively located on the channel layer at two sides of the gate structure along the second direction.

[0014] According to a second aspect of an embodiment of the present disclosure, a method for preparing a semiconductor structure is provided, comprising:

[0015] providing a substrate;

[0016] A plurality of grooves arranged along a first direction and extending along a second direction are formed on the surface of the substrate; wherein the second direction is a channel length direction, the first direction intersects with the second direction, and the first direction and the second direction are parallel to the substrate plane;

[0017] forming a channel layer on the substrate, wherein the channel layer covers the sidewall and the bottom of the groove;

[0018] A gate structure is formed on the channel layer, and the gate structure fills the groove.

[0019] In some embodiments, forming the gate structure includes:

[0020] sequentially forming a gate oxide layer and a gate conductive layer located on the gate oxide layer;

[0021] The sum of the heights of the gate oxide layer and the channel layer along a direction perpendicular to the substrate plane is smaller than the height of the groove along a direction perpendicular to the substrate plane.

[0022] In some embodiments, along the first direction, the distance between two adjacent grooves is in the range of 10-20 nm.

[0023] In some embodiments, the height of the groove along the direction perpendicular to the substrate ranges from 5 to 10 nm, and the width of the groove along the first direction ranges from 10 to 20 nm.

[0024] In some embodiments, it also includes:

[0025] A first source / drain region and a second source / drain region are formed, wherein the first source / drain region and the second source / drain region are respectively located on the channel layer at two sides of the gate structure along the second direction.

[0026] In the embodiment of the present disclosure, a plurality of grooves extending along the channel length direction are formed on the surface of the substrate, and then a channel layer and a gate structure are formed in the grooves. In this way, the contact area between the channel layer and the gate structure in the width direction is increased, thereby increasing the width of the transistor and thus increasing the current. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the conventional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0028] Figure 1 A schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure;

[0029] Figure 2 For along Figure 1 A cross-sectional view along the A-A' direction;

[0030] Figure 3 A flow chart of a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0031] Figures 4a to 7b A schematic diagram of the structure of a semiconductor structure during the preparation process provided by an embodiment of the present disclosure.

[0032] Description of reference numerals:

[0033] Substrate, 10; bottom substrate, 11; buried oxide layer, 12;

[0034] groove, 20;

[0035] channel layer, 30;

[0036] Gate structure, 40; gate oxide layer, 41; gate conductive layer, 42;

[0037] A first source / drain region, 51 ; and a second source / drain region, 52 . DETAILED DESCRIPTION

[0038] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0039] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0040] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0041] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0042] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0043] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0044] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below, but in addition to these detailed descriptions, the present disclosure may also have other implementations.

[0045] In the related art, the current value of the transistor can be obtained by the following formula (1).

[0046]

[0047] Among them, Un represents the migration rate of electrons, Cox represents the capacitance of the gate oxide layer per unit area, W / L represents the ratio of the width to the length of the gate oxide layer, and Vgs-Vth represents the driving voltage. It can be seen from formula (1) that the current can be increased by increasing the width of the gate oxide layer or reducing the length of the gate oxide layer, but due to the short channel effect, it is difficult to reduce the length of the gate oxide layer.

[0048] Based on this, an embodiment of the present disclosure provides a semiconductor structure. Figure 1 A schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure, Figure 2 For along Figure 1 Cross-sectional view along the A-A' direction.

[0049] See also Figure 1 and Figure 2 , the semiconductor structure comprises:

[0050] A substrate 10, wherein a plurality of grooves 20 arranged along a first direction and extending along a second direction are formed on the surface of the substrate 10; wherein the second direction is a channel length direction, the first direction intersects with the second direction, and the first direction and the second direction are parallel to the plane of the substrate 10;

[0051] A channel layer 30 is located on the substrate 10 and covers the sidewall and bottom of the groove 20;

[0052] The gate structure 40 is located on the channel layer 30 and fills the groove 20 .

[0053] In the embodiment of the present disclosure, a plurality of grooves extending along the channel length direction are formed on the surface of the substrate, and then a channel layer and a gate structure are formed in the grooves. In this way, the contact area between the channel layer and the gate structure in the width direction is increased, thereby increasing the width of the transistor and thus increasing the current.

[0054] In one embodiment, the substrate 10 may be a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, an SOI (Silicon On Insulator) substrate, or a GOI (Germanium On Insulator) substrate, etc. It may also be a substrate including other element semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (such as a gallium nitride substrate or a gallium arsenide substrate, etc.), it may also be a stacked structure, such as Si / SiGe, etc., and it may also be other epitaxial structures, such as SGOI (Silicon Germanium On Insulator), etc.

[0055] In the embodiment of the present disclosure, the substrate 10 includes a base substrate 11 and a buried oxide layer 12 located on the base substrate 11. The material of the base substrate 11 includes but is not limited to silicon (Si), and the material of the buried oxide layer 12 includes but is not limited to silicon dioxide (SiO2).

[0056] like Figure 2 As shown, a plurality of grooves 20 arranged along a first direction and extending along a second direction are formed on the surface of the substrate 10, wherein the second direction is the channel length direction, the first direction intersects with the second direction, and the first direction and the second direction are parallel to the plane of the substrate 10.

[0057] The channel length direction is the direction from the source to the drain, or the direction from the drain to the source.

[0058] In some embodiments, Figure 1 and Figure 2 As shown, the first direction and the second direction are perpendicular to each other.

[0059] In some other embodiments, the angle between the first direction and the second direction is less than 90 degrees.

[0060] In one embodiment, along the first direction, the distance between two adjacent grooves 20 is in the range of 10-20 nm.

[0061] In the disclosed embodiment, when the spacing between two adjacent grooves is 10-20nm, the contact area between the channel layer and the gate structure in the width direction can be increased, thereby increasing the width of the transistor and thus increasing the current, and the stability of the device structure can be ensured. Because if the spacing between two adjacent grooves is too small, the pattern between the two grooves will be too narrow, which is easy to cause collapse and poor stability; and if the spacing between two adjacent grooves is too large, the number of grooves will be too small, affecting the width of the channel layer and the gate structure.

[0062] In one embodiment, the height of the groove 20 along the direction perpendicular to the substrate 10 is in the range of 5-10 nm, and the width of the groove 20 along the first direction is in the range of 10-20 nm.

[0063] In the disclosed embodiment, when the height range of the groove is 5-10nm and the width range is 10-20nm, it can increase the contact area between the channel layer and the gate structure in the width direction, thereby increasing the width of the transistor and thus increasing the current, while ensuring the stability of the device structure.

[0064] In some embodiments, Figure 2 As shown, the shape of the groove 20 is a trapezoid. It is understandable that the shape of the groove is a trapezoid only as a lower, feasible specific implementation in the embodiment of the present disclosure, and does not constitute a limitation of the present disclosure. The shape of the groove may also be other shapes, for example, a rectangle, a triangle or some irregular shapes.

[0065] In one embodiment, the channel layer 30 is located on the substrate 10 and covers the sidewall and the bottom of the groove 20 .

[0066] In one embodiment, the material of the channel layer 30 may be an oxide semiconductor material, including but not limited to at least one of indium oxide, tin oxide, In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, In-Ga oxide, In-Ga-Zn oxide, In-Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, and Sn-Al-Zn oxide.

[0067] In a specific embodiment, the material of the channel layer 30 includes but is not limited to indium gallium zinc oxide (IGZO). The thickness of the channel layer 30 may range from 1 nm to 20 nm, such as 5 nm, 10 nm, 15 nm, 18 nm, etc. In some embodiments, the ratio of indium (In), gallium (Ga), and zinc (Zn) may be 1:1:1 or 2:2:1, etc. However, it is not limited thereto, and the ratio of indium (In), gallium (Ga), and zinc (Zn) may also be other suitable ratios.

[0068] It can be understood that when the material of the channel layer 30 is indium gallium zinc oxide (IGZO), the semiconductor device has the advantages of fast access speed, low cut-off current and low power consumption.

[0069] Optionally, the oxide semiconductor material may be an undoped oxide semiconductor material or a doped oxide semiconductor material.

[0070] In one embodiment, the gate structure 40 is located on the channel layer 30 and fills the groove 20 .

[0071] The gate structure 40 includes: a gate oxide layer 41 and a gate conductive layer 42 located on the gate oxide layer 41;

[0072] The sum of the heights of the gate oxide layer 41 and the channel layer 30 along a direction perpendicular to the plane of the substrate 10 is smaller than the height of the groove 20 along a direction perpendicular to the plane of the substrate 10 .

[0073] In the disclosed embodiment, the sum of the heights of the gate oxide layer and the channel layer is less than the height of the groove. Therefore, the gate oxide layer and the channel layer can be more located in the groove, thereby increasing the contact area between the gate oxide layer and the channel layer, thereby reducing the current.

[0074] The material of the gate oxide layer 41 includes but is not limited to oxide. In a specific embodiment, the material of the gate oxide layer 41 can be silicon oxide.

[0075] The material of the gate conductive layer 42 includes one or more of tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, and metal alloy. In a specific embodiment, the material of the gate conductive layer 42 can be titanium nitride.

[0076] In one embodiment, the semiconductor structure further includes: a first source / drain region 51 and a second source / drain region 52 , which are respectively located on the channel layer 30 at two sides of the gate structure 40 along the second direction.

[0077] In some embodiments, the first source / drain region 51 is a source region, and the second source / drain region 52 is a drain region.

[0078] In some other embodiments, the first source / drain region 51 is a drain region, and the second source / drain region 52 is a source region.

[0079] The material of the first source / drain region 51 and the second source / drain region 52 is one or more of titanium nitride (TiN), tantalum nitride (TaN), titanium (Ti), copper, gold, aluminum or molybdenum (Mo).

[0080] The present disclosure also provides a method for preparing a semiconductor structure. Figure 3 ,like Figure 3 As shown, the method comprises the following steps:

[0081] Step 301: providing a substrate;

[0082] Step 302: forming a plurality of grooves arranged along a first direction and extending along a second direction on the surface of the substrate; wherein the second direction is a channel length direction, the first direction intersects with the second direction, and the first direction and the second direction are parallel to the substrate plane;

[0083] Step 303: forming a channel layer on the substrate, wherein the channel layer covers the sidewall and bottom of the groove;

[0084] Step 304: forming a gate structure on the channel layer, wherein the gate structure fills the groove.

[0085] The method for preparing the semiconductor structure provided by the embodiment of the present disclosure is further described in detail below in conjunction with specific embodiments.

[0086] Figures 4a to 7b This is a schematic diagram of the structure of the semiconductor structure provided in the embodiment of the present disclosure during the preparation process. It should be explained that: Figure 4b , Figure 5b , Figure 6b and Figure 7b Along Figure 4a , Figure 5a , Figure 6a and Figure 7a Cross-sectional view along the A-A' direction.

[0087] See first Figure 4a and Figure 4b , execute step 301 and provide a substrate 10.

[0088] In one embodiment, the substrate 10 may be a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, an SOI (Silicon On Insulator) substrate, or a GOI (Germanium On Insulator) substrate, etc. It may also be a substrate including other element semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (such as a gallium nitride substrate or a gallium arsenide substrate, etc.), it may also be a stacked structure, such as Si / SiGe, etc., and it may also be other epitaxial structures, such as SGOI (Silicon Germanium On Insulator), etc.

[0089] In the embodiment of the present disclosure, the substrate 10 includes a base substrate 11 and a buried oxide layer 12 located on the base substrate 11. The material of the base substrate 11 includes but is not limited to silicon (Si), and the material of the buried oxide layer 12 includes but is not limited to silicon dioxide (SiO2).

[0090] Next, see Figure 5a and Figure 5b, execute step 302 to form a plurality of grooves 20 arranged along a first direction and extending along a second direction on the surface of the substrate 10; wherein the second direction is the channel length direction, the first direction intersects with the second direction, and the first direction and the second direction are parallel to the plane of the substrate 10.

[0091] In actual operation, a mask layer may be first grown on the upper surface of the substrate 10, and then the mask layer may be patterned to display the groove pattern to be etched on the mask layer, and the mask layer may be patterned by a photolithography process. The mask layer may be a photoresist mask or a hard mask patterned based on a photolithography mask; when the mask layer is a photoresist mask, the mask layer is patterned by steps such as exposure, development, and degumming. Then, a groove having a certain depth is etched according to the groove pattern to be etched.

[0092] The channel length direction is the direction from the source to the drain, or the direction from the drain to the source.

[0093] In some embodiments, Figure 5a and Figure 5b As shown, the first direction and the second direction are perpendicular to each other.

[0094] In some other embodiments, the angle between the first direction and the second direction is less than 90 degrees.

[0095] In one embodiment, along the first direction, the distance between two adjacent grooves 20 is in the range of 10-20 nm.

[0096] In the disclosed embodiment, when the spacing between two adjacent grooves is 10-20nm, the contact area between the channel layer and the gate structure in the width direction can be increased, thereby increasing the width of the transistor and thus increasing the current, and the stability of the device structure can be ensured. Because if the spacing between two adjacent grooves is too small, the pattern between the two grooves will be too narrow, which is easy to cause collapse and poor stability; and if the spacing between two adjacent grooves is too large, the number of grooves will be too small, affecting the width of the channel layer and the gate structure.

[0097] In one embodiment, the height of the groove 20 along the direction perpendicular to the substrate 10 is in the range of 5-10 nm, and the width of the groove 20 along the first direction is in the range of 10-20 nm.

[0098] In the disclosed embodiment, when the height range of the groove is 5-10nm and the width range is 10-20nm, it can increase the contact area between the channel layer and the gate structure in the width direction, thereby increasing the width of the transistor and thus increasing the current, while ensuring the stability of the device structure.

[0099] In some embodiments, Figure 5b As shown, the shape of the groove 20 is a trapezoid. It is understandable that the shape of the groove is a trapezoid only as a lower, feasible specific implementation in the embodiment of the present disclosure, and does not constitute a limitation of the present disclosure. The shape of the groove may also be other shapes, for example, a rectangle, a triangle or some irregular shapes.

[0100] Next, see Figure 6a and Figure 6b , executing step 303 , forming a channel layer 30 on the substrate 10 , wherein the channel layer 30 covers the sidewall and the bottom of the groove 20 .

[0101] In actual operation, the channel layer 30 can be formed using one or more thin film deposition processes; specifically, the deposition processes include but are not limited to any one of physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD) or a combination thereof. The physical vapor deposition process is a technology that uses physical methods under vacuum conditions to vaporize the material source and the solid or liquid surface into gaseous atoms, molecules or partially ionized ions, and deposits a thin film with a certain special function on the substrate surface through a low-pressure gas (or plasma) process; the chemical vapor deposition process is mainly a method of using one or more gas phase compounds or single substances containing thin film elements to chemically react on the substrate surface to generate a thin film; the atomic layer deposition process is a method of coating a substance on the substrate surface layer by layer in the form of a single atomic film.

[0102] In one embodiment, the material of the channel layer 30 may be an oxide semiconductor material, including but not limited to at least one of indium oxide, tin oxide, In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, In-Ga oxide, In-Ga-Zn oxide, In-Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, and Sn-Al-Zn oxide.

[0103] In a specific embodiment, the material of the channel layer 30 includes but is not limited to indium gallium zinc oxide (IGZO). The thickness of the channel layer 30 may range from 1 nm to 20 nm, such as 5 nm, 10 nm, 15 nm, 18 nm, etc. In some embodiments, the ratio of indium (In), gallium (Ga), and zinc (Zn) may be 1:1:1 or 2:2:1, etc. However, it is not limited thereto, and the ratio of indium (In), gallium (Ga), and zinc (Zn) may also be other suitable ratios.

[0104] It can be understood that when the material of the channel layer 30 is indium gallium zinc oxide (IGZO), the semiconductor device has the advantages of fast access speed, low cut-off current and low power consumption.

[0105] Optionally, the oxide semiconductor material may be an undoped oxide semiconductor material or a doped oxide semiconductor material.

[0106] Next, see Figure 7a and Figure 7b , executing step 304 , forming a gate structure 40 on the channel layer 30 , wherein the gate structure 40 fills the groove 20 .

[0107] The forming of the gate structure 40 includes:

[0108] A gate oxide layer 41 and a gate conductive layer 42 located on the gate oxide layer 41 are sequentially formed;

[0109] The sum of the heights of the gate oxide layer 41 and the channel layer 30 along a direction perpendicular to the plane of the substrate 10 is smaller than the height of the groove 20 along a direction perpendicular to the plane of the substrate 10 .

[0110] In the disclosed embodiment, the sum of the heights of the gate oxide layer and the channel layer is less than the height of the groove. Therefore, the gate oxide layer and the channel layer can be more located in the groove, thereby increasing the contact area between the gate oxide layer and the channel layer, thereby reducing the current.

[0111] In actual operation, the gate oxide layer 41 and the gate conductive layer 42 can be formed using one or more thin film deposition processes; specifically, the deposition processes include but are not limited to any one of physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD) processes or a combination thereof.

[0112] The material of the gate oxide layer 41 includes but is not limited to oxide. In a specific embodiment, the material of the gate oxide layer 41 can be silicon oxide.

[0113] The material of the gate conductive layer 42 includes one or more of tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, and metal alloy. In a specific embodiment, the material of the gate conductive layer 42 can be titanium nitride.

[0114] Next, continue to see Figure 7a and Figure 7b , the method further comprises:

[0115] A first source / drain region 51 and a second source / drain region 52 are formed. The first source / drain region 51 and the second source / drain region 52 are respectively located on the channel layer 30 at two sides of the gate structure 40 along the second direction.

[0116] In actual operation, the first source / drain region 51 and the second source / drain region 52 can be formed using one or more thin film deposition processes; specifically, the deposition processes include but are not limited to any one of physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD) processes or a combination thereof.

[0117] In some embodiments, the first source / drain region 51 is a source region, and the second source / drain region 52 is a drain region.

[0118] In some other embodiments, the first source / drain region 51 is a drain region, and the second source / drain region 52 is a source region.

[0119] The material of the first source / drain region 51 and the second source / drain region 52 is one or more of titanium nitride (TiN), tantalum nitride (TaN), titanium (Ti), copper, gold, aluminum or molybdenum (Mo).

[0120] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, wherein a plurality of grooves arranged along a first direction and extending along a second direction are formed on a surface of the substrate; wherein the second direction is a channel length direction, the first direction intersects with the second direction, and the first direction and the second direction are parallel to the substrate plane; A channel layer, located on the substrate and covering the sidewall and bottom of the groove; The gate structure is located on the channel layer and fills the groove.

2. The semiconductor structure according to claim 1, characterized in that: The gate structure comprises: a gate oxide layer and a gate conductive layer located on the gate oxide layer; The sum of the heights of the gate oxide layer and the channel layer along a direction perpendicular to the substrate plane is smaller than the height of the groove along a direction perpendicular to the substrate plane.

3. The semiconductor structure according to claim 1, characterized in that: Along the first direction, the distance between two adjacent grooves is in the range of 10-20 nm.

4. The semiconductor structure according to claim 1, characterized in that: The groove has a width of 5-10 nm along a direction perpendicular to the substrate and a width of 10-20 nm along the first direction.

5. The semiconductor structure according to claim 1, characterized in that: Also includes: A first source / drain region and a second source / drain region are respectively located on the channel layer at two sides of the gate structure along the second direction.

6. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; A plurality of grooves arranged along a first direction and extending along a second direction are formed on the surface of the substrate; wherein the second direction is a channel length direction, the first direction intersects with the second direction, and the first direction and the second direction are parallel to the substrate plane; forming a channel layer on the substrate, wherein the channel layer covers the sidewall and the bottom of the groove; A gate structure is formed on the channel layer, and the gate structure fills the groove.

7. The method according to claim 6, characterized in that The forming of the gate structure comprises: sequentially forming a gate oxide layer and a gate conductive layer located on the gate oxide layer; The sum of the heights of the gate oxide layer and the channel layer along a direction perpendicular to the substrate plane is smaller than the height of the groove along a direction perpendicular to the substrate plane.

8. The method according to claim 6, characterized in that Along the first direction, the distance between two adjacent grooves is in the range of 10-20 nm.

9. The method according to claim 6, characterized in that The height of the groove along the direction perpendicular to the substrate ranges from 5 to 10 nm, and the width of the groove along the first direction ranges from 10 to 20 nm.

10. The method according to claim 6, characterized in that Also includes: A first source / drain region and a second source / drain region are formed, wherein the first source / drain region and the second source / drain region are respectively located on the channel layer at two sides of the gate structure along the second direction.

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