Super junction preparation method and super junction structure
By forming a multi-layer epitaxial layer and trench structure in superjunction preparation, combined with gas phase etching technology, the problems of long process cycles and many defects in the existing technology are solved, and more efficient superjunction device preparation is achieved, reducing costs and defect risk, improving pressure resistance and yield.
Patent Information
- Application Number
- CN202411406773.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-09
- Publication Date
- 2025-01-14
AI Technical Summary
The existing super junction preparation methods have long process cycles, high production costs, and are prone to defects, which affect the reliability and yield of the device.
By forming a plurality of first conductive type epitaxial layers on the substrate and forming trenches therein, the second conductive type ions are injected to form a depletion layer of an alternating structure, reducing the number of repetitions, increasing the thickness of the epitaxial layer, and using gas phase etching Erosion removes damaged layers and reduces process requirements.
It reduces the process cycle, reduces production costs, reduces the probability of defect generation, and improves the voltage withstandability and product yield of super junction devices.
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Figure CN119317166A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a super junction preparation method and a super junction structure. Background Art
[0002] In super junction MOSFET (SJ MOS), the doping concentration of the device drift region is increased by setting an alternating PN column structure, thereby achieving low on-resistance. This structure can achieve charge compensation by depleting the P column and N column at a lower voltage in the off state, so that the P column and N column can achieve a high breakdown voltage at a higher doping concentration while obtaining a low on-resistance, breaking through the theoretical limit of traditional power devices. There are two main methods for preparing super junctions. The first is to form a multi-layer epitaxial layer stack (see Figure 1 ), grow an N-type epitaxial layer with a thickness of 5 to 7 μm on the substrate, form an alternating structure through photolithography and P-type ion implantation, and repeat the process of epitaxial growth, photolithography and implantation many times to achieve the required PN depletion layer thickness. Figure 1 Taking the structure as an example, multiple depletion layer thin layers 2 are formed on the substrate 1, and an alternating structure of P columns and N columns is formed in each depletion layer thin layer. Multiple depletion layer thin layers are superimposed to form a depletion layer, and the P columns in the depletion layer thin layers are superimposed up and down to form the final P column structure 3. If the thickness of the PN depletion layer is 40-50μm, the process of epitaxial growth, photolithography and injection needs to be repeated 5-7 times. This preparation method is less difficult, but it requires multiple photolithography and multiple epitaxy, which makes the process cycle long and the production cost high. The second is to use a trench filling process to deposit an N-type epitaxial layer of target thickness on a heavily doped substrate at one time, and then etch a deep trench in the N-type epitaxial layer, and finally fill the trench with a P-type epitaxial layer to form a PN depletion layer. However, this method has process difficulties when performing deep trench etching. The trench angle is straight and the depth is deep, which requires a relatively high capability of the etching equipment and is prone to defects.
[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention
[0004] In view of the problems in the prior art, the purpose of the present application is to provide a super junction preparation method and a super junction structure to reduce the process cycle, reduce the production cost, and reduce the probability of defects.
[0005] The present application provides a super junction preparation method, including:
[0006] S100: forming a first conductivity type epitaxial layer on one side of the substrate;
[0007] S200: performing photolithography on the first conductive type epitaxial layer to form a plurality of trenches;
[0008] S300: injecting second conductive type ions into the trench to form second conductive type columns, and forming first conductive type columns between two adjacent second conductive type columns to form a depletion layer with an alternating structure;
[0009] When the thickness of the depletion layer does not meet the depletion layer thickness requirement, S400: forming a first conductivity type epitaxial layer with a thickness of 10 to 11 μm on a side of the depletion layer away from the substrate, and repeating steps S200 and S300 until the thickness of the depletion layer meets the depletion layer thickness requirement.
[0010] The superjunction preparation method provided in this application has the following advantages:
[0011] By adopting the present application, the thickness of the first conductive type epitaxial layer is increased, and the required thickness of the depletion layer can be achieved with fewer repetitions, which reduces the process cycle, reduces the production cost, and reduces the probability of defects. The number of repetitions of lithography and implantation can be selected as needed. If the same number of repetitions as in the prior art is used, a higher PN depletion layer thickness can be obtained, which greatly increases the withstand voltage capability of the super junction device.
[0012] In some embodiments, implanting second conductive type ions into the trench to form second conductive type pillars comprises the following steps:
[0013] Implanting ions of the second conductivity type in the trench using a first energy to form a first portion of the second conductivity type;
[0014] Second conductive type ions are implanted into the groove using a second energy to form a second conductive type second part, the second energy is lower than the first energy, the first part and the second part of the second conductive type form a second conductive type column, and a first conductive type column is formed between two adjacent second conductive type columns to form a depletion layer with an alternating structure.
[0015] In some embodiments, the first energy is 2600Kev-3000Kev, and the second energy is 600Kev-1000Kev. Using a higher first energy to implant the second conductive type ions into the trench may be more suitable for the scenario of deepening the trench depth in the present application.
[0016] In some embodiments, when the thickness of the depletion layer does not meet the depletion layer thickness requirement, before forming a first conductivity type epitaxial layer with a thickness of 10 to 11 μm on a side of the depletion layer away from the substrate, the following steps are further included:
[0017] The damaged layer formed on the side of the depletion layer away from the substrate is removed by etching. Optionally, a vapor phase etching method is used to remove the damaged layer formed on the side of the depletion layer away from the substrate. The damaged layer is formed on the surface of the epitaxial layer by implanting ions with higher energy and has a very thin thickness.
[0018] In some embodiments, a damaged layer formed on a side of the depletion layer facing away from the substrate is removed by etching by introducing hydrogen chloride gas.
[0019] In some embodiments, the flow time of the hydrogen chloride gas is 30 to 50 seconds.
[0020] In some embodiments, the depletion layer thickness requirement is 40-50 μm, and steps S200 and S300 are repeated three times until the depletion layer thickness reaches the depletion layer thickness requirement.
[0021] In some embodiments, in the step S200, the first conductive type epitaxial layer is photolithographically processed to form a plurality of grooves, including: the first conductive type epitaxial layer is photolithographically processed to form grooves of 10 to 11 μm. When etching the first conductive type epitaxial layer formed in the step S100, the depth of the groove is less than the thickness of the first conductive type epitaxial layer, and when the step S200 is subsequently repeated, when etching the subsequent first conductive type epitaxial layer of 10 to 11 μm formed in the step S400, the depth of the groove is equal to the thickness of the first conductive type epitaxial layer;
[0022] In some embodiments, in step S100 , forming a first conductive type epitaxial layer on one side of the substrate includes: forming a 15 μm first conductive type epitaxial layer on one side of the substrate.
[0023] The embodiment of the present application also provides a super junction structure, which is obtained by using the super junction preparation method, thereby achieving the technical effect obtained by the above-mentioned super junction preparation method.
[0024] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] The accompanying drawings herein are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present invention, and together with the specification are used to explain the principles of the present invention. Obviously, the accompanying drawings described below are only some embodiments of the present invention, and for those of ordinary skill in the art, other accompanying drawings can be obtained based on these accompanying drawings without creative work.
[0026] Figure 1 It is a schematic diagram of a preparation process of a super junction in the prior art;
[0027] Figure 2 is a flow chart of a super junction preparation method according to an embodiment of the present application;
[0028] Figure 3 is a detailed flow chart of a super junction preparation method according to an embodiment of the present application;
[0029] Figure 4 is a schematic diagram of a super junction preparation method according to an embodiment of the present application when the damaged layer is not removed;
[0030] Figure 5 Schematic diagram of a super junction preparation process according to an embodiment of the present application. DETAILED DESCRIPTION
[0031] The example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as being limited to the embodiments set forth herein; on the contrary, these embodiments are provided so that the present application will be comprehensive and complete, and the concept of the example embodiments will be fully conveyed to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their repeated descriptions will be omitted. "Or" and "or" in the specification may both represent "and" or "or". Spatial relationship terms such as "on..." and the like can be used here to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientations shown in the figures, spatial relationship terms also include different orientations of devices in use and operation. For example, if the device in the drawings is flipped, the element or feature described as "on..." will be oriented to be "under..." other elements or features. Therefore, the exemplary term "on..." may include both upper and lower orientations. In addition, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptions used herein are interpreted accordingly.
[0032] When used herein, the singular forms "a", "an" and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items. Although "first" or "second" etc. are used in this specification to represent certain features, they are only used to represent the role, and are not used as a limitation on the number and importance of specific features.
[0033] As mentioned above, among the two existing super junction preparation methods, the first preparation method requires repeated lithography and injection many times to achieve the required depletion layer, with a long process cycle and high production cost. The second preparation method has high requirements for the etching process due to the one-time etching of very deep grooves. In the actual process, voids and defects are very likely to appear, which is a challenge to the reliability of the device. In addition, the process requirements are very high, and the control of defects is difficult, which reduces the yield of the product.
[0034] In order to solve the technical problems in the prior art, the present application provides a new super junction preparation method, which increases the thickness of the first conductive type epitaxial layer growth, and can achieve the required thickness of the depletion layer through fewer repetitions. Compared with the first preparation method, the number of repetitions is reduced, the process cycle is reduced, and the production cost is reduced. Compared with the second preparation method, it has lower process requirements, reduces the difficulty of defect control, and is conducive to improving product yield. The present application also provides a super junction structure obtained by using the super junction preparation method, which is used in super junction devices, can reduce product costs, improve product production efficiency, and improve product yield. Super junction devices have the characteristics of lower on-resistance than ordinary power MOSFET (metal-oxide semiconductor field effect transistor) tubes, and therefore are used as important devices for green energy and have been widely used.
[0035] In the super junction preparation method of the present application, a plurality of first conductive type epitaxial layers are formed above the substrate, and first conductive type columns and second conductive type columns are alternately formed in each first conductive type epitaxial layer to form a depletion layer with an alternating structure. The following description is made by taking the first conductive type as N type and the second conductive type as P type as an example. For N-channel MOSFET, when the structure is in the on state, the on-current flows through the N-type column; in the off state, the P-type region and the N-type region are mutually depleted to obtain a high breakdown voltage. Since there is no concern about the reduction of the breakdown voltage, a thinner N-type epitaxial layer and a higher N-type doping amount can be used, so a lower Rson (on-resistance) can be obtained while maintaining a high breakdown voltage. For P-channel MOSFET, the opposite is true.
[0036] like Figure 2 As shown, in one embodiment of the present application, the super junction preparation method includes the following steps:
[0037] S100: forming a first conductivity type epitaxial layer on one side of the substrate;
[0038] by Figure 4For example, an N-type epitaxial layer 200 is formed on the N+ substrate 100, and the thickness of the N-type epitaxial layer 200 can be selected to be 15 μm, but the present application is not limited thereto. The thickness of the first conductive type epitaxial layer here is only an example, but the present application is not limited thereto; the substrate 100 is, for example, a silicon substrate, a silicon germanium substrate, a silicon-on-insulator substrate, and a germanium-on-insulator substrate; in this embodiment, the substrate 100 is an N-type heavily doped silicon substrate, and the specific type and structure of the substrate 100 can be selected as needed, and are not limited to the examples here. Any substrate 100 that can provide a substrate function of a super junction structure can be used, and all belong to the protection scope of the present application;
[0039] S200: performing photolithography on the first conductive type epitaxial layer to form a plurality of trenches;
[0040] In this embodiment, the depth of the groove formed by photolithography is 10-11 μm; when the first conductive type epitaxial layer formed in step S100 is etched, the depth of the groove is less than the thickness of the first conductive type epitaxial layer, and when step S200 is subsequently repeated, when the first conductive type epitaxial layer of 10-11 μm formed in step S400 is etched, the depth of the groove is equal to the thickness of the first conductive type epitaxial layer;
[0041] The photolithography process includes, for example, the following sub-steps: forming a hard mask layer on the surface of the first conductive type epitaxial layer; coating the surface of the hard mask layer with photoresist, defining an etching window, and performing a photolithography process to form a groove; removing the photoresist;
[0042] S300: injecting second conductive type ions into the trench to form second conductive type columns, and forming first conductive type columns between two adjacent second conductive type columns to form a depletion layer with an alternating structure;
[0043] When the thickness of the depletion layer does not meet the depletion layer thickness requirement, S400: forming a first conductive type epitaxial layer with a thickness of 10 to 11 μm on the side of the depletion layer away from the substrate, and repeating steps S200 and S300 until the thickness of the depletion layer meets the depletion layer thickness requirement, thereby completing the super junction preparation process.
[0044] by Figure 4 and Figure 5For example, the depletion layer thickness requirement is 40 to 50 μm, so steps S200 and S300 are repeated three times to meet the depletion layer thickness requirement. When steps S200 and S300 are performed for the first time, the N-type epitaxial layer 200 is photolithographically processed to form multiple grooves, and the second conductive type ions are injected into the grooves to form P columns 310, and N columns are formed between two adjacent P columns 310 to form a PN depletion layer thin layer of alternating P columns and N columns, and then an N-type epitaxial layer 500 with a thickness of 10 to 11 μm is formed on the side of the depletion layer away from the substrate. When steps S200 and S300 are performed for the second time, the N-type epitaxial layer 500 is photolithographically processed to form multiple grooves, and the second conductive type ions are injected into the grooves to form P columns 310. The second conductive type ions are used to form P columns 320, and an N column is formed between two adjacent P columns 320 to form a PN depletion layer thin layer of alternating P columns and N columns, and then an N-type epitaxial layer 600 with a thickness of 10 to 11 μm is formed on the side of the depletion layer away from the substrate. When the steps S200 and S300 are performed for the third time, the N-type epitaxial layer 600 is photolithographically formed to form a plurality of grooves, and the second conductive type ions are injected into the grooves to form P columns 330, and an N column is formed between two adjacent P columns 330 to form a PN depletion layer thin layer of alternating P columns and N columns. The three PN depletion layer thin layers are aligned up and down to form a PN depletion layer that meets the depletion layer thickness requirements. Figure 4 exemplarily shows a structure in which two P pillars are formed, but the present application is not limited thereto, and the number of P pillars and the intervals between the P pillars can be set as required.
[0045] The depletion layer thickness requirements and the number of repeated lithography and injections here are only examples and are not intended to limit the scope of protection of this application. In different application scenarios, the depletion layer thickness requirements may be different, and the goal can be achieved by adjusting the number of repetitions of lithography and injection accordingly. For example, when the number of repeated lithography and injection reaches 5 times, the depletion layer thickness can reach 65-70μm, which greatly increases the withstand voltage of the super junction structure. If you need to increase the number of repetitions to obtain a thicker depletion layer thickness, for example, in Figure 4 On the basis of the above, a 10-11 μm N-type epitaxial layer is formed through step S400, and then steps S200 and S300 are repeated again to increase the depletion layer thickness until the depletion layer thickness in the final super junction structure meets the subsequent requirements of the depletion layer. During each repetition of steps S200 and S300, the doping concentration of the second type of ions can be selected as needed and is not limited here.
[0046] like Figure 3 As shown, in this embodiment, the step S300: injecting second conductive type ions into the trench to form a second conductive type column includes the following steps:
[0047] S310: Implanting second conductive type ions into the trench using a first energy to form a first portion of the second conductive type; in this embodiment, the first energy is a high energy of 2600Kev-3000Kev; specifically, the specific energy value of the first energy can be selected as needed, which is only an example;
[0048] In this embodiment, since the thickness of the epitaxial layer is increased, the depth of the trench is increased, and a higher implantation energy is required; Figure 4 Taking the formation of the first depletion layer as an example, high energy P-type ions are implanted in the trench to form the first part 311 of the P column;
[0049] S320: injecting second conductive type ions into the trench with a second energy to form a second conductive type second portion, wherein the second energy is lower than the first energy, the first portion and the second portion of the second conductive type form a second conductive type column, and a first conductive type column is formed between two adjacent second conductive type columns to form a depletion layer with an alternating structure; in this embodiment, the second energy is a low energy of 600Kev-1000Kev; specifically, the specific energy value of the second energy can be selected as needed, which is only an example;
[0050] by Figure 4 Taking the formation of the first depletion layer as an example, after the first part 311 of the P column is formed in the trench, P-type ions are implanted at low energy to form the second part 312 of the P column. The first part 311 and the second part 312 are aligned vertically.
[0051] In this embodiment, since step S200 uses a higher implantation energy, the high implantation energy causes a very thin damage layer to be formed on the surface of the epitaxial layer, for example, a damage layer with a thickness of 0.15 to 0.3 μm. Before forming the next first conductivity type epitaxial layer, the damage layer needs to be removed before growing the epitaxial layer.
[0052] Therefore, if Figure 3 As shown, when the thickness of the depletion layer does not meet the depletion layer thickness requirement, step S400: before forming a first conductivity type epitaxial layer with a thickness of 10-11 μm on a side of the depletion layer away from the substrate, the following steps are also included:
[0053] S330: etching and removing the damaged layer formed on the side of the depletion layer away from the substrate.
[0054] In this embodiment, the damaged layer is removed by vapor phase etching. Specifically, the damaged layer formed on the side of the depletion layer away from the substrate is removed by passing hydrogen chloride HCL gas to etch. Optionally, the flow time of the hydrogen chloride gas is 30 to 50 seconds, which is used to etch a damaged layer with a thickness of 0.15 to 0.3 μm. The gas type and flow time used here are only examples. In practical applications, they can be adjusted according to the actual thickness of the damaged layer, which is also within the scope of protection of this application. Since the thickness of the damaged layer is very thin, the time for removing the damaged layer by vapor phase etching is very short, which has little impact on the progress of the overall super junction preparation process.
[0055] Therefore, by adopting the super junction preparation method of the present application, the thickness of the first conductive type epitaxial layer growth is increased, and the required thickness of the depletion layer can be achieved with a fewer number of repetitions, which reduces the process cycle, reduces the production cost, and reduces the probability of defects. Since the thickness of the epitaxial layer and the depth of the groove are increased, higher energy is required to inject the second conductive type ions, which will form a damaged layer on the surface of the epitaxial layer. Before forming the next epitaxial layer, it is necessary to use vapor phase etching to remove a very thin damaged layer, which can also ensure the quality of the super junction product, and because the thickness of the damaged layer is very thin, the process of removing the damaged layer has little effect on the production cycle. The number of repetitions of lithography and injection can be selected as needed. If the same number of repetitions as in the prior art is used, a higher PN depletion layer thickness can be obtained, which greatly increases the voltage resistance of the super junction device. In practical applications, the PN depletion layer thickness can be determined according to the required voltage resistance of the super junction device, and then the number of repetitions of the above-mentioned lithography and injection steps can be determined.
[0056] The embodiment of the present application also provides a super junction structure obtained by the super junction preparation method, the super junction structure comprising a substrate, a first type epitaxial layer and a PN depletion layer on the first type epitaxial layer. The substrate is, for example, a silicon substrate, a silicon germanium substrate, a silicon-on-insulator substrate, and a germanium-on-insulator substrate, and the substrate is a heavily doped substrate. The first type epitaxial layer is, for example, an N-type epitaxial layer. The thickness of the PN depletion layer meets the depletion layer thickness requirement. The super junction structure may also include a gate above the PN depletion layer and other required structures. The super junction structure can be used for super junction devices such as MOSFET tubes.
[0057] The super junction structure of the present application has the following advantages:
[0058] It is prepared using a shorter process cycle, thereby reducing production costs and the probability of defects. The number of repetitions of lithography and implantation can be selected as needed. If the same number of repetitions as in the prior art is used, a higher PN depletion layer thickness can be obtained, greatly increasing the voltage resistance of the super junction device. Super junction devices, chips and circuit structures using this super junction structure can also obtain the beneficial effects of the super junction structure.
[0059] In the above embodiments, the first conductivity type is N type and the second conductivity type is P type. In other alternative embodiments, the first conductivity type may be P type and the second conductivity type may be N type, which can also achieve the purpose of the invention and fall within the protection scope of the present application.
[0060] The above content is a further detailed description of the present application in conjunction with specific preferred embodiments, and it cannot be determined that the specific implementation of the present application is limited to these descriptions. The various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present application will not further describe various possible combinations. The various different embodiments of the present invention can also be combined arbitrarily, as long as they do not violate the idea of the present invention, they should also be regarded as the contents disclosed by the present invention. For ordinary technicians in the technical field to which the present application belongs, without departing from the concept of the present application, several simple deductions or substitutions can also be made, which should all be regarded as belonging to the scope of protection of the present application.
Claims
1. A super junction preparation method, characterized in that: The steps include: S100: forming a first conductivity type epitaxial layer on one side of the substrate; S200: performing photolithography on the first conductive type epitaxial layer to form a plurality of trenches; S300: injecting second conductive type ions into the trench to form second conductive type columns, and forming first conductive type columns between two adjacent second conductive type columns to form a depletion layer with an alternating structure; When the thickness of the depletion layer does not meet the depletion layer thickness requirement, S400: forming a first conductivity type epitaxial layer with a thickness of 10 to 11 μm on a side of the depletion layer away from the substrate, and repeating steps S200 and S300 until the thickness of the depletion layer meets the depletion layer thickness requirement.
2. The super junction preparation method according to claim 1, characterized in that: Implanting second conductive type ions into the trench to form second conductive type columns comprises the following steps: Implanting ions of the second conductivity type in the trench using a first energy to form a first portion of the second conductivity type; Second conductive type ions are implanted into the groove using a second energy to form a second conductive type second part, the second energy is lower than the first energy, the first part and the second part of the second conductive type form a second conductive type column, and a first conductive type column is formed between two adjacent second conductive type columns to form a depletion layer with an alternating structure.
3. The super junction preparation method according to claim 2, characterized in that: The first energy is 2600Kev-3000Kev, and the second energy is 600Kev-1000Kev.
4. The super junction preparation method according to claim 1, characterized in that: When the thickness of the depletion layer does not meet the depletion layer thickness requirement, before forming a first conductivity type epitaxial layer with a thickness of 10-11 μm on a side of the depletion layer away from the substrate, the following steps are also included: The damaged layer formed on the side of the depletion layer facing away from the substrate is removed by etching.
5. The super junction preparation method according to claim 4, characterized in that: A damaged layer formed on a side of the depletion layer facing away from the substrate is removed by etching through the introduction of hydrogen chloride gas.
6. The super junction preparation method according to claim 5, characterized in that: The flow time of the hydrogen chloride gas is 30 to 50 seconds.
7. The super junction preparation method according to claim 1, characterized in that: The thickness requirement of the depletion layer is 40-50 μm, and steps S200 and S300 are repeated three times until the thickness of the depletion layer reaches the required thickness of the depletion layer.
8. The super junction preparation method according to claim 1, characterized in that: In the step S200, photolithography is performed on the first conductive type epitaxial layer to form a plurality of grooves, including: photolithography is performed on the first conductive type epitaxial layer to form grooves with a diameter of 10 to 11 μm.
9. The super junction preparation method according to claim 1, characterized in that: In the step S100 , forming a first conductive type epitaxial layer on one side of the substrate includes: forming a 15 μm first conductive type epitaxial layer on one side of the substrate.
10. A super junction structure, characterized in that: The super junction is obtained by the super junction preparation method according to any one of claims 1 to 9.