Preparation method of solar cell and solar cell
By forming a transparent conductive layer with a suede structure on the silicon substrate of the solar cell and etching it with chemical solution on the back, the problem of insufficient bonding force between the electrode and the transparent conductive layer is solved, the electrode adhesion and light reflection are improved, and the The efficiency of solar cells.
Patent Information
- Application Number
- CN202411421550.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-12
- Publication Date
- 2025-01-14
Smart Images
Figure CN119317236A_ABST
Abstract
Description
Technical Field
[0001] The present application mainly relates to the field of photovoltaic technology, and in particular to a method for preparing a solar cell and a solar cell. Background Art
[0002] Solar cells have the problem of weak bonding between electrodes and substrates, and electrodes are easy to fall off. For example, the bonding between electrodes and transparent conductive layers in heterojunction cells (HJT) is weak. Methods to improve electrode bonding include using laser etching process to activate metallized areas and then electroplating metal electrodes, but laser etching will damage the silicon substrate, causing a decrease in cell efficiency. Therefore, how to improve electrode bonding is one of the important research directions in this field. Summary of the invention
[0003] The technical problem to be solved by the present application is to provide a method for preparing a solar cell and a solar cell, wherein the method for preparing a solar cell and the solar cell can improve the bonding force between an electrode and a transparent conductive layer.
[0004] To solve the above technical problems, the present application provides a method for preparing a solar cell, comprising: providing a silicon substrate having a first surface and a second surface relative to each other, the first surface having a velvet structure, and the second surface having a polished surface; forming a first passivation layer, a first doped silicon layer and a first transparent conductive layer in sequence on the first surface, the first transparent conductive layer having a velvet structure; forming a second passivation layer, a second doped silicon layer and a second transparent conductive layer in sequence on the second surface, the doping type of the first doped silicon layer being opposite to that of the second doped silicon layer; forming a third transparent conductive layer distributed at intervals on the back side of the second transparent conductive layer, etching the third transparent conductive layer using a chemical solution to form a velvet structure on the back side of the third transparent conductive layer, the chemical solution not etching the second transparent conductive layer; and forming a first electrode and a second electrode electrically connected to the first transparent conductive layer and the third transparent conductive layer, respectively, wherein the second electrode is in contact with the velvet structure in the third transparent conductive layer.
[0005] In one embodiment of the present application, the second transparent conductive layer includes indium tin oxide, the third transparent conductive layer includes aluminum zinc oxide, and the chemical solution includes hydrochloric acid and / or oxalic acid.
[0006] In one embodiment of the present application, the first transparent conductive layer includes indium tin oxide.
[0007] In one embodiment of the present application, the method for forming the second electrode includes: printing a conductive paste on the back surface of the third transparent conductive layer; and sintering the conductive paste to form the second electrode.
[0008] In an embodiment of the present application, the first passivation layer and the second passivation layer include intrinsic amorphous silicon, and the first doped silicon layer and the second doped silicon layer include doped amorphous silicon.
[0009] In one embodiment of the present application, the method for forming the second surface having a polished surface includes: preparing a first surface and a second surface having a velvet structure; covering the first surface with a silicon oxide mask layer; single-sided polishing the second surface; and removing the silicon oxide mask layer.
[0010] On the other hand, the present application also proposes a solar cell, comprising: a silicon substrate, having a first surface and a second surface relative to each other, the first surface having a velvet structure, and the second surface having a polished surface; a first passivation layer, a first doped silicon layer and a first transparent conductive layer, which are stacked on the first surface, the first transparent conductive layer having a velvet structure; a second passivation layer, a second doped silicon layer and a second transparent conductive layer, which are stacked on the second surface, the doping type of the first doped silicon layer being opposite to that of the second doped silicon layer; a third transparent conductive layer, which is spaced apart on the back side of the second transparent conductive layer, the back side of the third transparent conductive layer having a velvet structure; and a first electrode and a second electrode, which are electrically connected to the first transparent conductive layer and the third transparent conductive layer, respectively, wherein the second electrode is in contact with the velvet structure in the third transparent conductive layer.
[0011] In one embodiment of the present application, the second transparent conductive layer includes indium tin oxide, and the third transparent conductive layer includes aluminum zinc oxide.
[0012] In one embodiment of the present application, the first transparent conductive layer includes indium tin oxide.
[0013] In an embodiment of the present application, the first passivation layer and the second passivation layer include intrinsic amorphous silicon, and the first doped silicon layer and the second doped silicon layer include doped amorphous silicon.
[0014] Compared with the prior art, the present application has the following advantages: a velvet structure is formed on the back of the third transparent conductive layer, and the velvet structure can increase the contact area of the attachment area of the second electrode, thereby improving the bonding force between the second electrode and the third transparent conductive layer. In addition, the chemical solution does not etch the second transparent conductive layer, which can increase the reflection of the second transparent conductive layer to light and reflect more light into the solar cell. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] The accompanying drawings are included to provide a further understanding of the present application. They are included and constitute a part of the present application. The accompanying drawings illustrate embodiments of the present application and together with the present specification serve to explain the principles of the present application. In the accompanying drawings:
[0016] Figure 1 is a schematic flow chart of a method for preparing a solar cell in one embodiment of the present application;
[0017] Figures 2 to 4 It is a schematic cross-sectional view of a solar cell in different steps of a preparation method in an embodiment of the present application.
[0018] Reference numerals
[0019] Silicon substrate 210 First transparent conductive layer 240 Third transparent conductive layer 280
[0020] First surface 211 Second passivation layer 250 Back surface 281
[0021] Second surface 212 Second doped silicon layer 260 First electrode 290
[0022] First passivation layer 220 Second transparent conductive layer 270 Second electrode 310
[0023] The first doped silicon layer 230 has a back surface 271 DETAILED DESCRIPTION
[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for the description of the embodiments. Obviously, the drawings described below are only some examples or embodiments of the present application. For ordinary technicians in this field, the present application can also be applied to other similar scenarios based on these drawings without creative work. Unless it is obvious from the language environment or otherwise explained, the same reference numerals in the figures represent the same structure or operation.
[0025] As shown in this application and claims, unless the context clearly indicates an exception, the words "a", "an", "an" and / or "the" do not refer to the singular and may also include the plural. Generally speaking, the terms "include" and "comprise" only indicate the inclusion of the steps and elements that have been clearly identified, and these steps and elements do not constitute an exclusive list. The method or device may also include other steps or elements.
[0026] Unless otherwise specifically stated, the relative arrangement, numerical expressions and numerical values of the parts and steps set forth in these embodiments do not limit the scope of the present application. At the same time, it should be understood that, for ease of description, the sizes of the various parts shown in the accompanying drawings are not drawn according to the actual proportional relationship. The technology, method and equipment known to those of ordinary skill in the relevant field may not be discussed in detail, but in appropriate cases, the technology, method and equipment should be considered as a part of the authorization specification. In all examples shown and discussed here, any specific value should be interpreted as being merely exemplary, rather than as a limitation. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters represent similar items in the following drawings, so that once a certain item is defined in an accompanying drawing, it does not need to be further discussed in subsequent drawings.
[0027] In the description of the present application, it should be understood that the directions or positional relationships indicated by directional words such as "front, back, up, down, left, right", "lateral, vertical, perpendicular, horizontal" and "top, bottom" are usually based on the directions or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description. Unless otherwise specified, these directional words do not indicate or imply that the device or element referred to must have a specific direction or be constructed and operated in a specific direction, and therefore cannot be understood as limiting the scope of protection of the present application; the directional words "inside and outside" refer to the inside and outside relative to the contours of each component itself.
[0028] For ease of description, spatially relative terms such as "above", "above", "on the upper surface of", "above", etc. may be used here to describe the spatial positional relationship between a device or feature and other devices or features as shown in the figure. It should be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation described in the figure. For example, if the device in the accompanying drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Thus, the exemplary term "above" can include both "above" and "below". The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatially relative descriptions used here are interpreted accordingly.
[0029] In addition, it should be noted that the use of words such as "first" and "second" to define components is only for the convenience of distinguishing the corresponding components. If not otherwise stated, the above words have no special meaning and cannot be understood as limiting the scope of protection of this application. In addition, although the terms used in this application are selected from well-known and commonly used terms, some terms mentioned in the specification of this application may be selected by the applicant at his or her discretion, and their detailed meanings are explained in the relevant parts of the description of this article. In addition, it is required to understand this application not only by the actual terms used, but also by the meaning implied by each term.
[0030] Flowcharts are used in the present application to illustrate the operations performed by the system according to the embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed accurately in order. On the contrary, various steps may be processed in reverse order or simultaneously. At the same time, other operations may be added to these processes, or one or more operations may be removed from these processes.
[0031] Next, the preparation method of the solar cell and the solar cell of the present application are described through examples.
[0032] refer to Figure 1 As shown, in Figure 1 In the embodiment of the present invention, the preparation method includes the following steps S110 to S150.
[0033] Step S110: providing a silicon substrate having a first surface and a second surface opposite to each other, wherein the first surface has a suede structure and the second surface has a polished surface;
[0034] Step S120: forming a first passivation layer, a first doped silicon layer and a first transparent conductive layer in sequence on the first surface, wherein the first transparent conductive layer has a suede structure;
[0035] Step S130: forming a second passivation layer, a second doped silicon layer, and a second transparent conductive layer in sequence on the second surface, wherein the doping type of the first doped silicon layer is opposite to that of the second doped silicon layer;
[0036] Step S140: forming a third transparent conductive layer distributed at intervals on the back side of the second transparent conductive layer, etching the third transparent conductive layer with a chemical solution to form a suede structure on the back side of the third transparent conductive layer, and the chemical solution does not etch the second transparent conductive layer;
[0037] Step S150: forming a first electrode and a second electrode electrically connected to the first transparent conductive layer and the third transparent conductive layer respectively, wherein the second electrode contacts the suede structure in the third transparent conductive layer.
[0038] Next, steps S110 to S150 are described in detail.
[0039] refer to Figure 2 As shown, in step S110, a silicon substrate 210 is provided, and the silicon substrate 210 has a first surface 211 and a second surface 212 opposite to each other, the first surface 211 has a velvet structure, and the second surface 212 has a polished surface. The silicon substrate 210 can be N-type single crystal silicon or P-type single crystal silicon, the entire surface of the first surface 211 can be a velvet structure, and the velvet structure can reduce the reflection of the solar cell to the incident light, and the entire surface of the second surface 212 can be a polished surface, which helps to reflect the light into the interior of the solar cell.
[0040] In one embodiment, the method for forming the second surface 212 having a polished surface includes the following steps 1 to 4.
[0041] Step 1: Prepare a first surface and a second surface with a suede structure.
[0042] Step 2: Cover the first surface with a silicon oxide mask layer. A plasma enhanced chemical vapor deposition (PECVD) process may be used to deposit a layer of silicon oxide as a mask on the first surface on which the textured structure has been formed.
[0043] Step 3: Single-sided polishing of the second surface: Specifically, the second surface is polished with a chemical liquid to form a second surface having a polished surface. During the polishing process, the silicon oxide mask formed in step 2 can protect the first surface from being etched by the chemical liquid.
[0044] Step 4: removing the silicon oxide mask layer.
[0045] refer to Figure 2 As shown, in step S120, a first passivation layer 220, a first doped silicon layer 230 and a first transparent conductive layer 240 are sequentially formed on the first surface 211, and the first transparent conductive layer 240 has a suede structure. The first passivation layer 220 may include intrinsic amorphous silicon, and the first doped silicon layer 230 may include doped amorphous silicon, for example, N-type doped amorphous silicon or P-type doped amorphous silicon. The first transparent conductive layer 240 may include indium tin oxide (ITO).
[0046] The present application does not limit the process method for forming the first passivation layer 220, the first doped silicon layer 230 and the first transparent conductive layer 240. For example, it can be chemical vapor deposition (CVD) or physical vapor deposition (PVD). In the process of forming the first passivation layer 220, the first doped silicon layer 230 and the first transparent conductive layer 240, since the first surface 211 has a suede structure, the above-mentioned film layer is conformal with the first surface 211 and therefore also has a suede structure.
[0047] refer to Figure 2As shown, in step S130, a second passivation layer 250, a second doped silicon layer 260, and a second transparent conductive layer 270 are sequentially formed on the second surface 212. The second passivation layer 250 may include intrinsic amorphous silicon, the second doped silicon layer 260 may include doped amorphous silicon, for example, N-type doped amorphous silicon or P-type doped amorphous silicon, and the doping type of the first doped silicon layer 230 is opposite to the doping type of the second doped silicon layer 260.
[0048] The present application does not limit the process method for forming the second passivation layer 250 , the second doped silicon layer 260 and the second transparent conductive layer 270 . For example, they may be chemical vapor deposition (CVD) or physical vapor deposition (PVD).
[0049] refer to Figure 2 and Figure 3 As shown, in step S140, the second transparent conductive layer 270 has a back surface 271, and the third transparent conductive layers 280 are formed on the back surface 271. The spacing between adjacent third transparent conductive layers 280 can be adjusted as required. The third transparent conductive layer 280 has a back surface 281, and the third transparent conductive layer 280 is etched using a chemical solution to form a velvet structure (such as Figure 3 As shown in FIG. 2 , the chemical solution does not etch the second transparent conductive layer 270. It should be noted that the chemical solution substantially does not etch the second transparent conductive layer 270, which is also within the protection scope of the present application.
[0050] Preferably, the present application directly forms the third transparent conductive layer 280 distributed at intervals on the back surface 271, for example, by means of a mask-deposition process. Compared with the method of forming the entire third transparent conductive layer 280 and then selectively removing part of the third transparent conductive layer 280, the above method of the present application has the advantage of saving materials.
[0051] Next, it is described how the chemical solution forms a velvet structure on the back surface 281 without etching the second transparent conductive layer 270. The material of the second transparent conductive layer 270, the material of the third transparent conductive layer 280 and the chemical solution are matched with each other, and the etching rate of the third transparent conductive layer 280 by the chemical solution is much greater than the etching rate of the second transparent conductive layer 270, or the chemical solution does not (basically) etch the second transparent conductive layer 270. In one embodiment, the second transparent conductive layer 270 includes indium tin oxide (ITO), the third transparent conductive layer 280 includes aluminum zinc oxide (AZO), and the chemical solution includes hydrochloric acid and / or oxalic acid.
[0052] refer to Figure 3 and Figure 4As shown, in step S150, a first electrode 290 and a second electrode 310 are formed which are electrically connected to the first transparent conductive layer 240 and the third transparent conductive layer 280 respectively, and the second electrode 310 is in contact with the velvet structure in the third transparent conductive layer 280. The velvet structure in the third transparent conductive layer 280 can increase the contact area of the attachment region of the second electrode 310, thereby improving the bonding force between the second electrode 310 and the third transparent conductive layer 280.
[0053] As mentioned above, the chemical solution does not etch the second transparent conductive layer 270 , which can increase the reflection of light by the second transparent conductive layer 270 and reflect more light into the solar cell.
[0054] In one embodiment, forming the second electrode 310 includes: printing a conductive paste on the back surface 281 of the third transparent conductive layer 280 , and then sintering the conductive paste to form the second electrode 310 . The conductive paste may contain metallic silver.
[0055] On the other hand, the present application also proposes a solar cell, Figure 3 and Figure 4 As shown, the solar cell includes: a silicon substrate 210, a first passivation layer 220, a first doped silicon layer 230, a first transparent conductive layer 240, a second passivation layer 250, a second doped silicon layer 260, a second transparent conductive layer 270, a third transparent conductive layer 280, a first electrode 290 and a second electrode 310.
[0056] Specifically, the silicon substrate 210 has a first surface 211 and a second surface 212 opposite to each other, the first surface 211 has a velvet structure, and the second surface 212 has a polished surface. The first passivation layer 220, the first doped silicon layer 230 and the first transparent conductive layer 240 are stacked on the first surface 211, and the first transparent conductive layer 240 has a velvet structure. The second passivation layer 250, the second doped silicon layer 260 and the second transparent conductive layer 270 are stacked on the second surface 212, and the doping type of the first doped silicon layer 230 is opposite to that of the second doped silicon layer 260. The third transparent conductive layer 280 is spaced apart on the back side 271 of the second transparent conductive layer 270, and the back side 281 of the third transparent conductive layer 280 has a velvet structure. As described above, the velvet structure can be formed on the back side 281 by using a chemical solution etching method, and the chemical solution does not etch the second transparent conductive layer 270. The first electrode 290 and the second electrode 310 are electrically connected to the first transparent conductive layer 240 and the third transparent conductive layer 280 , respectively. The second electrode 310 is in contact with the textured structure in the third transparent conductive layer 280 .
[0057] In one embodiment, the second transparent conductive layer 270 includes indium tin oxide, and the third transparent conductive layer 280 includes aluminum zinc oxide. A chemical solution containing hydrochloric acid and / or oxalic acid can be used to etch the third transparent conductive layer 280 to form a suede structure. The chemical solution etches aluminum zinc oxide but does not etch indium tin oxide. In one embodiment, the first transparent conductive layer 240 includes indium tin oxide.
[0058] In one embodiment, the first passivation layer 220 and the second passivation layer 250 include intrinsic amorphous silicon, and the first doped silicon layer 230 and the second doped silicon layer 260 include doped amorphous silicon. For example, the first doped silicon layer 230 is N-type or P-type doped amorphous silicon, and the second doped silicon layer 260 is N-type or P-type doped amorphous silicon. The doping type of the first doped silicon layer 230 is opposite to the doping type of the second doped silicon layer 260.
[0059] For other descriptions about the battery of the present application, please refer to the description of the preparation method above, which will not be elaborated here.
[0060] The basic concepts have been described above. Obviously, for those skilled in the art, the above application disclosure is only an example and does not constitute a limitation of the present application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements and amendments to the present application. Such modifications, improvements and amendments are suggested in the present application, so such modifications, improvements and amendments still belong to the spirit and scope of the exemplary embodiments of the present application.
[0061] At the same time, the present application uses specific words to describe the embodiments of the present application. For example, "one embodiment", "an embodiment", and / or "some embodiments" refer to a certain feature, structure or characteristic related to at least one embodiment of the present application. Therefore, it should be emphasized and noted that "one embodiment" or "an embodiment" or "an alternative embodiment" mentioned twice or more in different positions in this specification does not necessarily refer to the same embodiment. In addition, some features, structures or characteristics in one or more embodiments of the present application can be appropriately combined.
[0062] Similarly, it should be noted that in order to simplify the description of the disclosure of this application and thus help understand one or more application embodiments, in the above description of the embodiments of this application, multiple features are sometimes merged into one embodiment, figure or description thereof. However, this disclosure method does not mean that the features required by the object of this application are more than the features mentioned in the claims. In fact, the features of the embodiments are less than all the features of the single embodiment disclosed above.
[0063] In some embodiments, numbers describing the number of components and attributes are used. It should be understood that such numbers used in the description of the embodiments are modified by the modifiers "about", "approximately" or "substantially" in some examples. Unless otherwise specified, "about", "approximately" or "substantially" indicate that the numbers are allowed to vary by ±20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximate values, which may change according to the required features of individual embodiments. In some embodiments, the numerical parameters should take into account the specified significant digits and adopt the general method of retaining digits. Although the numerical domains and parameters used to confirm the breadth of their range in some embodiments of the present application are approximate values, in specific embodiments, the setting of such numerical values is as accurate as possible within the feasible range.
[0064] Although the present application has been described with reference to the current specific embodiments, ordinary technicians in this technical field should recognize that the above embodiments are only used to illustrate the present application, and various equivalent changes or substitutions may be made without departing from the spirit of the present application. Therefore, as long as the changes and modifications to the above embodiments are within the essential spirit of the present application, they will fall within the scope of the claims of the present application.
Claims
1. A method for preparing a solar cell, characterized in that: include: Providing a silicon substrate having a first surface and a second surface opposite to each other, wherein the first surface has a suede structure and the second surface has a polished surface; forming a first passivation layer, a first doped silicon layer and a first transparent conductive layer in sequence on the first surface, wherein the first transparent conductive layer has a suede structure; forming a second passivation layer, a second doped silicon layer, and a second transparent conductive layer on the second surface in sequence, wherein the doping type of the first doped silicon layer is opposite to that of the second doped silicon layer; forming a third transparent conductive layer distributed at intervals on the back side of the second transparent conductive layer, etching the third transparent conductive layer with a chemical solution to form a suede structure on the back side of the third transparent conductive layer, wherein the chemical solution does not etch the second transparent conductive layer; as well as A first electrode and a second electrode are formed which are electrically connected to the first transparent conductive layer and the third transparent conductive layer respectively, wherein the second electrode is in contact with the texture structure in the third transparent conductive layer.
2. The preparation method according to claim 1, characterized in that The second transparent conductive layer includes indium tin oxide, the third transparent conductive layer includes aluminum zinc oxide, and the chemical solution includes hydrochloric acid and / or oxalic acid.
3. The preparation method according to claim 1, characterized in that: The first transparent conductive layer includes indium tin oxide.
4. The preparation method according to claim 1, characterized in that: The method of forming the second electrode comprises: printing a conductive paste on the back surface of the third transparent conductive layer; and The conductive paste is sintered to form the second electrode.
5. The preparation method according to claim 1, characterized in that: The first passivation layer and the second passivation layer include intrinsic amorphous silicon, and the first doped silicon layer and the second doped silicon layer include doped amorphous silicon.
6. The preparation method according to claim 1, characterized in that: The method of forming the second surface having a polished surface comprises: preparing a first surface and a second surface having a suede structure; Using a silicon oxide mask layer to cover the first surface; performing single-side polishing on the second surface; and The silicon oxide mask layer is removed.
7. A solar cell, characterized in that: include: A silicon substrate having a first surface and a second surface opposite to each other, wherein the first surface has a suede structure and the second surface has a polished surface; A first passivation layer, a first doped silicon layer and a first transparent conductive layer are stacked on the first surface, and the first transparent conductive layer has a suede structure; A second passivation layer, a second doped silicon layer, and a second transparent conductive layer are stacked on the second surface, wherein the doping type of the first doped silicon layer is opposite to that of the second doped silicon layer; A third transparent conductive layer is spaced apart and distributed on the back surface of the second transparent conductive layer, and the back surface of the third transparent conductive layer has a suede structure; as well as The first electrode and the second electrode are electrically connected to the first transparent conductive layer and the third transparent conductive layer respectively, wherein the second electrode is in contact with the velvet structure in the third transparent conductive layer.
8. The solar cell according to claim 7, wherein: The second transparent conductive layer includes indium tin oxide, and the third transparent conductive layer includes aluminum zinc oxide.
9. The solar cell according to claim 7, wherein: The first transparent conductive layer includes indium tin oxide.
10. The solar cell according to claim 7, wherein: The first passivation layer and the second passivation layer include intrinsic amorphous silicon, and the first doped silicon layer and the second doped silicon layer include doped amorphous silicon.