Thermoelectric cooling chip and manufacturing method and packaging structure thereof

Abstract

The invention discloses a thermoelectric cooling chip and a manufacturing method and a packaging structure thereof. The thermoelectric cooling chip comprises a substrate; the buffer layer is arranged on the surface of the substrate; the first etching stop layer is arranged on the buffer layer; the dielectric layer is arranged on the first etching stop layer; a first conductive type semiconductor layer embedded in the dielectric layer; the first wire layer is arranged in the dielectric layer and is in direct contact with the side wall of the first conductive type semiconductor layer; a second etch stop layer disposed on the first conductive type semiconductor layer; the second lead layer is arranged in the dielectric layer and the second etching stop layer and is in direct contact with the side wall of the first conductive type semiconductor layer; a second conductive type semiconductor layer on the first conductive type semiconductor layer; and a third lead layer disposed on the second lead layer and in direct contact with the sidewall of the second conductive type semiconductor layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a thermoelectric cooling chip and a manufacturing method and a packaging structure thereof. Background Art

[0002] It is known that the thermoelectric cooling structure is made of thermoelectric materials and achieves cooling effect by inputting electric current. The working principle of the thermoelectric cooling structure is to use a combination of P-type semiconductor and N-type semiconductor, and connect the two ends of the P-type semiconductor and the N-type semiconductor with metal. When the current passes through the PN couple, only high-energy holes in the P-type semiconductor can overcome the energy barrier and pass through, and only high-energy electrons in the N-type semiconductor can overcome the energy barrier and pass through. Because these two types of hot carriers leave and take away heat, one end of the metal connecting the P-type semiconductor and the N-type semiconductor will absorb heat, and the other end will release heat. In addition, the temperature difference between the two ends of the metal can be controlled by the current size, thereby controlling the temperature of the heat source.

[0003] The P-type and N-type semiconductors of the thermoelectric cooling chips currently on the market are arranged in a planar manner, which makes the thermoelectric cooling chips larger in size. Therefore, they can only be placed outside the IC package to help the package dissipate heat, and cannot be placed inside the package to directly contact the heat source chip. Summary of the invention

[0004] The main purpose of the present invention is to provide an innovative thermoelectric cooling chip and its packaging structure, which can improve the above-mentioned deficiencies and shortcomings of the prior art.

[0005] On one hand, the present invention provides a thermoelectric cooling chip, comprising: a substrate; a buffer layer, arranged on the surface of the substrate; a first etch stop layer, arranged on the buffer layer; a dielectric layer, arranged on the first etch stop layer; a first conductive semiconductor layer, buried in the dielectric layer; a first conductive wire layer, arranged in the dielectric layer and directly contacting the side wall of the first conductive semiconductor layer; a second etch stop layer, arranged on the first conductive semiconductor layer; a second conductive wire layer, arranged between the dielectric layer and the second etch stop layer and directly contacting the side wall of the first conductive semiconductor layer; a second conductive semiconductor layer, located on the first conductive semiconductor layer; and a third conductive wire layer, arranged on the second conductive wire layer and directly contacting the side wall of the second conductive semiconductor layer.

[0006] According to an embodiment of the present invention, the substrate includes a silicon substrate.

[0007] According to an embodiment of the present invention, the first conductivity type semiconductor layer is a P-type doped polysilicon layer, and the second conductivity type is an N-type doped polysilicon layer.

[0008] According to an embodiment of the present invention, the first conductivity type semiconductor layer is an N-type doped polysilicon layer, and the second conductivity type is a P-type doped polysilicon layer.

[0009] According to an embodiment of the present invention, the buffer layer includes a silicon oxide layer, the first etching stop layer includes a silicon nitride layer, and the second etching stop layer includes a silicon nitride layer.

[0010] According to an embodiment of the present invention, the dielectric layer includes a silicon oxide layer.

[0011] According to the embodiment of the present invention, the second conductive type semiconductor layer and the first conductive type semiconductor layer are electrically isolated from each other by the second etching stop layer.

[0012] Another aspect of the present invention provides a method for forming a thermoelectric cooling chip, comprising: providing a substrate; forming a buffer layer on the surface of the substrate; forming a first etch stop layer on the buffer layer; forming a dielectric layer on the first etch stop layer; forming a first conductive semiconductor layer in the dielectric layer; forming a first conductive wire layer in the dielectric layer, directly contacting the side wall of the first conductive semiconductor layer; forming a second conductive wire layer on the first conductive semiconductor layer; forming a second conductive wire layer in the dielectric layer and the second etch stop layer, directly contacting the side wall of the first conductive semiconductor layer; forming a second conductive wire layer on the first conductive semiconductor layer; and forming a third conductive wire layer on the second conductive wire layer, directly contacting the side wall of the second conductive semiconductor layer.

[0013] On the other hand, the present invention provides a packaging structure, comprising: a packaging substrate; a heat source chip, comprising an active surface and a passive surface, the active surface being connected to the packaging substrate; a thermoelectric cooling chip, comprising a top surface and a bottom surface, the passive surface of the heat source chip being in thermal contact with the top surface of the thermoelectric cooling chip, wherein the top surface of the thermoelectric cooling chip comprises a plurality of N-type semiconductor layers and P-type semiconductor layers formed in a three-dimensional stacking manner, arranged in a ring shape corresponding to the periphery of the heat source chip; a molding compound, covering the heat source chip and the thermoelectric cooling chip, exposing the bottom surface of the thermoelectric cooling chip; and a heat sink, disposed on the bottom surface of the thermoelectric cooling chip.

[0014] According to an embodiment of the present invention, the plurality of N-type semiconductor layers and P-type semiconductor layers are electrically connected in pairs by wires, thereby forming an annular inner heat absorption zone and an annular outer heat release zone, wherein the outer heat release zone surrounds the inner heat absorption zone.

[0015] According to an embodiment of the present invention, the top surface of the thermoelectric cooling chip further includes a metal bonding pad which is electrically connected to the packaging substrate via a copper column disposed in the molding compound.

[0016] According to an embodiment of the present invention, the thermoelectric cooling chip further comprises a through-silicon via, wherein one end of the through-silicon via is exposed at the bottom surface of the thermoelectric cooling chip, and the other end is adjacent to the outer heat release area.

[0017] According to an embodiment of the present invention, a thermally conductive interface material is further disposed between the heat sink and the bottom surface of the thermoelectric cooling chip.

[0018] On the other hand, the present invention provides a packaging structure, comprising: a packaging substrate; a heat source chip, comprising an active surface and a passive surface; a thermoelectric cooling chip, comprising a top surface and a bottom surface, the passive surface of the heat source chip thermally contacts the top surface of the thermoelectric cooling chip, wherein the top surface of the thermoelectric cooling chip comprises a plurality of N-type semiconductor layers and P-type semiconductor layers formed in a three-dimensional stacking manner, arranged in a ring shape corresponding to the periphery of the heat source chip, wherein the bottom surface of the thermoelectric cooling chip is fixed on the packaging substrate; a molding compound, covering the heat source chip and the thermoelectric cooling chip; a redistribution layer, disposed on the molding compound and on the active surface of the heat source chip; and a heat sink, disposed on the redistribution layer.

[0019] According to an embodiment of the present invention, the plurality of N-type semiconductor layers and P-type semiconductor layers are electrically connected in pairs by wires, thereby forming an annular inner heat absorption zone and an annular outer heat release zone, wherein the outer heat release zone surrounds the inner heat absorption zone.

[0020] According to an embodiment of the present invention, a through-mold hole is provided in the molding material between the redistribution layer and the top surface of the thermoelectric cooling chip, wherein one end of the through-mold hole thermally contacts the outer heat release area of ​​the thermoelectric cooling chip.

[0021] According to an embodiment of the present invention, the top surface of the thermoelectric cooling chip further includes a metal bonding pad which is electrically connected to the packaging substrate via a bonding wire disposed in the molding compound.

[0022] According to an embodiment of the present invention, a thermally conductive interface material is further disposed between the heat sink and the redistribution layer.

[0023] In order to make the above-mentioned objectives, features and advantages of the present invention more clearly understood, the following is a detailed description of the preferred embodiments and the accompanying drawings. However, the following preferred embodiments and drawings are only for reference and explanation, and are not intended to limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 The figure is a perspective view of a semiconductor structure combining a thermoelectric cooling chip and a heat source chip according to an embodiment of the present invention. Figure 2 For along Figure 1 Schematic cross-sectional view shown by the midline II'. Figure 3 It is a schematic cross-sectional view of a packaging structure according to an embodiment of the present invention. Figure 4 It is a schematic cross-sectional view of a packaging structure according to another embodiment of the present invention. Figures 5 to 17 A method for manufacturing a thermoelectric cooling chip is illustrated. DETAILED DESCRIPTION

[0025] In the following, the details will be described with reference to the accompanying drawings, which also constitute part of the detailed description of the specification, and are depicted in a specific way that the embodiment can be implemented. The following embodiments have been described in sufficient detail to enable a person of ordinary skill in the art to implement them. Of course, other embodiments may be implemented, or any structural, logical, and electrical changes may be made without departing from the embodiments described herein. Therefore, the detailed description below should not be regarded as limiting, but rather, the embodiments included therein will be defined by the appended claims.

[0026] It should be understood that although the terms "first", "second", etc. may be used herein to describe various components, regions, layers and / or parts, these components, regions, layers and / or parts should not be limited to these terms. These terms are only used to distinguish one component, region, layer or part from another component, region, layer or part. Therefore, the first component, region, layer or part discussed below can be referred to as a second component, region, layer or part without departing from the teachings of the exemplary embodiments.

[0027] The present invention relates to a packaging structure with a thermoelectric cooling chip, which can package the thermoelectric cooling chip and the heat source chip together. The thermoelectric cooling chip is made in the form of a semiconductor film, and the number of P-type semiconductors and N-type semiconductors is increased in a three-dimensional stacking manner, thereby improving the heat absorption area and heat dissipation efficiency. The present invention uses packaging technology to package the thermoelectric cooling chip and the heat source chip together to form a single packaging structure with the thermoelectric cooling chip, so as to solve the shortcomings of the existing technology.

[0028] See also Figure 1 and Figure 2 ,in, Figure 1 FIG. 1 is a perspective view of a semiconductor structure combining a thermoelectric cooling chip and a heat source chip according to an embodiment of the present invention. Figure 2 For along Figure 1 The cross-sectional view shown by the midline I-I'. Figure 1 and Figure 2As shown, the semiconductor structure 1 includes a thermoelectric cooling chip 10 and a heat source chip 20 disposed on the top surface 10a of the thermoelectric cooling chip 10. According to an embodiment of the present invention, the heat source chip 20 includes an active surface 20a and a passive surface 20b, wherein a plurality of input / output (I / O) pads 201 may be disposed on the active surface 20a. The thermoelectric cooling chip 10 includes a substrate 100. According to an embodiment of the present invention, for example, the substrate 100 may be a silicon substrate.

[0029] According to an embodiment of the present invention, for example, the thermoelectric cooling chip 10 and the heat source chip 20 may be silicon chips. According to an embodiment of the present invention, for example, the heat source chip 20 may include, but is not limited to, an application processor (AP) chip, a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, a system on chip (SoC), etc.

[0030] According to an embodiment of the present invention, the passive surface 20b of the heat source chip 20 is directly connected to the top surface 10a of the thermal contact thermoelectric cooling chip 10. According to an embodiment of the present invention, the heat source chip 20 can be fixed on the top surface 10a of the thermoelectric cooling chip 10 by any suitable heat conduction method, such as bonding or direct bonding. According to an embodiment of the present invention, the top surface 10a of the thermoelectric cooling chip 10 includes an N-type semiconductor layer 101 and a P-type semiconductor layer 102 formed in a three-dimensional stacking manner, which are arranged in a ring shape corresponding to the periphery of the heat source chip 20.

[0031] According to an embodiment of the present invention, the N-type semiconductor layer 101 and the P-type semiconductor layer 102 are made by semiconductor technology and are electrically connected to each other in pairs by wires 110, so as to form an inner heat absorption region R1 and an outer heat release region R2 as shown in the dotted area, wherein the outer heat release region R2 surrounds the inner heat absorption region R1. According to an embodiment of the present invention, for example, the wire 110 may include a copper wire, but is not limited thereto. According to an embodiment of the present invention, the N-type semiconductor layer 101 and the P-type semiconductor layer 102 on the top surface 10a of the thermoelectric cooling chip 10 may be a two-layer stack or a multi-layer stack with more than two layers in an alternating configuration.

[0032] According to an embodiment of the present invention, a metal bonding pad 112 may be further included on the top surface 10a of the thermoelectric cooling chip 10, and the metal bonding pad 112 is electrically connected to the wire 110 and can be connected to an external signal to provide the current required by the thermoelectric cooling chip 10. According to an embodiment of the present invention, for example, the substrate 100 of the thermoelectric cooling chip 10 may further include a through silicon via (TSV) 106 for heat conduction, wherein one end of the through silicon via 106 may be exposed to the bottom surface 10b of the thermoelectric cooling chip 10, and the other end may be adjacent to the outer heat release area R2. Those skilled in the art should understand that the size or number of each component and area shown in the figure is only for illustration and is not drawn according to the original scale.

[0033] See also Figure 3 , which is a schematic cross-sectional view of a packaging structure according to an embodiment of the present invention. Figure 3 As shown, the package structure P includes a package substrate 30 and a semiconductor structure 1 disposed on the package substrate 30, wherein the semiconductor structure 1, Figure 1 and Figure 2 As described in , it includes a thermoelectric cooling chip 10 and a heat source chip 20 arranged on the top surface 10a of the thermoelectric cooling chip 10. According to an embodiment of the present invention, the heat source chip 20 includes an active surface 20a and a passive surface 20b, wherein a plurality of output / input pads 201 may be arranged on the active surface 20a. The thermoelectric cooling chip 10 includes a substrate 100. According to an embodiment of the present invention, for example, the substrate 100 may be a silicon substrate. According to an embodiment of the present invention, the semiconductor structure 1 is covered by a molding compound 40, and only the bottom surface 10b of the thermoelectric cooling chip 10 is exposed.

[0034] According to an embodiment of the present invention, the passive surface 20b of the heat source chip 20 is directly connected to the top surface 10a of the thermal contact thermoelectric cooling chip 10. According to an embodiment of the present invention, the heat source chip 20 can be fixed on the top surface 10a of the thermoelectric cooling chip 10 by any suitable heat conduction method, such as bonding or direct bonding. According to an embodiment of the present invention, the top surface 10a of the thermoelectric cooling chip 10 includes an N-type semiconductor layer 101 and a P-type semiconductor layer 102 formed in a three-dimensional stacking manner, which are arranged in a ring shape corresponding to the periphery of the heat source chip 20.

[0035] According to an embodiment of the present invention, the N-type semiconductor layer 101 and the P-type semiconductor layer 102 are made by semiconductor technology and are electrically connected to each other in pairs by wires 110, so as to form an annular inner heat absorption area R1 and an annular outer heat release area R2 as shown in the dotted area, wherein the outer heat release area R2 surrounds the inner heat absorption area R1. According to an embodiment of the present invention, for example, the wire 110 may include a copper wire, but is not limited thereto. According to an embodiment of the present invention, the N-type semiconductor layer 101 and the P-type semiconductor layer 102 on the top surface 10a of the thermoelectric cooling chip 10 may be a two-layer stack or a multi-layer stack of more than two layers in an alternating configuration.

[0036] According to an embodiment of the present invention, a metal bonding pad 112 is further included on the top surface 10a of the thermoelectric cooling chip 10, and the metal bonding pad 112 is electrically connected to the wire 110 and can be connected to an external signal to provide the current required by the thermoelectric cooling chip 10. According to an embodiment of the present invention, for example, the substrate 100 of the thermoelectric cooling chip 10 further includes a through-silicon via 106 for heat conduction, wherein one end of the through-silicon via 106 is exposed on the bottom surface 10b of the thermoelectric cooling chip 10, and the other end is adjacent to the outer heat release area R2.

[0037] According to an embodiment of the present invention, the semiconductor structure 1 is connected to the top surface 30a of the packaging substrate 30 in a flip chip manner. According to an embodiment of the present invention, for example, the active surface 20a of the heat source chip 20 of the semiconductor structure 1 is electrically connected to the corresponding pad 301 on the top surface 30a of the packaging substrate 30 through the conductive connector 210. According to some embodiments of the present invention, an underfill may be additionally filled between the top surface 30a of the packaging substrate 30 and the active surface 20a of the heat source chip 20. According to an embodiment of the present invention, for example, the conductive connector 210 may include, but is not limited to, solder, solder balls, bumps, micro bumps, copper pillars, copper bumps, etc.

[0038] According to an embodiment of the present invention, the packaging substrate 30 may include a cored substrate or a coreless substrate. According to other embodiments of the present invention, the packaging substrate 30 may include an interposer substrate. According to an embodiment of the present invention, the packaging substrate 30 may include a multi-layer build-up film DI and a multi-layer wiring layer IN. According to an embodiment of the present invention, for example, the build-up film DI may include a bismaleimide triazine (BT) resin or an Ajinomoto build-up film (ABF), but is not limited thereto. According to an embodiment of the present invention, for example, the wiring layer IN may include copper, but is not limited thereto.

[0039] According to the embodiment of the present invention, a pad 312 is further provided on the top surface 30a of the package substrate 30, and is electrically connected to the metal bonding pad 112 on the top surface 10a of the thermoelectric cooling chip 10 through the copper pillar 412 embedded in the molding compound 40. A ball pad 314 is further provided on the bottom surface 30b of the package substrate 30, and a solder ball SB is provided on the ball pad 314, for example, a ball grid array (BGA) solder ball.

[0040] According to an embodiment of the present invention, a heat sink 50 is further provided on the bottom surface 10b of the thermoelectric cooling chip 10, and its material includes, for example, aluminum, copper, graphene or other suitable high thermal conductivity materials. According to an embodiment of the present invention, a thermal interface material (TIM) 510 can be further provided between the heat sink 50 and the bottom surface 10b of the thermoelectric cooling chip 10 to improve the thermal conduction efficiency of the interface.

[0041] See also Figure 4 , which is a schematic cross-sectional view of a packaging structure according to another embodiment of the present invention, wherein the same regions, components, and layers are still represented by the same symbols. Figure 4 As shown, the package structure P1 also includes a package substrate 30 and a semiconductor structure 1 disposed on the package substrate 30, wherein the semiconductor structure 1, Figure 1 and Figure 2 As described in , it includes a thermoelectric cooling chip 10 and a heat source chip 20 arranged on the top surface 10a of the thermoelectric cooling chip 10. According to an embodiment of the present invention, the heat source chip 20 includes an active surface 20a and a passive surface 20b, wherein a plurality of output / input pads 201 may be arranged on the active surface 20a. The thermoelectric cooling chip 10 includes a substrate 100. According to an embodiment of the present invention, for example, the substrate 100 may be a silicon substrate. According to an embodiment of the present invention, the semiconductor structure 1 is covered by a molding compound 40.

[0042] According to an embodiment of the present invention, the passive surface 20b of the heat source chip 20 is directly connected to the top surface 10a of the thermal contact thermoelectric cooling chip 10. According to an embodiment of the present invention, the heat source chip 20 can be fixed on the top surface 10a of the thermoelectric cooling chip 10 by any suitable heat-conductive method, such as bonding or direct bonding. According to an embodiment of the present invention, the top surface 10a of the thermoelectric cooling chip 10 includes an N-type semiconductor layer 101 and a P-type semiconductor layer 102 formed in a three-dimensional stacking manner, which are arranged in a ring shape corresponding to the periphery of the heat source chip 20.

[0043] According to an embodiment of the present invention, the N-type semiconductor layer 101 and the P-type semiconductor layer 102 are made by semiconductor technology and are electrically connected to each other in pairs by wires 110, so as to form an annular inner heat absorption area R1 and an annular outer heat release area R2 as shown in the dotted area, wherein the outer heat release area R2 surrounds the inner heat absorption area R1. According to an embodiment of the present invention, for example, the wire 110 may include a copper wire, but is not limited thereto. According to an embodiment of the present invention, the N-type semiconductor layer 101 and the P-type semiconductor layer 102 on the top surface 10a of the thermoelectric cooling chip 10 may be a two-layer stack or a multi-layer stack of more than two layers in an alternating configuration.

[0044] According to an embodiment of the present invention, a metal bonding pad 112 is further included on the top surface 10a of the thermoelectric cooling chip 10, and the metal bonding pad 112 is electrically connected to the wire 110 and can be connected to an external signal to provide the current required by the thermoelectric cooling chip 10. According to an embodiment of the present invention, for example, the metal bonding pad 112 of the thermoelectric cooling chip 10 can be electrically connected to the corresponding pad 313 on the top surface 30a of the packaging substrate 30 through a bonding wire WB. According to an embodiment of the present invention, for example, the bonding wire WB can include a gold wire or a copper wire, but is not limited thereto.

[0045] According to an embodiment of the present invention, the bottom surface 10b of the thermoelectric cooling chip 10 of the semiconductor structure 1 can be adhered and fixed to the top surface 30a of the packaging substrate 30. According to an embodiment of the present invention, the packaging substrate 30 can be a core substrate or a coreless substrate. According to other embodiments of the present invention, the packaging substrate 30 can be an intermediate substrate. According to an embodiment of the present invention, the packaging substrate 30 can include a multi-layer build-up insulating film DI and a multi-layer wiring layer IN. According to an embodiment of the present invention, for example, the build-up insulating film DI can include BT resin or ABF, but is not limited thereto. According to an embodiment of the present invention, for example, the wiring layer IN can include copper, but is not limited thereto. A ball pad 314 is provided on the bottom surface 30b of the packaging substrate 30, and a solder ball SB is provided on the ball pad 314, for example, a BGA solder ball.

[0046] According to an embodiment of the present invention, a re-distribution layer (RDL) 60 is further provided on the molding material 40 and the active surface 20a of the heat source chip 20. According to an embodiment of the present invention, the re-distribution layer 60 may include an insulating layer DR and an internal connection layer IR, wherein the internal connection layer IR of the re-distribution layer 60 may be electrically connected to the output / input pad 201 on the active surface 20a of the heat source chip 20, and thus has the function of transmitting signals. According to an embodiment of the present invention, the insulating layer DR may include silicon oxide, silicon nitride, etc. According to an embodiment of the present invention, the internal connection layer IR may include copper. According to an embodiment of the present invention, the re-distribution layer 60 further includes a pad 612, for example, a copper pad, which is electrically connected to the pad 312 on the top surface 30a of the package substrate 30 through a copper column 412 embedded in the molding material 40. A through mold via (TMV) 414 is formed in the molding material 40 between the redistribution layer 60 and the top surface 10 a of the thermoelectric cooling chip 10 , wherein one end of the through mold via 414 thermally contacts the outer heat release region R2 of the thermoelectric cooling chip 10 .

[0047] According to an embodiment of the present invention, a heat sink 50 is further provided on the redistribution layer 60, and its material includes, for example, aluminum, copper, graphene or other suitable high thermal conductivity materials. According to an embodiment of the present invention, a thermal interface material 510 can be further provided between the heat sink 50 and the redistribution layer 60 to improve the thermal conductivity efficiency of the interface. According to an embodiment of the present invention, the heat of the outer heat release area R2 of the thermoelectric cooling chip 10 can be transferred to the heat sink 50 via the through-mold via 414, the thermal pad 613 in the redistribution layer 60, the thermal through-hole 614v and the thermal pad 614. According to some embodiments of the present invention, the bonding wire WB can be omitted, and the through-mold via 414 can be directly located on the metal bonding pad 112 for signal transmission.

[0048] Figures 5 to 17 A method for making a thermoelectric cooling chip is illustrated. Figure 5 As shown, a substrate 100 is first provided, for example, a silicon substrate, and then a silicon oxide layer 120, a silicon nitride layer 130 and a polysilicon layer 140 are sequentially deposited on the substrate 100. According to an embodiment of the present invention, the silicon oxide layer 120 can be used as a buffer layer, and the silicon nitride layer 130 can be used as an etching stop layer. Figure 6 As shown, a lithography process and an ion implantation process are then performed to form an N-type semiconductor layer 101 and a P-type semiconductor layer 102 at predetermined positions in the polysilicon layer 140. Figure 7 As shown, the polysilicon layer 140 other than the N-type semiconductor layer 101 and the P-type semiconductor layer 102 is removed by etching to expose a portion of the surface of the silicon nitride layer 130 .

[0049] like Figure 8As shown, a chemical vapor deposition (CVD) process is then performed to sequentially deposit a sacrificial layer 150, such as a silicon oxide layer, on the silicon nitride layer 130, the N-type semiconductor layer 101, and the P-type semiconductor layer 102, but is not limited thereto. Fig. 9 As shown, a photolithography process and a dry etching process are then performed to form an opening 150 g in the sacrificial layer 150 , so that the opening 150 g exposes the sidewalls of the N-type semiconductor layer 101 and the P-type semiconductor layer 102 .

[0050] like Fig.10 As shown, a metal layer 160 is formed on the sacrificial layer 150 and in the opening 150g by a sputtering process or a physical vapor deposition (PVD) process, for example, copper, titanium, cobalt, nickel, tungsten, but not limited thereto. In addition, the metal layer 160 can be selectively reacted with the sidewalls of the N-type semiconductor layer 101 and the P-type semiconductor layer 102 to form a metal silicide. Fig.11 As shown, the sacrificial layer 150 and the metal layer 160 on the sacrificial layer 150 are removed to form a first conductive line layer MS1.

[0051] like Fig.12 As shown, then, a silicon oxide layer 170 is deposited all over to sequentially cover the silicon nitride layer 130, the first wire layer MS1, the N-type semiconductor layer 101, and the P-type semiconductor layer 102. Fig.13 As shown, a planarization process, such as a chemical mechanical polishing (CMP) process, is performed to remove a portion of the thickness of the silicon oxide layer 170 so that the surface of the polished silicon oxide layer 170 is flush with the surfaces of the N-type semiconductor layer 101 and the P-type semiconductor layer 102 .

[0052] like Fig.14 As shown, a silicon nitride layer 131 and a sacrificial layer 151 are sequentially deposited on the surface of the silicon oxide layer 170 and the surfaces of the N-type semiconductor layer 101 and the P-type semiconductor layer 102, and an opening 151g is formed in the sacrificial layer 151 to expose a first conductive wire layer MS1 to be electrically connected to another semiconductor layer. Fig.15 As shown in FIG. 1 , a metal layer 161 is formed on the sacrificial layer 151 and in the opening 151g. Fig.16 As shown, the sacrificial layer 151 and the metal layer 161 on the sacrificial layer 151 are then removed to form the second wire layer MS2. At this time, the first wire layer MS1 is covered by the silicon nitride layer 131, while the second wire layer MS2 is not covered by the silicon nitride layer 131.

[0053] like Fig.17 As shown, repeat Figures 5 to 11The steps of forming a three-dimensional stacked structure of the N-type semiconductor layer 101 and the P-type semiconductor layer 102 and the third wire layer MS3, wherein the second wire layer MS2 and the third wire layer MS3 form an inner wire ML, electrically connecting the upper and lower stacked N-type semiconductor layers 101 and the P-type semiconductor layer 102 on the same side. Fig.12 and the planarization process shown in FIG. 13 . The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Explanation of symbols

Claims

1. A thermoelectric cooling chip, characterized in that: Include: a base; a buffer layer disposed on the surface of the substrate; a first etch stop layer disposed on the buffer layer; a dielectric layer disposed on the first etch stop layer; a first conductive type semiconductor layer buried in the dielectric layer; A first conductive line layer is disposed in the dielectric layer and directly contacts the side wall of the first conductive type semiconductor layer; a second etching stop layer, disposed on the first conductive type semiconductor layer; a second conductive line layer disposed in the dielectric layer and the second etching stop layer and directly contacting the sidewall of the first conductive type semiconductor layer; a second conductive type semiconductor layer, located on the first conductive type semiconductor layer; as well as A third conductive line layer is disposed on the second conductive line layer and directly contacts the side wall of the second conductive type semiconductor layer.

2. The thermoelectric cooling chip according to claim 1, characterized in that: The substrate includes a silicon substrate.

3. The thermoelectric cooling chip according to claim 1, characterized in that: The first conductive type semiconductor layer is a P-type doped polysilicon layer, and the second conductive type semiconductor layer is an N-type doped polysilicon layer.

4. The thermoelectric cooling chip according to claim 1, characterized in that: The first conductive type semiconductor layer is an N-type doped polysilicon layer, and the second conductive type semiconductor layer is a P-type doped polysilicon layer.

5. The thermoelectric cooling chip according to claim 1, characterized in that: The buffer layer includes a silicon oxide layer, the first etching stop layer includes a silicon nitride layer, and the second etching stop layer includes a silicon nitride layer.

6. The thermoelectric cooling chip according to claim 1, characterized in that: The dielectric layer includes a silicon oxide layer.

7. The thermoelectric cooling chip according to claim 1, characterized in that: The second conductive type semiconductor layer and the first conductive type semiconductor layer are electrically isolated from each other by the second etching stop layer.

8. A method for forming a thermoelectric cooling chip, characterized in that: Include: providing a substrate; forming a buffer layer on the surface of the substrate; forming a first etch stop layer on the buffer layer; forming a dielectric layer on the first etch stop layer; forming a first conductive type semiconductor layer in the dielectric layer; Forming a first conductive line layer in the dielectric layer, directly contacting the sidewall of the first conductive type semiconductor layer; forming a second etching stop layer on the first conductive type semiconductor layer; forming a second conductive line layer in the dielectric layer and the second etching stop layer, directly contacting the sidewall of the first conductive type semiconductor layer; forming a second conductive type semiconductor layer on the first conductive type semiconductor layer; and A third conductive line layer is formed on the second conductive line layer to directly contact the side wall of the second conductive type semiconductor layer.

9. A packaging structure, characterized in that: Include: a packaging substrate; A heat source chip, comprising an active surface and a passive surface, wherein the active surface is connected to the packaging substrate; A thermoelectric cooling chip, comprising a top surface and a bottom surface, wherein the passive surface of the heat source chip is in thermal contact with the top surface of the thermoelectric cooling chip, wherein the top surface of the thermoelectric cooling chip comprises a plurality of N-type semiconductor layers and P-type semiconductor layers formed in a three-dimensional stacking manner and arranged in a ring shape corresponding to the periphery of the heat source chip; A molded plastic covering the heat source chip and the thermoelectric cooling chip, exposing the bottom surface of the thermoelectric cooling chip; and A heat sink is arranged on the bottom surface of the thermoelectric cooling chip.

10. A packaging structure, characterized in that: Include: a packaging substrate; A heat source chip including an active surface and a passive surface; A thermoelectric cooling chip, comprising a top surface and a bottom surface, wherein the passive surface of the heat source chip is in thermal contact with the top surface of the thermoelectric cooling chip, wherein the top surface of the thermoelectric cooling chip comprises a plurality of N-type semiconductor layers and P-type semiconductor layers formed in a three-dimensional stacking manner and arranged in a ring shape corresponding to the periphery of the heat source chip, wherein the bottom surface of the thermoelectric cooling chip is fixed on the packaging substrate; A molded plastic covering the heat source chip and the thermoelectric cooling chip; a redistribution layer disposed on the molding compound and the active surface of the heat source chip; and A heat dissipation element is arranged on the redistribution layer.

Images