Condition-adaptive semiconductor chip array test system

Abstract

The invention relates to the technical field of semiconductor chips, and discloses a condition-adaptive semiconductor chip array test system, which comprises a PC (Personal Computer) end, a semiconductor device array and a control module, and is characterized in that the PC end and the semiconductor device array are respectively connected with the control module; the control module comprises an acquisition unit, a gating array unit, an impedance adjustment unit and a test unit; the acquisition unit is used for acquiring a semiconductor device signal and determining a gating mode according to the semiconductor device signal; the gating array unit is used for determining the switching speed and the conduction resistance according to the gating mode; the impedance adjusting unit is used for adjusting the access resistance to a target resistance; the test unit is used for applying excitation to a to-be-tested device of the semiconductor device array and controlling the acquisition unit to acquire a response signal of the to-be-tested device. According to the invention, the test efficiency and precision are significantly improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor chips, and in particular to an adaptive condition semiconductor chip array testing system. Background Art

[0002] In the context of today's technological development, the preparation and application of large-scale semiconductor devices are gradually becoming a hot topic of research. However, the testing and application process of large-scale device arrays often requires a lot of time and effort, and the experimental operation is relatively cumbersome. For example, in the testing phase of semiconductor devices such as memristors and photodetectors, due to the limitations of the test equipment, the number of devices that can be tested each time is limited, which results in a considerable amount of time to complete the entire test task. In addition, since most semiconductor devices are relatively small in size, the test operation usually needs to be performed under a microscope. If the device needs to be aligned under a microscope for each test, this will undoubtedly greatly reduce the efficiency of the test, making the entire test process more complicated and time-consuming.

[0003] Therefore, it is necessary to design a semiconductor chip array test system with adaptive conditions to solve the problems existing in the current technology. Summary of the invention

[0004] In view of this, the present invention proposes a semiconductor chip array test system with adaptive conditions, aiming to achieve fast switching of different devices in a semiconductor device array, simplify the test process, and improve the test efficiency.

[0005] The present invention provides a semiconductor chip array test system with adaptive conditions, comprising:

[0006] A PC terminal, a semiconductor device array and a control module, wherein the PC terminal and the semiconductor device array are respectively connected to the control module; the control module comprises a collection unit, a gate array unit, an impedance adjustment unit and a test unit;

[0007] The acquisition unit is used to acquire semiconductor device signals and determine a gating mode according to the semiconductor device signals;

[0008] The gating array unit is used to determine the switching speed and the on-resistance according to the gating mode;

[0009] The impedance adjustment unit is used to adjust the path resistance to a target resistance;

[0010] The testing unit is used to apply excitation to the devices under test of the semiconductor device array, and control the collecting unit to collect response signals of the devices under test.

[0011] Further, determining the gating mode according to the semiconductor device signal includes:

[0012] Detecting the response signal voltage of the device under test by using an ADC, and converting the response signal voltage into a digital signal;

[0013] A digital signal processing algorithm is used to obtain characteristic data of the digital signal, and a gating mode is determined according to the characteristic data.

[0014] Furthermore, the gating modes include: sequential gating, reverse gating, cyclic gating and random gating.

[0015] Furthermore, the gate array unit is composed of five analog switch chips, and the analog switch chips are high-speed and low-resistance analog switch chips.

[0016] Further, when determining the switching speed and the on-resistance according to the gating mode, it includes:

[0017] When the gating mode is sequential gating, determining the switching speed to be a first switching speed, and determining the on-resistance to be a first on-resistance;

[0018] When the gating mode is reverse gating, determining the switching speed to be a second switching speed, and determining the on-resistance to be a second on-resistance;

[0019] When the gating mode is cyclic gating or random gating, determining the switching speed to be a third switching speed, and determining the on-resistance to be a third on-resistance;

[0020] The first switching speed is less than the second switching speed, and the second switching speed is less than the third switching speed; the first on-resistance is greater than or equal to the second on-resistance, and the second on-resistance is greater than the third on-resistance.

[0021] Furthermore, when adjusting the path resistance to the target resistance, the steps include:

[0022] Collecting an average resistance value of the semiconductor device array, comparing the average resistance value with an average resistance threshold value, and adjusting the path resistance value according to the comparison result;

[0023] When the average resistance is less than or equal to the average resistance threshold, the impedance adjustment unit increases the path resistance to the target resistance;

[0024] When the average resistance is greater than the average resistance threshold, the path resistance is lowered to the target resistance by the impedance adjustment unit.

[0025] Furthermore, the test unit includes a plurality of semiconductor test devices; the semiconductor test devices include one or more of a source meter, a keyley4200, an Agilent4155b, an oscilloscope and a signal generator.

[0026] Furthermore, the control module controls the test operation of the test unit through a level triggering method or an interface communication method.

[0027] Compared with the prior art, the present invention has the following beneficial effects:

[0028] The semiconductor device array testing system proposed in the present invention has excellent compatibility and can be adapted to a variety of semiconductor testing equipment.

[0029] The present invention can use low-resistance analog switch chips to reduce interference with semiconductor device parameter testing; it can also use high-speed analog switch chips to quickly switch analog switches to achieve rapid testing of semiconductor devices. At the same time, the system also supports the selection of high-speed low-resistance analog switch chips to meet the needs of different application scenarios.

[0030] The present invention introduces an impedance adjustment module, which can automatically adjust to the target impedance through the control module according to the actual needs of the semiconductor device, thereby regulating the current flowing through the semiconductor device, ensuring the stability of the semiconductor device test, and simplifying the data processing process.

[0031] The present invention adopts a closed-loop control system, which is composed of PC-side software, a control unit, a gating circuit and a semiconductor array. The PC-side software can send adjustment instructions to the control unit according to the collected semiconductor device test results, and the control unit further regulates the gating circuit and the impedance adjustment unit, thereby changing the path of the semiconductor array (including signal impedance, signal channel, etc.), significantly improving the efficiency and accuracy of the test.

[0032] The design of the present invention is concise and clear, and the cost is low, so it is easy for designers to master and apply in actual design work. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present invention. Moreover, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0034] Figure 1 A structural block diagram of a semiconductor chip array testing system with adaptive conditions provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0035] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art. It should be noted that, in the absence of conflict, the embodiments of the present invention and the features described in the embodiments can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0036] See also Figure 1 As shown, in some embodiments of the present application, this embodiment provides a semiconductor chip array test system with adaptive conditions, including:

[0037] A PC terminal, a semiconductor device array and a control module, wherein the PC terminal and the semiconductor device array are respectively connected to the control module; the control module comprises a collection unit, a gate array unit, an impedance adjustment unit and a test unit;

[0038] The acquisition unit is used to acquire semiconductor device signals and determine a gating mode according to the semiconductor device signals;

[0039] The gating array unit is used to determine the switching speed and the on-resistance according to the gating mode;

[0040] The impedance adjustment unit is used to adjust the path resistance to a target resistance;

[0041] The testing unit is used to apply excitation to the devices under test of the semiconductor device array, and control the collecting unit to collect response signals of the devices under test.

[0042] In this embodiment, the analog switch selection signals (specifically the signals output by the 5-bit counter module) A4, A3, A2, A1, A0 in the control module, and the chip selection signal EN are all generated by the STM32 system. These signals mainly play the following five functions: first, control the gate array unit, regulate the connection between the semiconductor device and the test equipment according to specific rules, so as to realize signal collection or measurement; second, collect the signal of the semiconductor device through the gate array unit, and adjust the working mode of the gate array accordingly, including but not limited to the gate speed, gate sequence and the gate of specific devices; third, establish communication with the test instrument, and remotely control the test operation of the test equipment by means of serial port interface communication (such as GPIB, UART, etc.), such as the sending of start, stop, pause and test simulation instructions; fourth, establish a communication bridge with the PC side through the serial port, receive control instructions from the PC side, and set control parameters, such as gate speed, gate sequence, gate number and control the start, stop and pause of the gate, so as to realize precise control of the gate array operation; fifth, also communicate with the PC side through the serial port, and feed back the semiconductor device signal or scanning status (such as current gate parameters, etc.) collected by the control module to the PC side, so as to facilitate real-time monitoring of the control unit, the gate array and the working status of the semiconductor device.

[0043] It can be understood that the semiconductor chip array test system with adaptive conditions provided in this embodiment can realize efficient testing of semiconductor device arrays. During the test process, the system can automatically select appropriate test modes and parameters according to the characteristics of the semiconductor device, thereby ensuring the accuracy and repeatability of the test. In this way, the test system of the present invention not only improves the test efficiency, but also reduces the test cost, providing strong technical support for the mass production and quality control of semiconductor devices.

[0044] Specifically, determining the gating mode according to the semiconductor device signal includes:

[0045] Detecting the response signal voltage of the device under test by using an ADC, and converting the response signal voltage into a digital signal;

[0046] A digital signal processing algorithm is used to obtain characteristic data of the digital signal, and a gating mode is determined according to the characteristic data.

[0047] In the present embodiment, ADC is an analog-to-digital converter, which is used to convert analog signals into digital signals for computer processing. The conversion accuracy and speed of ADC directly affect the performance of the test system. In the present invention, the use of ADC ensures high accuracy and high efficiency of signal acquisition, thereby providing a reliable data basis for subsequent digital signal processing.

[0048] In this embodiment, the characteristic data includes the amplitude, frequency and phase information of the response signal. Through these characteristic data, the system can identify the specific state and performance parameters of the semiconductor device, so as to select the most appropriate test mode. For example, for high-speed switching devices, the system will give priority to the rise time and fall time of the signal, while for low-noise amplifiers, it will pay more attention to the signal-to-noise ratio and linearity of the signal.

[0049] Specifically, the gating modes include: sequential gating, reverse gating, cyclic gating and random gating.

[0050] In this embodiment, sequential gating is to control the sequential gating of devices 0 to n, reverse gating is to control the sequential gating of devices n to 0, cyclic gating is to control the cyclic gating of devices 0 to n to 0..., and random gating is to randomly gating certain arrays for targeted testing, such as only gating devices 0, 8, 13, 25...

[0051] Specifically, the gate array unit is composed of five analog switch chips, and the analog switch chips are high-speed and low-resistance analog switch chips.

[0052] In this embodiment, in actual application, the control module dynamically adjusts the working mode of the gate array unit according to the scale and test requirements of the semiconductor device array. For example, when a full scan test is required for the entire array, the system will use a sequential gate mode; when a specific area or a specific device is tested, a reverse gate or a cyclic gate mode may be used. The random gate mode is suitable for scenarios where repeated testing or fault diagnosis of a specific device is required.

[0053] Specifically, when determining the switching speed and the on-resistance according to the gating mode, it includes:

[0054] When the gating mode is sequential gating, determining the switching speed to be a first switching speed, and determining the on-resistance to be a first on-resistance;

[0055] When the gating mode is reverse gating, determining the switching speed to be a second switching speed, and determining the on-resistance to be a second on-resistance;

[0056] When the gating mode is cyclic gating or random gating, determining the switching speed to be a third switching speed, and determining the on-resistance to be a third on-resistance;

[0057] The first switching speed is less than the second switching speed, and the second switching speed is less than the third switching speed; the first on-resistance is greater than or equal to the second on-resistance, and the second on-resistance is greater than the third on-resistance.

[0058] In this embodiment, the first on-resistance is set to ensure the stability and accuracy of signal transmission in the sequential gating mode, because the signal transmission path in the sequential gating mode is long, and a larger on-resistance is required to reduce signal attenuation. The second on-resistance is set in the reverse gating mode, because the signal transmission path is short, and the on-resistance can be appropriately reduced to increase the signal transmission speed. As for the cyclic gating or random gating mode, since it may involve frequent switching, it is necessary to set a moderate on-resistance and switching speed to balance the stability and speed of signal transmission.

[0059] Specifically, when adjusting the path resistance to the target resistance, it includes:

[0060] Collecting an average resistance value of the semiconductor device array, comparing the average resistance value with an average resistance threshold value, and adjusting the path resistance value according to the comparison result;

[0061] When the average resistance is less than or equal to the average resistance threshold, the impedance adjustment unit increases the path resistance to the target resistance;

[0062] When the average resistance is greater than the average resistance threshold, the path resistance is lowered to the target resistance by the impedance adjustment unit.

[0063] In this embodiment, the resistance of the path is adjusted manually or automatically by a resistance adjustment device such as a variable resistor or a digital potentiometer, so that the resistance of the path is adjusted to a target resistance;

[0064] In this embodiment, the impedance adjustment unit is to ensure that the resistance of the semiconductor device array can be accurately controlled during the test process to adapt to different test conditions and requirements. By real-time monitoring and adjusting the path resistance, the system can maintain the stability and accuracy of the test signal, thereby improving the reliability of the overall test. For example, when the test environment or device characteristics change, the impedance adjustment unit can quickly respond and adjust the path resistance to adapt to the new test conditions. This dynamic adjustment mechanism is an important feature of the test system of the present invention, which enables the test system to adapt to various complex and changeable test scenarios and ensure the consistency and repeatability of the test results.

[0065] Specifically, the test unit includes a plurality of semiconductor test devices; the semiconductor test devices include one or more of a source meter, a keyley4200, an Agilent4155b, an oscilloscope and a signal generator.

[0066] In this embodiment, the configuration of the test unit can be flexibly adjusted according to different test requirements. For example, for tests that require precise current control, a source meter device can be used; while for applications that require high-speed signal measurement, the Keithley 4200 semiconductor parameter analyzer and the Agile 4155B semiconductor parameter analyzer provide high-speed and high-precision signal measurement capabilities. The oscilloscope is used to observe and record signal waveforms, while the signal generator is used to generate specific signals required for testing. Through the combined use of these devices, the test unit can perform various complex test tasks, including DC parameter testing, AC parameter testing, transient analysis, and frequency characteristic analysis.

[0067] Specifically, the control module controls the test operation of the test unit through a level triggering method or an interface communication method.

[0068] In this embodiment, the control module controls the test operation of the test unit through a level trigger mode or an interface communication mode. The level trigger mode allows the test system to start or stop the test immediately after receiving a specific level signal, which is suitable for test scenarios that require a quick response. The interface communication mode exchanges data with the interface of the test unit to achieve more complex control logic and test process management.

[0069] In summary, the semiconductor chip array test system with adaptive conditions provided in this example can flexibly adjust the test parameters and operating procedures according to different test requirements, thereby realizing efficient and accurate testing of semiconductor chip arrays. The system can not only adapt to various test conditions, but also provide customized test solutions for specific test requirements, which greatly improves the flexibility and efficiency of the test. In addition, the design of the system takes into account the stability and accuracy of the signal, ensuring the reliability and repeatability of the test results, which is of great significance for the research and development and production of semiconductor devices. Through this adaptive condition test system, the product development cycle can be effectively shortened, the test cost can be reduced, and the market competitiveness of the product can be improved.

[0070] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0071] The present application is described with reference to flowcharts and / or block diagrams of methods, devices (systems) and computer program products according to embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0072] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0073] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0074] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in the relevant field should understand that the specific implementation methods of the present invention can still be modified or replaced by equivalents. Any modification or equivalent replacement that does not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A semiconductor chip array test system with self-adaptive conditions, characterized in that: include: A PC terminal, a semiconductor device array and a control module, wherein the PC terminal and the semiconductor device array are respectively connected to the control module; the control module comprises a collection unit, a gate array unit, an impedance adjustment unit and a test unit; The acquisition unit is used to acquire semiconductor device signals and determine a gating mode according to the semiconductor device signals; The gating array unit is used to determine the switching speed and the on-resistance according to the gating mode; The impedance adjustment unit is used to adjust the path resistance to a target resistance; The testing unit is used to apply excitation to the devices under test of the semiconductor device array, and control the collecting unit to collect response signals of the devices under test.

2. The semiconductor chip array test system with self-adaptive conditions according to claim 1, characterized in that: Determining the gating mode according to the semiconductor device signal includes: Detecting the response signal voltage of the device under test by using an ADC, and converting the response signal voltage into a digital signal; A digital signal processing algorithm is used to obtain characteristic data of the digital signal, and a gating mode is determined according to the characteristic data.

3. The semiconductor chip array test system with self-adaptive conditions according to claim 2, characterized in that: The gating modes include: sequential gating, reverse gating, cyclic gating and random gating.

4. The semiconductor chip array test system with self-adaptive conditions according to claim 1, characterized in that: The gate array unit is composed of five analog switch chips, and the analog switch chips are high-speed and low-resistance analog switch chips.

5. The semiconductor chip array test system with self-adaptive conditions according to claim 1, characterized in that: When determining the switching speed and the on-resistance according to the gating mode, it includes: When the gating mode is sequential gating, determining the switching speed to be a first switching speed, and determining the on-resistance to be a first on-resistance; When the gating mode is reverse gating, determining the switching speed to be a second switching speed, and determining the on-resistance to be a second on-resistance; When the gating mode is cyclic gating or random gating, determining the switching speed to be a third switching speed, and determining the on-resistance to be a third on-resistance; The first switching speed is less than the second switching speed, and the second switching speed is less than the third switching speed; the first on-resistance is greater than or equal to the second on-resistance, and the second on-resistance is greater than the third on-resistance.

6. The semiconductor chip array test system with self-adaptive conditions according to claim 1, characterized in that: When adjusting the path resistance to the target resistance, include: Collecting an average resistance value of the semiconductor device array, comparing the average resistance value with an average resistance threshold value, and adjusting the path resistance value according to the comparison result; When the average resistance is less than or equal to the average resistance threshold, the impedance adjustment unit increases the path resistance to the target resistance; When the average resistance is greater than the average resistance threshold, the path resistance is lowered to the target resistance by the impedance adjustment unit.

7. The semiconductor chip array test system with self-adaptive conditions according to claim 1, characterized in that: The test unit includes a plurality of semiconductor test devices; the semiconductor test devices include one or more of a source meter, a Keithley 4200, an Agilent 4155b, an oscilloscope and a signal generator.

8. The semiconductor chip array test system with self-adaptive conditions according to claim 1, characterized in that: The control module controls the test operation of the test unit through a level triggering mode or an interface communication mode.

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