Method for converting neural network training model into Verilog-A language device model

Abstract

The invention discloses a method for converting a neural network training model based on a python language into a VerlogA language model, and the method comprises the steps: enabling a trained model to generate a device model which accords with the VerlogA grammar description through a python code; comprising the steps of describing a neural network structure, reading a model weight and model bias generated by a neural network, outputting a Verilog-A module statement and a model port by using a python script, reading out the model weight by using the script, reading out the model bias by using the script, and reading out neuron input and output by using the script. The script is used for defining input and output variables of different layers of neurons in the neural network, the script is used for defining an activation function, the script is used for defining source and drain ports, and the script is used for defining normalization operation. Using scripts to define neuron connection relations and activate function operation. According to the method, the model trained by the neural network is described into the device model based on the Verilog-A language based on the python code, so that the conversion from the model trained by the neural network based on the python to the model of the Verilog-A language is quickly realized, the conversion efficiency of the model is greatly improved, and the device model training and circuit simulation efficiency is greatly improved.

Description

Technical Field

[0001] The present invention relates to the field of device modeling, and in particular to a method for converting a model trained by a neural network into a Verilog-A language device model. Background Art

[0002] As a hardware description language, Verilog-A plays an important role in the design and simulation of analog and mixed-signal circuits. With the widespread application of artificial neural networks (ANN) in the field of device modeling, how to efficiently convert the trained neural network results into Verilog-A models has become a key issue. Current methods may require manual writing and debugging of large amounts of Verilog-A code, which is not only time-consuming and labor-intensive, but also prone to errors. Summary of the invention

[0003] In view of the above-mentioned defects of the prior art, the technical problem to be solved by the present invention is that the existing artificial neural network conversion to Verilog-A model requires manual writing and debugging of a large amount of Verilog-A code, which is time-consuming, labor-intensive, and prone to errors. The present invention provides a method for converting a neural network trained model to a Verilog-A language device model, which can efficiently and automatically convert the trained neural network results into Verilog-A code, significantly improves the application efficiency of the neural network results in circuit simulation, and reduces the programming complexity of the model creator.

[0004] To achieve the above object, the present invention provides a method for converting a model trained by a neural network into a Verilog-A language device model, which specifically comprises the following steps:

[0005] Generate device definitions that conform to Verilog-A syntax;

[0006] After generating a device definition that conforms to the Verilog-A syntax, instantiate the variables that conform to the Verilog-A syntax;

[0007] Read the weights and biases obtained after neural network training, and generate device parameter expressions that conform to Verilog-A syntax;

[0008] After reading the parameter expressions and instantiating the variables, an activation function conforming to the Verilog-A syntax is generated;

[0009] After the activation function is defined, the neuron connection relationship and activation function operation that conform to the Verilog-A syntax are output;

[0010] After the operation relationship is defined, the device port charge transport relationship that conforms to the Verilog-A syntax is output;

[0011] Finally, the end statement that complies with the Verilog-A model is output, and a device model that complies with Verilog-A is generated.

[0012] Furthermore, the device definition includes header file definition, model name, model port, setting port input and output characteristics, and port electrical declaration.

[0013] Furthermore, variables conforming to Verilog-A syntax include neurons in a neural network, ports, and variables used in a calculation process.

[0014] Furthermore, the parameter expression is set to output the parameter first, then the parameter name, and finally the corresponding parameter value.

[0015] Furthermore, the activation function includes different activation functions, specifically including an activation function from an input layer to a hidden layer, an activation function between hidden layers, and an activation function between a hidden layer and an output layer.

[0016] Furthermore, a device definition conforming to the Verilog-A syntax is generated, specifically including generating a header file conforming to the Verilog-A syntax to define relevant parameters of the analog signal type, defining it in the Verilog-A device model, including the device name, the number of ports of the device, and specifying the output port, assigning electrical properties to each port, and then using and outputting module declarations, device port definitions, and electrical declarations conforming to the Verilog-A syntax in the model python language.

[0017] Furthermore, the weights and biases obtained after the neural network training are read, and a device parameter expression conforming to the Verilog-A syntax is generated. Specifically, the model obtained after the ANN training is described by weights W and biases B. In the Verilog-A model, the weights and biases obtained after the ANN training are the device model parameters. The weights W1_x_y between the input layer neurons and the hidden layer neurons obtained after the ANN training need to be input, where x and y represent the neuron number, the weight W2_x_y between the hidden layer neurons and the next hidden layer neurons, and the weight W3_x_y between the hidden layer neurons and the output layer neurons; the python language is used to read the weights between each adjacent neuron in the ANN model, and the information is stored according to the number, and the output is in the form of parameters conforming to the Verilog-A syntax.

[0018] Furthermore, after the operation relationship is defined, the device port charge transport relationship that conforms to the Verilog-A syntax is output, specifically including: initially multiplying the output value of the first neuron in the previous layer by the corresponding weight coefficient as the starting point, multiplying the output values ​​of the remaining neurons in the previous layer by their corresponding weight coefficients through a loop, and adding them to the sum in turn, adding the above weighted summation result to the bias term of the neuron to generate the input expression of the neuron, and writing it into the Verilog-A module, the code uses the generated neuron input expression as the input of the activation function, and calculates the output value of the neuron; the calculated output value is used as the output of the neuron and is written into the Verilog-A module.

[0019] Furthermore, finally, an end statement conforming to the Verilog-A model is output, and a device model conforming to Verilog-A is generated, specifically including determining the connection relationship of the output port to dynamically handle the working mode of the device under different voltage conditions and adjust the corresponding voltage value, and then outputting an end statement conforming to the Verilog-A model to generate a device model conforming to Verilog-A.

[0020] Technical Effects

[0021] The present invention provides a method for converting a neural network training model into a Verilog-A language device model, which realizes the rapid conversion of the Python-based neural network training model into a Verilog-A language model, greatly improves the model conversion efficiency and thus greatly improves the device model training and circuit simulation efficiency.

[0022] The concept, specific structure and technical effects of the present invention will be further described below to fully understand the purpose, characteristics and effects of the present invention. DETAILED DESCRIPTION

[0023] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0024] In the following description, specific details such as specific internal procedures and techniques are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present invention. However, it should be clear to those skilled in the art that the present invention may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present invention.

[0025] The embodiment of the present invention provides a method for converting a model trained by a neural network into a Verilog-A language device model, which specifically includes the following steps:

[0026] Step 100, generating a device definition in accordance with Verilog-A syntax, wherein the device definition includes a header file definition, a model name, a model port, setting port input and output characteristics, and a port electrical declaration. Specifically, it includes generating a header file in accordance with Verilog-A syntax to define the relevant parameters of the analog signal type, defining it in the Verilog-A device model, including the device name, the number of ports of the device, and specifying the output port, assigning electrical properties to each port, and then using and outputting the module declaration, device port definition, and electrical declaration in accordance with Verilog-A syntax in the model python language. In this embodiment, the discipline.h header file is first defined in the Verilog-A module, which defines some key concepts in electrical engineering; then, the transistor name and the corresponding four ports are defined: drain, gate, source and body, which are used to connect with other circuits or modules; then, the four ports are declared as bidirectional ports, indicating that they can be used as input or output, thereby realizing bidirectional transmission of signals; and the four ports of drain, gate, source and body are defined as electrical types, indicating that they correspond to electrical signals or nodes, which can carry current or voltage.

[0027] Step 200, after generating the device definition conforming to the Verilog-A syntax, define the variables conforming to the Verilog-A syntax, wherein the variables conforming to the Verilog-A syntax include the neuron ports in the neural network and the variables used in the operation process. After the variables are defined, they can be more clearly recognized by the compiler.

[0028] Step 300, read the weights and biases obtained after the neural network training, and generate a device parameter expression that conforms to the Verilog-A syntax. The parameter expression is set to output the parameters first, then the parameter names, and finally the corresponding parameter values. The weights and biases output by the neural network are read using a python script, and the input layer, output layer, hidden layer number, and the number of neurons corresponding to each layer of the neural network are defined and described in detail through the python script; specifically, the model obtained after ANN training is described by weights W and biases B. In the Verilog-A model, the weights and biases obtained after ANN training are the device model parameters, and the weights W1_x_y between the input layer neurons and the hidden layer neurons obtained after ANN training need to be input, where x and y represent the neuron number, the weights W2_x_y between the hidden layer neurons and the next hidden layer neurons, and the weights W3_x_y between the hidden layer neurons and the output layer neurons; the weights between each adjacent neuron in the ANN model are read using the python language, and the information is stored according to the number, and the output is in the form of parameters that conform to the Verilog-A syntax. In the Verilog-A model, after the device parameters are read, each neuron of the ANN neural network and each variable used need to be instantiated so that the compiler can recognize the variables.

[0029] Step 400, after reading the parameter expression and instantiating the variable, generate an activation function that complies with the Verilog-A syntax; the activation function includes different activation functions, specifically including the activation function from the input layer to the hidden layer, the activation function between the hidden layer and the hidden layer, and the activation function between the hidden layer and the output layer. Among them, the activation function that complies with the Verilog-A syntax is output using the python language, such as the hyperbolic tangent function and the logarithmic sigmoid function, which are usually used to simulate nonlinear behavior in circuits or the implementation of neural networks

[0030] Step 500, after the activation function is defined, output the neuron connection relationship and activation function operation that conform to the Verilog-A syntax; initially, the output value of the first neuron in the previous layer is multiplied by the corresponding weight coefficient as the starting point, and the output values ​​of the remaining neurons in the previous layer are multiplied by their corresponding weight coefficients through a loop, and added to the sum in turn, and the above weighted summation result is added to the bias term (bias) of the neuron to generate the input expression of the neuron, and written into the Verilog-A module.

[0031] Combine the bias and weight of the read neuron and use the corresponding activation function to connect the input and output of the neuron.

[0032] Step 600, after the definition of the operation relationship is completed, the device port charge transport relationship conforming to the Verilog-A syntax is output; specifically, the following steps are performed: initially, the output value of the first neuron in the previous layer is multiplied by the corresponding weight coefficient as a starting point, and the output values ​​of the remaining neurons in the previous layer are multiplied by their corresponding weight coefficients through a loop, and are added to the sum in sequence, and the above weighted summation result is added to the bias term of the neuron to generate the input expression of the neuron, and is written into the Verilog-A module, the code uses the generated neuron input expression as the input of the activation function, and calculates the output value of the neuron; the calculated output value is used as the output of the neuron, and is written into the Verilog-A module.

[0033] Step 700, finally, output the end statement that conforms to the Verilog-A model, and generate a device model that conforms to Verilog-A. Use the connection relationship of the python script output port to dynamically process the working mode of the device under different voltage conditions, and adjust the corresponding voltage value, and then output the end statement that conforms to the Verilog-A model to generate a device model that conforms to Verilog-A. Wherein, use the connection relationship of the python script output port to assign the above calculation results to the corresponding device port, for example:

[0034] neuron0_1_out=vds;

[0035] neuron0_2_out=vgs.

[0036] The present invention provides a method for converting a neural network training model into a Verilog-A language device model, which realizes the rapid conversion of the Python-based neural network training model into a Verilog-A language model, greatly improves the model conversion efficiency and thus greatly improves the device model training and circuit simulation efficiency, and realizes cross-domain model conversion.

[0037] The preferred specific embodiments of the present invention are described in detail above. It should be understood that a person skilled in the art can make many modifications and changes based on the concept of the present invention without creative work. Therefore, any technical solution that can be obtained by a person skilled in the art through logical analysis, reasoning or limited experiments based on the concept of the present invention on the basis of the prior art should be within the scope of protection determined by the claims.

Claims

1. A method for converting a neural network training model into a Verilog-A language device model, characterized in that: The specific steps include: Generate device definitions that conform to Verilog-A syntax; After generating a device definition that conforms to the Verilog-A syntax, instantiate the variables that conform to the Verilog-A syntax; Read the weights and biases obtained after neural network training, and generate device parameter expressions that conform to Verilog-A syntax; After reading the parameter expressions and instantiating the variables, an activation function conforming to the Verilog-A syntax is generated; After the activation function is defined, the neuron connection relationship and activation function operation that conform to the Verilog-A syntax are output; After the operation relationship is defined, the device port charge transport relationship that conforms to the Verilog-A syntax is output; Finally, the end statement that complies with the Verilog-A model is output, and a device model that complies with Verilog-A is generated.

2. The method for converting a neural network training model into a Verilog-A language device model as claimed in claim 1, characterized in that: The device definition includes header file definition, model name, model port, setting port input and output characteristics, and port electrical declaration.

3. The method for converting a neural network training model into a Verilog-A language device model as claimed in claim 1, characterized in that: Variables that conform to Verilog-A syntax include neurons in a neural network, ports, and variables used in the calculation process.

4. The method for converting a neural network training model to a Verilog-A language device model as claimed in claim 1, characterized in that: The parameter expression is set to output the parameter first, then the parameter name, and finally the corresponding parameter value.

5. The method for converting a neural network training model into a Verilog-A language device model as claimed in claim 1, characterized in that: The activation function includes different activation functions, specifically including the activation function from the input layer to the hidden layer, the activation function between the hidden layer and the hidden layer, and the activation function between the hidden layer and the output layer.

6. The method for converting a neural network training model into a Verilog-A language device model as claimed in claim 2, characterized in that: Generate device definitions that conform to Verilog-A syntax, specifically including generating header files that conform to Verilog-A syntax to define relevant parameters of analog signal types, defining them in the Verilog-A device model, including device name, number of device ports, specifying output ports, assigning electrical properties to each port, and then using and outputting module declarations, device port definitions, and electrical declarations that conform to Verilog-A syntax in the model python language.

7. The method for converting a neural network training model into a Verilog-A language device model as claimed in claim 1, characterized in that: The weights and biases obtained after the neural network training are read, and the device parameter expressions conforming to the Verilog-A syntax are generated. Specifically, the model obtained after the ANN training is described by the weights W and the biases B. In the Verilog-A model, the weights and biases obtained after the ANN training are the device model parameters. The weights W1_x_y between the input layer neurons and the hidden layer neurons obtained after the ANN training need to be input, where x and y represent the neuron number, the weight W2_x_y between the hidden layer neurons and the next hidden layer neurons, and the weight W3_x_y between the hidden layer neurons and the output layer neurons; the python language is used to read the weights between each adjacent neuron in the ANN model, and the information is stored according to the number, and the output is in the form of parameters conforming to the Verilog-A syntax.

8. The method for converting a neural network training model into a Verilog-A language device model as claimed in claim 7, characterized in that: After the operation relationship is defined, the device port charge transport relationship that conforms to the Verilog-A syntax is output, specifically including: initially multiplying the output value of the first neuron in the previous layer by the corresponding weight coefficient as the starting point, multiplying the output values ​​of the remaining neurons in the previous layer by their corresponding weight coefficients through a loop, and adding them to the sum in turn, adding the above weighted summation result to the bias term of the neuron to generate the input expression of the neuron, and writing it into the Verilog-A module. The code uses the generated neuron input expression as the input of the activation function to calculate the output value of the neuron; the calculated output value is used as the output of the neuron and is written into the Verilog-A module.

9. The method for converting a neural network training model into a Verilog-A language device model as claimed in claim 6, characterized in that: Finally, an end statement conforming to the Verilog-A model is output, and a device model conforming to Verilog-A is generated. Specifically, the connection relationship of the output port is determined to dynamically handle the working mode of the device under different voltage conditions and adjust the corresponding voltage value. Then, an end statement conforming to the Verilog-A model is output, and a device model conforming to Verilog-A is generated.