Server

Abstract

The invention discloses a server. In the server, the first bidirectional level translator is connected with the first debugging device, the second bidirectional level translator is connected with the connection interface, and the controller is connected with the first bidirectional level translator and the second bidirectional level translator, so that the controller judges whether the second debugging device is connected with the connection interface or not. According to the method and the device, the controller and the two bidirectional level converters are used for determining whether the processor is debugged by the first debugging device through the first bidirectional level converter or the processor is debugged by the second debugging device through the second bidirectional level converter, so that adaptation to different debugging devices is realized through the controller and the two bidirectional level converters, a plurality of analog switches do not need to be arranged, and the debugging efficiency is improved. The topology complexity of the server can be reduced, and the hardware cost is reduced.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of servers, and in particular to a server. Background Art

[0002] When a server fails, it is necessary to find the cause of the failure and perform maintenance on the server in a timely manner to restore the normal operation of the server. Currently, the commonly used method is to manually use debugging tools to detect and eliminate the faults of the server's processor.

[0003] Because the debugging levels of the debugging tool and the server's processor are different, the debugging tool needs to implement level conversion during the transmission from the debugging tool to the processor, and level conversion during the transmission from the processor to the debugging tool. Therefore, when setting up debugging for the processor inside the server, it is usually necessary to set up multiple analog switches, and then control the analog switches to conduct to enable a certain level conversion chip to implement the corresponding level conversion process to adapt to the debugging of the processor by different debugging tools. However, the topological relationship inside the server is complex and requires many devices, which will bring difficulties to the circuit layout and routing inside the server. Summary of the invention

[0004] The server provided in the embodiment of the present application can reduce the complexity of server layout and reduce hardware costs.

[0005] In a first aspect, an embodiment of the present application provides a server, the server comprising a first debugging device, a connection interface, a first bidirectional level converter, a second bidirectional level converter, a controller and a processor, wherein the first bidirectional level converter is connected between the processor and the first debugging device, the second bidirectional level converter is connected between the connection interface and the processor, and the first bidirectional level converter and the second bidirectional level converter are also connected to the controller respectively, wherein:

[0006] The controller is used to control the second bidirectional level converter to be in an operating state when the second debugging device is in a connected state with the connection interface, so as to enable the second debugging device to debug the processor through the second bidirectional level converter, or to control the first bidirectional level converter to be in an operating state when the second debugging device is in a disconnected state with the connection interface, so as to enable the first debugging device to debug the processor through the first bidirectional level converter.

[0007] In the above-mentioned server, a first bidirectional level converter is provided to connect to the first debugging device, and a second bidirectional level converter is connected to the connection interface. The controller is respectively connected to the first bidirectional level converter and the second bidirectional level converter, so that the controller decides whether to implement debugging of the processor by the first debugging device through the first bidirectional level converter or to implement debugging of the processor by the second debugging device through the second bidirectional level converter according to whether the second debugging device is connected to the connection interface. The embodiment of the present application realizes adaptation to different debugging devices through the controller and the two bidirectional level converters. The controller controls the current state of the target bidirectional level converter that needs to perform level conversion work, so as to realize the selection of the two debugging devices. In the embodiment of the present application, the working state of the bidirectional level converter refers to the conduction of the debugging line between the corresponding debugging device and the processor, and the non-working state of the bidirectional level converter refers to the disconnection of the debugging line between the corresponding debugging device and the processor, so that there is no need to set up multiple analog switches, which can reduce the complexity of the server and reduce the hardware cost.

[0008] In some embodiments, the processor includes a first processor and a second processor, wherein: an input end of the first processor is connected to the first bidirectional level converter and the second bidirectional level converter, an output end of the first processor is connected to an input end of the second processor, and an output end of the second processor is respectively connected to the first bidirectional level converter and the second bidirectional level converter, so that after the target debugging device debugs the first processor through the target bidirectional level converter, the target debugging device continues to debug the second processor, wherein the target bidirectional level converter is a bidirectional level converter in a working state between the first bidirectional level converter and the second bidirectional level converter, and the target debugging device is a debugging device connected to the target bidirectional level converter.

[0009] It can be understood that, in the scenario where the processor includes a first processor and a second processor connected in series, the embodiment of the present application connects the target bidirectional level converter, the first processor and the second processor in series in sequence to form a debugging loop, so that when the first processor completes its own debugging process, it can directly send the debugging results and debugging signals to the second processor, without the need for the target debugging device to send debugging signals to the second processor separately, thereby simplifying the debugging process.

[0010] In some embodiments, the first processor and the second processor are connected via a first switch element, the second processor is also connected to an enable end of the first switch element, the input end of the first switch element is connected to the first processor, the first output end of the first switch element is connected to the second processor, and the second output end of the first switch element is respectively connected to the first bidirectional level converter and the second bidirectional level converter, so as to control the first switch element to turn on the path between the first processor and the second processor, or to turn on the path between the first processor and the first bidirectional level converter and the second bidirectional level converter according to the target state of the second processor, and the target state includes a normal debugging state or an abnormal debugging state.

[0011] It can be understood that by connecting the first switching element between the first processor and the second processor, when the second processor cannot perform debugging work normally, the path between the first processor and the first bidirectional level converter and the second bidirectional level converter can be turned on, so that the first processor can output the debugging results directly to the first bidirectional level converter and the second bidirectional level converter without passing through the second processor, thereby avoiding the debugging process being interrupted due to the inability of the second processor to debug normally.

[0012] In some embodiments, the debugging signal sent by the target debugging device to the processor includes a target identifier indicating the processor to be debugged, the second processor includes a third processor and a fourth processor connected in series, and the first processor and the third processor are connected via a second switch element, wherein: an input end of the second switch element is connected to the first processor, a first output end of the second switch element is connected to the third processor, a second output end of the second switch element is connected to the fourth processor, and an enable end of the second switch element is connected to the first processor, so that the first processor controls the second switch element to turn on the path between the first processor and the third processor, or turns on the path between the first processor and the fourth processor, according to the target identifier.

[0013] It can be understood that by setting the second switch element between the first processor and the third processor, the first processor can control the second switch element to turn on the path corresponding to the third processor or the path corresponding to the fourth processor according to the processor to be debugged indicated by the target identifier in the debug signal, so as to transmit the debug signal sent by the target debugging device to the third processor or the fourth processor, thereby realizing the fixed-point transmission of the debug signal and improving the debugging efficiency.

[0014] In some embodiments, the third processor and the fourth processor are further connected via a third switch element, wherein: an input end of the third switch element is respectively connected to the third processor and the second output end of the second switch element, a first output end of the third switch element is connected to the fourth processor, a second output end of the third switch element is respectively connected to the first bidirectional level converter and the second bidirectional level converter, and an enable end of the third switch element is connected to the third processor, so that the third processor controls the third switch element to turn on the path between the third processor and the fourth processor according to the target identifier, or turns on the path between the third processor and the first bidirectional level converter and the second bidirectional level converter.

[0015] It can be understood that by setting a third switching element between the third processor and the fourth processor, when there is no need to debug the fourth processor, the path between the third processor and the first bidirectional level converter and the second bidirectional level converter can be turned on, allowing the data signal to be directly transmitted to the target debugging device through the target bidirectional level converter, thereby reducing the consumption of the fourth processor and improving debugging efficiency.

[0016] In some embodiments, the debugging signal sent by the target debugging device to the processor includes an instruction signal, and the first bidirectional level converter is also connected to the first processor and the second processor respectively, and the second bidirectional level converter is also connected to the first processor and the second processor respectively, so that when the target bidirectional level converter is in a working state, the target debugging device transmits the instruction signal to the first processor and the second processor through the target bidirectional level converter, and the instruction signal is used for debugging parameters when the first processor and the second processor perform debugging, and the debugging parameters include at least one of a debugging clock and a debugging mode.

[0017] It can be understood that by setting a bidirectional level converter connected to the first processor and the second processor respectively, and a second bidirectional level converter connected to the first processor and the second processor respectively, the transmission of instruction signals during the debugging process can be realized, ensuring that each processor can perform debugging according to the corresponding debugging parameters, thereby improving the stability of each processor in executing the debugging process.

[0018] In some embodiments, the processor includes a first processor and a second processor, the input end of the first processor is respectively connected to the first bidirectional level converter and the second bidirectional level converter, the output end of the first processor is respectively connected to the first bidirectional level converter and the second bidirectional level converter, the input end of the second processor is respectively connected to the first bidirectional level converter and the second bidirectional level converter, and the output end of the second processor is respectively connected to the first bidirectional level converter and the second bidirectional level converter, so as to respectively implement the debugging of the first processor and the second processor by the target debugging device through the target bidirectional level converter, wherein the target bidirectional level converter is the bidirectional level converter in a working state between the first bidirectional level converter and the second bidirectional level converter, and the target debugging device is a debugging device connected to the target bidirectional level converter.

[0019] It can be understood that, in the scenario where the processor includes a first processor and a second processor connected in parallel, the embodiment of the present application connects the target bidirectional level converter to the first processor and the second processor respectively to form different debugging loops, so that the first processor and the second processor can independently execute their own debugging processes. When either the first processor or the second processor cannot perform the debugging work normally, the other can still perform the debugging work normally, thereby ensuring the stability of the debugging work of both parties.

[0020] In some embodiments, the controller controls the first bidirectional level converter to be in a working state, including:

[0021] The controller sends an enable signal to the first bidirectional level converter to control the first bidirectional level converter to be in the working state.

[0022] It is understandable that when the controller needs to control the first bidirectional level converter to perform the level conversion process between the first debugging device and the processor, the controller directly sends an enable signal to the first bidirectional level converter, which can simplify the communication process between the controller and the first bidirectional level converter.

[0023] In some embodiments, the controller controls the second bidirectional level converter to be in a working state when the second debugging device is in a connected state with the connection interface, including:

[0024] When the controller obtains the presence signal of the second debugging device through the connection interface, it is determined that the second debugging device and the connection interface are in the connection state, and the second bidirectional level converter is controlled to be in the working state.

[0025] It is understandable that when the controller obtains the presence signal of the second debugging device, it is determined that the second debugging device is in a connected state with the connection interface, which can simplify the detection process of the controller for the second debugging device.

[0026] In some embodiments, the number of the second debugging devices and the connection interfaces is two or more, the number of the second bidirectional level converters is two or more, the second bidirectional level converters correspond to the connection interfaces one by one, and the controller is further used for:

[0027] In the case that there is a one-to-one connection between the second debugging device and the connection interface, a target debugging device with a priority higher than a threshold is determined from two or more second debugging devices according to a preset priority, and a second bidirectional level converter connected to the target debugging device is controlled to be in an operating state.

[0028] It is understandable that, in the case where there are two or more second debugging devices, by presetting the priorities of the multiple second debugging devices, one of the multiple second debugging devices can be quickly determined as the target debugging device, thereby saving debugging time.

[0029] In some embodiments, the number of the second debugging devices is two or more, and the controller is further configured to:

[0030] In a case where there are two or more second debugging devices connected to the two or more connection interfaces in a one-to-one correspondence, determining a target debugging device from the two or more second debugging devices according to the acquired historical debugging results, the target bidirectional level converter being a bidirectional level converter connected to the target debugging device;

[0031] The historical debugging results include debugging results corresponding to some debugging devices among the two or more second debugging devices, and the target debugging device is a debugging device other than the some debugging devices among the two or more second debugging devices.

[0032] It is understandable that, when there are two or more second debugging devices, one of the two or more debugging devices is determined as the target debugging device according to the acquired historical debugging results, so that a suitable target debugging device can be quickly determined, thereby improving debugging efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present application and are used together with the specification to illustrate the technical solution of the present application.

[0034] Figure 1One of the structural diagrams of the server provided in the embodiment of the present application;

[0035] Figure 2 One of the structural schematic diagrams of the bidirectional level converter provided in the embodiment of the present application;

[0036] Figure 3 The second structural diagram of the bidirectional level converter provided in the embodiment of the present application;

[0037] Figure 4 The second structural diagram of the server provided in the embodiment of the present application;

[0038] Figure 5 A schematic diagram of the structure of a transmission branch between a target bidirectional level converter and a processor provided in an embodiment of the present application;

[0039] Figure 6 A schematic diagram of the structure of multiple processors in parallel provided in an embodiment of the present application;

[0040] Figure 7 A schematic diagram of the structure of multiple processors in series relationship provided in an embodiment of the present application;

[0041] Figure 8 One of the structural diagrams of the processor provided in the embodiment of the present application;

[0042] Fig. 9 One of the structural schematic diagrams of the first switch element provided in an embodiment of the present application;

[0043] Fig.10 A second structural schematic diagram of the first switch element provided in an embodiment of the present application;

[0044] Fig.11 The second structural diagram of the processor provided in the embodiment of the present application;

[0045] Fig.12 The third structural diagram of the processor provided in the embodiment of the present application;

[0046] Fig.13 A fourth structural diagram of a processor provided in an embodiment of the present application;

[0047] Fig.14 A schematic diagram of the implementation structure of the server provided in the embodiment of the present application;

[0048] Fig.15 A schematic diagram of the control flow of the controller provided in an embodiment of the present application. DETAILED DESCRIPTION

[0049] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the specific technical solution of the present application will be further described in detail below in conjunction with the drawings in the embodiments of the present application. The following embodiments are used to illustrate the present application, but are not used to limit the scope of the present application.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0051] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present application are used to distinguish similar or different objects, and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present application described here can be implemented in an order other than that illustrated or described here.

[0052] An embodiment of the present application provides a server, wherein a first bidirectional level converter is provided to be connected to a first debugging device, a second bidirectional level converter is connected to a connection interface, and a controller is respectively connected to the first bidirectional level converter and the second bidirectional level converter, so that the controller decides whether to implement debugging of a processor by the first debugging device through the first bidirectional level converter or to implement debugging of the processor by the second debugging device through the second bidirectional level converter according to whether the second debugging device is connected to the connection interface. The embodiment of the present application implements adaptation to different debugging devices through the controller and the two bidirectional level converters. The controller controls the current state of the target bidirectional level converter that needs to perform level conversion work, so as to realize the selection of the two debugging devices. In the embodiment of the present application, the working state of the bidirectional level converter refers to the conduction of the debugging line between the corresponding debugging device and the processor, and the non-working state of the bidirectional level converter refers to the disconnection of the debugging line between the corresponding debugging device and the processor, so that there is no need to set up multiple analog switches, which can reduce the complexity of the server and reduce the hardware cost.

[0053] Figure 1 A schematic diagram of the structure of a server provided in an embodiment of the present application. Figure 1 As shown, the server may include a first debugging device 14, a connection interface 16, a first bidirectional level converter 11, a second bidirectional level converter 15, a controller 13 and a processor 12, wherein the first bidirectional level converter 11 is connected between the processor 12 and the first debugging device 14, the second bidirectional level converter 15 is connected between the connection interface and the processor 12, and the first bidirectional level converter 11 and the second bidirectional level converter 15 are also connected to the controller 13 respectively, wherein:

[0054] The controller 13 is used to control the second bidirectional level converter 15 to be in a working state when the second debugging device is in a connected state with the connection interface 16, so that the second debugging device can debug the processor 12 through the second bidirectional level converter 15. Alternatively, the controller 13 is used to control the first bidirectional level converter 11 to be in a working state when the second debugging device is in a non-connected state with the connection interface 16, so that the first debugging device 14 can debug the processor 12 through the first bidirectional level converter 11.

[0055] For ease of description, when the first bidirectional level converter is in working state, the first bidirectional level converter is a target bidirectional level converter, and the first debugging device connected to the first bidirectional level converter is a target debugging device. When the second bidirectional level converter is in working state, the second bidirectional level converter is a target bidirectional level converter, and the second debugging device connected to the second bidirectional level converter is a target debugging device. When the target bidirectional level converter is the first bidirectional level converter, the first debugging device debugs the processor. During the debugging process, the first bidirectional level converter 11 can perform a first level conversion process on the first debugging signal after receiving the first debugging signal sent by the first debugging device, so as to output a second debugging signal, and the level of the second debugging signal is adapted to the working level of the processor 12. After receiving the second debugging signal, the processor 12 performs a debugging step according to the second debugging signal, generates and outputs a first output signal, and the first output signal includes a debugging result obtained by performing the debugging step. After receiving the first output signal, the first bidirectional level converter 11 performs a second level conversion process on the first output signal to output a second output signal, and the level of the second output signal is adapted to the working level of the first debugging device, so that the first debugging device obtains the debugging result of the processor 12 according to the second output signal.

[0056] When the target bidirectional level converter is the second bidirectional level converter, the second debugging device debugs the processor. The debugging process is similar to the debugging process of the processor by the first debugging device, and will not be repeated. Usually the debugging signal and the debugging result exist in the form of binary data, so the bidirectional level converter can provide hardware support for implementing different level conversion processes through switching elements. It can be understood that the structures of the first bidirectional level converter and the second bidirectional level converter can be the same or different. The specific structure of the first bidirectional level converter or the second bidirectional level converter is described below.

[0057] In some embodiments, Figure 2As shown, the first bidirectional level converter 11 or the second bidirectional level converter 15 may include a first power supply 101, a second power supply 102, a switch element 103, a first port, and a second port. The first port is used to connect to a debugging device, and the second port is used to connect to a processor 12. The switch element 103 is connected to the first power supply 101, the second power supply 102, the first port, and the second port, respectively. The first power supply 101 is also connected to the first port, and the second power supply 102 is also connected to the second port. When the first port is connected to the first debugging device 14 or the second debugging device, and the second port is connected to the processor 12, the voltage of the first power supply 101 matches the debugging level of the processor 12, and the voltage of the second power supply 102 matches the debugging level of the first debugging device 14 or the second debugging device. The switch element 103 is used to control the first connection end and the second connection end to be in an on state or a off state.

[0058] During the debugging process, if the first port is connected to the debugging device and the second port is connected to the processor 12, when the debugging signal of the first debugging device 14 or the second debugging device is input into the target bidirectional level converter, the level at the first port is high, the switch element 103 disconnects the connection between the first port and the second port, and the second port is connected to the second power supply 102, so the level value of the second power supply 102 is output, thereby realizing the first level conversion processing; similarly, when the debugging result of the processor is input into the target bidirectional level converter, the level at the second port is high, the switch element 103 disconnects the connection between the first port and the second port, and the first port is connected to the first power supply 101, so the level value of the first power supply 101 is output, thereby realizing the second level conversion processing; when the first port or the second port does not receive the input signal, the switch element 103 is in the on state, and the first port or the second port presents the on-state voltage drop corresponding to the switch element 103, which is regarded as a low level, that is, no signal is output.

[0059] The switch element 103 may be a field effect transistor, such as Figure 2 As shown, the gate of the field effect transistor is connected to the first power supply 101, the drain of the field effect transistor is connected to the first port, and the source of the field effect transistor is connected to the second power supply 102 and the second port respectively.

[0060] In some embodiments, Figure 3As shown, the switch element 103 may include a first switch tube 1031 and a second switch tube 1032, wherein the collector of the first switch tube 1031 is connected to the first port, the emitter of the first switch tube 1031 is connected to the second port, the collector of the second switch tube 1032 is connected to the second port, and the emitter of the second switch tube 1032 is connected to the first port. The base of the first switch tube 1031 is respectively connected to one end of the first resistor 1033 and one end of the second resistor 1034, the other end of the first resistor 1033 is connected to the third power supply 1037, and the other end of the second resistor 1034 is connected to the ground; the base of the second switch tube 1032 is respectively connected to one end of the third resistor 1035 and one end of the fourth resistor 1036, the other end of the third resistor 1035 is connected to the fourth power supply 1038, and the other end of the fourth resistor 1036 is connected to the ground.

[0061] Therefore, the voltage output by the third power supply 1037 can generate a corresponding first base voltage after being divided by the first resistor 1033 and the second resistor 1034, so that the conduction control of the first switch tube 1031 is achieved by adjusting the voltage of the third power supply 1037, the resistance value of the first resistor 1033 and the resistance value of the second resistor 1034. Similarly, the voltage output by the fourth power supply 1038 can generate a corresponding second base voltage after being divided by the third resistor 1035 and the fourth resistor 1036, so that the conduction control of the second switch tube 1032 is achieved by adjusting the voltage of the fourth power supply 1038, the resistance value of the third resistor 1035 and the resistance value of the fourth resistor 1036.

[0062] In the level conversion process, taking the first power supply as 1.8V, the second power supply 102, the third power supply 1037 and the fourth power supply 1038 as 3.3V, and the first switch tube 1031 and the second switch tube 1032 as NPN transistors, the voltage at the first port is V1, the voltage at the second port is V2, the voltage at the base of the first switch tube 1031 is the first reference voltage V3, and the voltage at the base of the second switch tube 1032 is the second reference voltage V4. Wherein, assuming that the resistance value R1 of the first resistor 1033 is 10kΩ, the resistance value R2 of the second resistor 1034 is 20kΩ, the resistance value R3 of the third resistor 1035 is 18kΩ, and the resistance value R4 of the fourth resistor 1036 is 15kΩ, then the calculation formula of the first reference voltage V3 is:

[0063] V3=3.3V*R2 / (R1+R2)=3.3*20K / (10K+20K)=2.2V;

[0064] The calculation formula of the second reference voltage V4 is:

[0065] V4=3.3V*R4 / (R3+R4)=3.3*15K / (18K+15K)=1.5V.

[0066] When the signal is input from the first port, the following situations are included:

[0067] 1. When the first port is in the idle state, both the first port and the second port are at high level, that is, V1 = 1.8V and V2 = 3.3V;

[0068] 2. When V1 changes from 1.8V to 0V, V1 = 0V (low level), V3 > V1, so the second switching transistor 1032 conducts, and the voltage of the second port is pulled down, that is, V2 = 0 (low level);

[0069] 3. When V1 changes from 0V to 1.8V, V1 = 1.8V (high level), V3 < V1, so the second switching transistor 1032 cuts off, and the voltage of the second port returns to high level, that is, V2 = 3.3V (high level);

[0070] Therefore, the conversion from 1.8V signal to 3.3V signal is realized.

[0071] Among them, because the second reference voltage V4 is 1.5V, and the conduction voltage of the triode is about 0.6V, so when the low level of the voltage V1 at the first port fluctuates below 0.9V (excluding 0.9V), V4 - V1 > 0.6V can be achieved, so the second switching transistor 1032 can conduct, and the second port can also output low level normally. Similarly, when the high level of the voltage V1 at the first port fluctuates above 0.9V, the second switching transistor 1032 can cut off, and the second port can also output high level normally.

[0072] When the signal is input from the second port, the following situations are included:

[0073] 1. When the second port is in the idle state, both the first port and the second port are at high level, that is, V1 = 1.8V and V2 = 3.3V;

[0074] 2. When V2 changes from 1.8V to 0V, V2 = 0V (low level), V3 > V2, so the first switching transistor 1031 conducts, and the voltage of the first port is pulled down, that is, V1 = 0 (low level);

[0075] 3. When V2 changes from 0V to 1.8V, V2 = 1.8V (high level), V3 < V2, so the first switching transistor 1031 cuts off, and the voltage of the first port returns to high level, that is, V1 = 3.3V (high level);

[0076] Therefore, the conversion from 3.3V signal to 1.8V signal is realized.

[0077] Among them, because the first reference voltage V3 is 2.2V, and the conduction voltage of the transistor is about 0.6V, the low level of the voltage V2 at the second port fluctuates below 1.6V (excluding 1.6V), and V3-V1>0.6V can be achieved, so the first switch tube 1031 can be turned on, and the first port can also output a low level normally. Similarly, when the high level of the voltage V2 at the second port fluctuates above 1.6V, the first switch tube 1031 can be turned off, and the first port can also output a high level normally.

[0078] The above scheme sets different conduction threshold values ​​for the level conversion direction from the target debugging device to the processor 12 and the level conversion direction from the processor 12 to the target debugging device, thereby effectively filtering out the influence of voltage fluctuation on the switch element 103, and effectively avoiding the phenomenon of the switch element 103 being mistakenly turned on or off when the signal of the first port or the second port has voltage fluctuation. In some embodiments, the above processor 12 may include a central processing unit (CPU), an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU). This embodiment is described by taking the processor as a central processing unit as an example.

[0079] In some embodiments, the connection interface 16 is used to realize the connection between the second debugging device and the server, and the connection interface 16 can be a serial wire debug (SWD), a joint test action group (JTAG), a remote debug interface (Remote Debug Interface), etc. Different connection interfaces 16 have different data transmission protocols. For example, for a standard JTAG interface, at least 4 pins are included: a mode selection pin TMS, a clock input pin TCK, a test data input pin TDI, and a test data output pin TDO. The server and the second debugging device realize the processor debugging process based on the communication protocol of the JTAG interface by connecting the above 4 pins.

[0080] In some embodiments, the first debugging device 14 or the second debugging device may be any debugging tool for implementing the debugging process of the processor, wherein the first debugging device 14 is a debugging device fixedly set in the server, such as a baseboard management controller (Baseboard Management Controller, BMC); the second debugging device is a debugging device that needs to be connected to the server through the connection interface 16 to perform debugging work, such as a common debugging tool such as eXpress DataPath (XDP) or a load balancing program (software load balance, SLB). BMC mainly detects the hardware status of the processor, and the hardware status includes hardware status information such as temperature, voltage, fan speed, and basic input and output system (Basic Input Output System, BIOS); XDP mainly monitors network data, such as flow control functions such as flow shaping and load balancing, and implements network security policies, such as firewall rules, intrusion detection, etc. The specific debugging tool to be used is set by technical personnel in this field according to actual conditions. For example, when the second debugging device is not connected to the server, the processor 12 is debugged by the first debugging device 14. When the second debugging device is connected to the server, the processor 12 is debugged by the second debugging device. The embodiments of the present application do not limit this.

[0081] In some embodiments, the controller 13 determines whether the second debugging device is in a connected state or a disconnected state with the connection interface 16 by detecting whether a presence signal of the second debugging device is obtained.

[0082] That is, when the controller 13 obtains the in-position signal of the second debugging device through the connection interface 16, it determines that the second debugging device is in a connection state with the connection interface 16, and controls the second bidirectional level converter 15 to be in a working state;

[0083] When the controller 13 fails to obtain the presence signal of the second debugging device through the connection interface 16 , it determines that the second debugging device is in a disconnected state with the connection interface 16 , and controls the first bidirectional level converter 11 to be in an operating state.

[0084] Among them, the above-mentioned in-place signal can be triggered and generated by the controller 13 when the device information of the second debugging device is detected, or it can be automatically sent to the controller 13 by the second debugging device after establishing a communication link with the server. The specific setting can be made by technical personnel in this field according to actual conditions, and the embodiments of the present application are not limited.

[0085] It is understandable that the controller 13 determines the connection status between the second debugging device and the connection interface by detecting whether the presence signal sent by the second debugging device is obtained, which can simplify the detection process of the controller 13 for the second debugging device.

[0086] In some embodiments, the controller 13 controls the target bidirectional level converter to be in working state, which may include:

[0087] The controller 13 sends an enable signal to the target bidirectional level converter to control the target bidirectional level converter to be in a working state.

[0088] It should be understood that when the controller 13 is connected to the first bidirectional level converter 11 and the second bidirectional level converter 15, the controller 13 is connected to the control end of the first bidirectional level converter 11 and the control end of the second bidirectional level converter 15, so that when the controller 13 needs to control the target bidirectional level converter in the first bidirectional level converter 11 or the second bidirectional level converter 15 to be in a working state, the controller 13 can send an enable signal to the control end of the target bidirectional level converter to put the target bidirectional level converter in a working state, thereby realizing the control operation of putting the target bidirectional level converter in a working state.

[0089] It should be noted that, while the controller 13 sends the enable signal to the target bidirectional level converter, it may also send a control signal to other bidirectional level converters to control the other bidirectional level converters to be in a non-operating state.

[0090] Exemplarily, when the controller 13 obtains the presence signal of the second debugging device, the controller 13 sends EN_A to the second bidirectional level converter to control the second bidirectional level converter to be in a working state, and sends EN_B to the first bidirectional level converter 11 to control the first bidirectional level converter 11 to be in a non-working state; if the controller 13 does not obtain the presence signal of the second debugging device, the controller 13 sends EN_B to the second bidirectional level converter 15 to control the second bidirectional level converter 15 to be in a non-working state, and sends EN_A to the first bidirectional level converter 11 to control the first bidirectional level converter 11 to be in a working state.

[0091] It can be understood that when the controller 13 needs to control the first bidirectional level converter 11 to perform the level conversion process between the first debugging device 14 and the processor 12, the communication process between the controller 13 and the first bidirectional level converter 11 can be simplified by directly sending an enable signal to the first bidirectional level converter 11 through the controller 13.

[0092] In some embodiments, Figure 4As shown, the number of the above-mentioned second debugging devices, connection interfaces 16 and second bidirectional level converters 15 may include two or more, each second debugging device is connected to a second bidirectional level converter 15 respectively, and the controller 13 can first determine the target debugging device from the two or more second debugging devices, and then determine the target bidirectional level converter according to the target debugging device.

[0093] It should be understood that each second debugging device is respectively connected to a second bidirectional level converter 15, and two or more second debugging devices may be connected to two or more second bidirectional level converters 15 in a one-to-one correspondence, or two or more second debugging devices may be connected to the same second bidirectional level converter 15, or some of the second debugging devices may be connected to one of the second bidirectional level converters 15, and other second debugging devices may be connected to another second bidirectional level converter 15. The specific configuration is made by those skilled in the art according to actual conditions, and is not limited in the embodiments of the present application. Figure 5 This is only one example and should not be considered as a limitation to the embodiments of the present application.

[0094] When there are two or more second debugging devices connected to the server, in order to avoid conflicts between debugging signals sent by different second debugging devices when multiple second debugging devices work at the same time, one of the second debugging devices is set to perform the debugging process on the processor 12 at the same time, that is, at this time, one of the two or more second debugging devices needs to be determined as the target debugging device. The method of determining the target debugging device may include one of the following or a combination:

[0095] Method 1:

[0096] The controller 13 determines a target debugging device having a priority higher than a threshold from two or more second debugging devices according to a preset priority, and the target bidirectional level controller is a bidirectional level converter connected to the target debugging device.

[0097] It should be understood that different second debugging devices have different debugging contents when debugging the processor, so those skilled in the art can set preset priorities for two or more second debugging devices according to debugging needs to control the second debugging device with a higher priority to perform the debugging process on the processor 12. In some embodiments, after completing the debugging of the second debugging device with a higher priority, those skilled in the art can disconnect the connection between the second debugging device and the server, so that the controller 13 can continue to perform the debugging process on other second debugging devices according to the preset priority.

[0098] Exemplarily, the two or more second debugging devices include debugging device A and debugging device B, and the two or more second bidirectional level controllers include bidirectional level controller A and bidirectional level controller B. After debugging device A is connected to bidirectional level controller A, and debugging device B is connected to bidirectional level controller B, the controller 13 can determine a second debugging device with a higher priority from debugging device A and debugging device B. Taking debugging device A as an example, after determining that debugging device A is the target debugging device, the bidirectional level controller A connected to debugging device A is further determined as the target bidirectional level controller. The controller 13 controls the bidirectional level controller A to be in a working state, so that the bidirectional level controller A performs a first level conversion processing on the first debugging signal output by debugging device A, and performs a second level conversion processing on the first output signal output by processor 12.

[0099] It is understandable that, in the case where there are two or more second debugging devices, by presetting the priorities of the multiple second debugging devices, one of the multiple second debugging devices can be quickly determined as the target debugging device, thereby saving debugging time.

[0100] Method 2:

[0101] The controller 13 determines a target debugging device from two or more second debugging devices according to the acquired historical debugging results, and the target bidirectional level converter is a bidirectional level converter connected to the target debugging device;

[0102] The historical debugging results include debugging results corresponding to some of the second debugging devices among the two or more second debugging devices, and the target debugging device is the second debugging device other than some of the second debugging devices among the two or more second debugging devices.

[0103] It should be understood that different second debugging devices debug different contents of the processor, and it is unlikely that the same debugging content is debugged in two adjacent debugging processes. Therefore, after each debugging process, the second debugging device that obtains the debugging result can be recorded to form a historical debugging result. Before determining the target debugging device in the current debugging process, a second debugging device that has not appeared in the historical debugging results is determined, and the second debugging device that has not appeared is used as the target debugging device, so as to control the target debugging device to execute the debugging process.

[0104] The controller 13 may clear some debugging results with earlier recording time in the historical debugging results at regular intervals, so as to automatically and periodically update the historical debugging results.

[0105] Exemplarily, the two or more second debugging devices include debugging device A and debugging device B, and the two or more second bidirectional level converters include bidirectional leveler A and bidirectional leveler B. After debugging device A is connected to bidirectional leveler A, and debugging device B is connected to bidirectional leveler B, the controller 13 can determine a second debugging device that has not appeared in the historical debugging results from debugging device A and debugging device B. Taking debugging device A as an example, after determining that debugging device A is the target debugging device, the bidirectional leveler A connected to debugging device A is further determined as the target bidirectional leveler. The controller 13 controls the bidirectional leveler A to be in a working state, so that the bidirectional leveler A performs a first level conversion processing on the first debugging signal output by debugging device A, and performs a second level conversion processing on the first output signal output by processor 12.

[0106] It is understandable that, when there are two or more second debugging devices, one of the two or more debugging devices is determined as the target debugging device according to the acquired historical debugging results, so that a suitable target debugging device can be quickly determined, thereby improving debugging efficiency.

[0107] Among them, the debugging signal includes a data signal and an instruction signal. After receiving the data signal and the instruction signal, the processor will first initialize the debugging environment required for executing the debugging process according to the debugging parameters in the instruction signal, and then execute the corresponding debugging steps in the debugging environment according to the data signal. The specific content of the execution steps will vary according to the different data signals. The debugging parameters include at least one or more of the debugging clock and the debugging mode.

[0108] Since the command signal only needs to be transmitted from the target bidirectional level converter to the processor and does not require feedback, and after the data signal is transmitted from the target bidirectional level converter to the processor, the processor needs to feedback the corresponding debugging result to the target bidirectional level converter, so for the data signal, it is necessary to set a transmission loop that transmits from the target bidirectional level converter to the processor and then to the target bidirectional level converter.

[0109] At this time, the target bidirectional level converter can send the instruction signal to the processor through the first transmission branch, and send the data signal to the processor through the second transmission branch. The processor then transmits the debugging result corresponding to the data signal to the target bidirectional level converter through the third transmission branch. The second transmission branch and the third transmission branch constitute a data transmission loop between the processor and the target bidirectional level converter, wherein the instruction signal may include a clock signal TCK and a debugging mode signal TMS, and the data signal may include an input signal TDI.

[0110] For example, Figure 5As shown, taking the example of transmitting the instruction signal in the second debug signal through the first transmission branch, transmitting the data signal in the second debug signal through the second transmission branch, and transmitting the debug result through the third transmission branch between the target bidirectional level converter and the processor 12, the first transmission branch includes a first transmission line for transmitting the clock signal TCK and a second transmission line for transmitting the debug mode signal TMS, the second transmission branch includes a third transmission line for transmitting the input signal TDI, the third transmission branch includes a fourth transmission line for transmitting the output signal TDO, and the third transmission line and the fourth transmission line constitute a data transmission loop between the processor and the target bidirectional level converter.

[0111] During the debugging process, the target debugging device sends a first debugging signal including a clock signal TCK, a debugging mode signal TMS and an input signal TDI to the target bidirectional level converter. After performing level conversion on the first debugging signal, the target bidirectional level converter obtains a second debugging signal after level conversion, and transmits the clock signal TCK after level conversion to the processor through the first transmission line, transmits the debugging mode signal TMS after level conversion to the processor through the second transmission line, and transmits the input signal TDI after level conversion to the processor through the third transmission line. After the processor completes the debugging steps according to the clock signal TCK, the debugging mode signal TMS and the input signal TDI, it transmits the output signal TDO to the target bidirectional level converter through the fourth transmission line. The target bidirectional level converter then performs level conversion on the output signal TDO, obtains and outputs the output signal TDO after level conversion to the target debugging device, thereby completing the debugging.

[0112] Wherein, when the number of the above-mentioned processors 12 is two or more, the number of the above-mentioned first transmission line, second transmission line, third transmission line and fourth transmission line is also two or more, each processor is connected to the target bidirectional level converter through the first transmission line and the second transmission line to transmit the instruction signal, and at the same time, each processor 12 will also form a data transmission loop with the target bidirectional level converter through the third transmission line and the fourth transmission line to transmit the data signal and the debugging result, and the connection relationship between different two or more processors 12 has different forms of data transmission loops. Wherein, the two or more processors 12 can be in parallel or in series, which is specifically set by those skilled in the art according to the actual situation, and the embodiment of the present application is not limited.

[0113] For example, Figure 6As shown, taking the parallel relationship between two or more processors 12 as an example, the two or more processors 12 include a first processor 121 and a second processor 122, the input end of the first processor 121 is respectively connected to the first bidirectional level converter 11 and the second bidirectional level converter 15, the output end of the first processor 121 is respectively connected to the first bidirectional level converter 11 and the second bidirectional level converter 15, the input end of the second processor 122 is respectively connected to the first bidirectional level converter 11 and the second bidirectional level converter 15, and the output end of the second processor 122 is respectively connected to the first bidirectional level converter 11 and the second bidirectional level converter 15.

[0114] That is, in a parallel relationship, each of the two or more processors 12 will form a data transmission loop with the target bidirectional level converter, that is, there are two or more data transmission loops for respectively transmitting data signals of different processors and corresponding debugging results.

[0115] During the debugging process, the target bidirectional level converter will output the data signal after level conversion to the first processor 121 and the second processor 122 respectively. The first processor 121 executes the debugging process according to the data signal to obtain the corresponding first sub-result. The second processor 122 executes the debugging process according to the data signal to obtain the corresponding second sub-result. Then, the first processor 121 feeds back the first sub-result to the target debugging device via the target bidirectional level converter, and the second processor 122 feeds back the second sub-result to the target debugging device via the target bidirectional level converter. The target debugging device completes the debugging of the first processor 121 and the second processor 122 according to the received first sub-result and second sub-result.

[0116] It can be understood that by setting the input end of the first processor 121 and the input end of the second processor 122 to be connected to the first bidirectional level converter 11 and the second bidirectional level converter 15 respectively, the output end of the first processor 121 and the output end of the second processor 122 are connected to the first bidirectional level converter 11 and the second bidirectional level converter 15 respectively, so that the first processor and the second processor can be debugged in parallel based on the data signal, thereby shortening the total debugging time of the entire server processor and improving the debugging efficiency.

[0117] For example, Figure 7As shown, taking the example of two or more processors 12 being connected in series, the two or more processors 12 include a first processor 121 and a second processor 122, the input end of the first processor 121 is connected to the first bidirectional level converter 11 and the second bidirectional level converter 15, the output end of the first processor 121 is connected to the input end of the second processor 122, and the output end of the second processor 122 is respectively connected to the first bidirectional level converter 11 and the second bidirectional level converter 15.

[0118] That is, in a series relationship, two or more processors 12 are in the same data transmission loop, and the data transmission loop is used to transmit data signals and corresponding debugging results in the two or more processors 12 in sequence.

[0119] During the debugging process, the target bidirectional level converter transmits the data signal after level conversion to the first processor 121, so that the first processor 121 obtains the corresponding first sub-result, and then the first processor 121 transmits the first sub-result and the data signal to the second processor 122, so that the second processor 122 obtains the corresponding second sub-result according to the data signal, and then the second processor 122 transmits the data signal, the first sub-result and the second sub-result to the target bidirectional level converter, so that the target bidirectional level converter performs level conversion on the first sub-result and the second sub-result to obtain the second output result, thereby completing the debugging of the first processor 121 and the second processor 122.

[0120] It can be understood that by setting the input end of the first processor 121 to be connected to the first bidirectional level converter 11 and the second bidirectional level converter 15 respectively, the input end of the second processor 122 is connected to the output end of the first processor 121, and the output end of the second processor 122 is connected to the first bidirectional level converter 11 and the second bidirectional level converter 15 respectively, thereby, the first bidirectional level converter and the second bidirectional level converter are connected to one of the multiple processors, which simplifies the complexity of the line setting, makes the wiring scheme simpler, and the target bidirectional level converter performs two conversions during the test process, and the signal transmission delay is lower.

[0121] In some embodiments, a switch element may be further provided between two or more processors 12 connected in series in the server to control the conduction branch of the switch element, for example, Figure 8As shown, the two or more processors 12 include a first processor 121 and a second processor 122. The first processor 121 and the second processor 122 are connected via a first switch element 123. The second processor 122 is also connected to the control end of the first switch element 123. The input end of the first switch element 123 is connected to the first processor 121. The first output end of the first switch element 123 is connected to the second processor 122. The second output end of the first switch element 123 is respectively connected to the first bidirectional level converter 11 and the second bidirectional level converter 15.

[0122] During the debugging process, if the second processor 122 detects that it is not executing a task process with a large computing demand or the temperature has not exceeded the threshold, that is, it is in a normal debugging state, then the second processor 122 can send a switch control signal indicating conduction to the first switch element 123, so that the first switch element 123 conducts the connection path between the first processor 121 and the second processor 122; if the second processor 122 detects that it is executing a task process with a large computing demand or the temperature has exceeded the threshold, that is, it is in an abnormal debugging state, then the second processor 122 can send a switch control signal indicating disconnection to the first switch element 123, so that the first switch element 123 conducts the connection path between the first processor 121 and the target bidirectional level converter. The second processor 122 can check the normal debugging state or the abnormal debugging state at any time when the second processor 122 is in a working state.

[0123] It should be noted that if the processor 12 is in a debugging exception state before executing debugging, the debugging process cannot be executed normally. For example, in the debugging exception state caused by a busy state, the processor 12 is executing some task processes with high computing requirements. If the debugging process is executed at this time, it will interfere with the running task processes, and the execution efficiency of the debugging process will also be greatly affected; or in the debugging exception state caused by an overheating state, the processor will reduce the frequency or suspend all task processes to reduce heat generation. If the debugging process is executed at this time, the time for the processor to execute the debugging process will definitely be longer than the time executed in the normal debugging state, and the processor may even freeze when executing the debugging process, causing debugging interruption.

[0124] It should be understood that when the first switch element 123 turns on the path between the first processor 121 and the first bidirectional level converter 11 and the second bidirectional level converter 15, the first processor 121 will directly transmit the obtained sub-result to the target bidirectional level converter, so that the target debugging device can receive the output signal TDO including the sub-result corresponding to the first processor 121; when the first switch element 123 turns on the path between the first processor 121 and the second processor 122, the first processor 121 will first transmit the obtained first sub-result and the input signal TDI to the second processor 122, and the second processor 122 will obtain the sub-result corresponding to the second processor 122 according to the input signal, so that the second processor outputs the output signal TDO including the first sub-result and the second sub-result to the target bidirectional level converter.

[0125] In the embodiment of the present application, the second processor can determine whether to perform debugging based on its own state. When the second processor cannot perform debugging, the first switch element 123 can be controlled to turn on the path between the first processor 121 and the first bidirectional level converter 11 and the second bidirectional level converter 15, so that the target adjustment device can obtain the debugging result of the first processor, thereby improving the debugging efficiency.

[0126] It should be noted that although the above embodiment only describes the structural framework when there are two processors (i.e., the first processor 121 and the second processor 122), the structural framework when there are more than two processors is similar to the structural framework in the above embodiment and will not be repeated here.

[0127] It can be understood that by connecting the first switching element 123 between the first processor 121 and the second processor 122, when the second processor 122 is unable to perform debugging, the path between the first processor 121 and the first bidirectional level converter 11 and the second bidirectional level converter 15 can be turned on, so that the first processor 121 can output the debugging results directly to the first bidirectional level converter 11 and the second bidirectional level converter 15 without passing through the second processor 122, thereby avoiding the debugging process being interrupted due to the inability of the second processor to debug normally.

[0128] In some embodiments, the first switch element 123 may include a plurality of single-pole single-throw switches, and the number of the single-pole single-throw switches is determined according to the number of two or more processors. For example, for the first processor 121 and the second processor 122, the output end of the first processor 121 is connected to the input end of the second processor 122 via a single-pole single-throw switch, and the output end of the first processor 121 is also connected to the target bidirectional level converter via another single-pole single-throw switch. The second processor is respectively connected to the control ends of the plurality of single-pole single-throw switches, and the plurality of single-pole single-throw switches are not turned on at the same time.

[0129] For example, Fig. 9 As shown, the multiple single-pole single-throw switches include a first single-pole single-throw switch K1 and a second single-pole single-throw switch K2. When the second processor 122 controls the first single-pole single-throw switch K1 to disconnect the connection between the first processor 121 and the second processor 122, the second processor 122 also controls the second single-pole single-throw switch K2 to be turned on, so as to output a first output signal to the target bidirectional level converter, and the first output signal includes the debugging result of the first processor 121; when the second processor 122 controls the first single-pole single-throw switch K1 to connect the connection between the first processor 121 and the second processor 122, the second processor 122 also controls the second single-pole single-throw switch K2 to be turned off, and the first processor 121 outputs the debugging result of the first processor 121 and the second debugging signal to the second processor 122, and then the second processor 122 outputs the first output signal to the target bidirectional level converter, and the first output signal includes the debugging result of the first processor 121 and the debugging result of the second processor 122.

[0130] In some other embodiments, the first switch element 123 includes a switch controller and a single-pole multi-throw switch, and the number of output terminals of the single-pole multi-throw switch is determined according to the number of two or more processors, for example, Fig.10 As shown, the switch controller is connected to the second processor 122, the input end of the single-pole multi-throw switch is connected to the first processor 121, the first output end of the single-pole multi-throw switch is connected to the second processor 122, and the second output end of the single-pole multi-throw switch is connected to the first bidirectional level converter and the second bidirectional level converter 15 respectively, wherein:

[0131] The second processor 122 is used to output a switch control signal to the switch controller according to a current target state, where the current state includes a normal debugging state or an abnormal debugging state;

[0132] The switch controller is used to receive and control the single-pole multi-throw switch to conduct a first path between the first processor 121 and the second processor 122, or to conduct a second path between the first processor 121 and a target bidirectional level converter according to a switch control signal.

[0133] During the debugging process, the second processor 122 can send a corresponding switch control signal to the switch controller according to whether it can currently execute the debugging process normally. That is, when the second processor 122 can execute the debugging process normally, the switch control signal instructing to turn on the first path is sent to the switch controller, so that the switch controller controls the single-pole multi-throw switch to turn on the first path, and the debugging result received by the target debugging device includes the sub-result corresponding to the first processor 121 and the sub-result corresponding to the second processor 122; when the second processor 122 cannot execute the debugging process normally, the switch control signal instructing to turn on the second path is sent to the switch controller, so that the switch controller controls the single-pole multi-throw switch to turn on the second path, and the debugging result received by the target debugging device includes the sub-result corresponding to the first processor 121.

[0134] The above embodiment only describes the framework in the case where there are two processors, and the framework is similar when there are more than two processors.

[0135] For example, Fig.11 As shown, in the case where the two or more processors include a first processor, a second processor and a third processor connected in series, the first processor and the second processor are connected through a first switch SW1, and the second processor and the third processor are connected through a second switch SW2. The structure of the first switch SW1 and the structure of the second switch SW2 are the same as the first switch element 123. The first bidirectional level converter 11 and the second bidirectional level converter 15 are respectively connected to the first processor, the second processor and the third processor through a first transmission line and a second transmission line, respectively, so as to transmit the clock signal TCK and the debug mode signal TMS to the first processor, the second processor and the third processor, respectively. The first bidirectional level converter 11 and the second bidirectional level converter 15 are connected in series with the first processor, the second processor and the third processor through a third transmission line and a fourth transmission line, so as to transmit the input signal TDI to the first processor, and then transmit the input signal TDI to the second processor and the third processor in sequence through the series path between the first processor, the first switch SW1, the second processor, the second switch SW2 and the third processor.

[0136] Among them, when the second processor can execute the debugging process normally, a switch control signal indicating that it is currently in a normal debugging state is sent to the first switch SW1, so that the first switch SW1 turns on the first path, and the sub-result and debugging signal corresponding to the first processor can be transmitted to the third processor; conversely, when the second processor cannot execute the debugging process normally, a switch control signal indicating that it is currently in an abnormal debugging state is sent to the switch controller, so that the switch controller controls the first switch SW1 to turn on the second path, and the sub-result corresponding to the first processor will be directly transmitted to the target bidirectional level converter.

[0137] When the third processor can execute the debugging process, a switch control signal indicating that it is currently in a normal debugging state is sent to the second switch SW2, so that the second switch SW2 turns on the first path, and the sub-result corresponding to the first processor, the sub-result corresponding to the second processor, and the input signal TDI can be transmitted to the third processor; conversely, when the third processor cannot execute the debugging process normally, a switch control signal indicating that it is currently in an abnormal debugging state is sent to the second switch SW2, so that the second switch SW2 turns on the second path, and the sub-result corresponding to the first processor and the sub-result corresponding to the second processor are directly transmitted to the target bidirectional level converter.

[0138] In some embodiments, a switch element may be provided between two or more processors to control the transmission path to the target processor, for example, Fig.12 As shown, the two or more processors include a first processor 121, a third processor 1221 and a fourth processor 1222, the third processor 1221 is connected between the first processor 121 and the fourth processor 1222, the input end of the second switch element 124 is connected to the first processor 121, the first output end of the second switch element 124 is connected to the third processor 1221, the second output end of the second switch element 124 is respectively connected to the fourth processor 1222, and the enable end of the second switch element 124 is connected to the first processor 121, so as to open the path between the first processor 121 and the third processor 1221 according to the control of the first processor 121, or to open the path between the first processor 121 and the fourth processor 1222.

[0139] It should be understood that when the target debugging device needs to perform targeted debugging on one or several processors among the first processor 121, the third processor 1221, and the fourth processor 1222, it is necessary to add a target identifier in the debugging signal, and the target identifier is used to indicate the target processor among the first processor 121, the third processor 1221, and the fourth processor 1222 to be debugged, and only the target processor executes the debugging step after receiving the debugging signal. Among them, the debugging signal with the added identifier can be a data signal or an instruction signal, which is specifically set by those skilled in the art according to actual conditions, and is not limited by the embodiments of the present application.

[0140] During the debugging process, the target debugging device transmits a debugging signal to the first processor 121 through the target bidirectional level converter. After receiving the debugging signal, the first processor 121 determines the target processor according to the target identifier. If the target processor includes the first processor 121, the first processor 121 executes the debugging step according to the debugging signal, and then obtains and outputs the corresponding sub-result, which can be transmitted to the target bidirectional level converter through the third processor 1221 or the fourth processor 1222, and the third processor 1221 or the fourth processor 1222 will not execute the corresponding debugging step, that is, the debugging result transmitted to the target bidirectional level converter only includes the sub-result of the first processor 121.

[0141] If the target processor does not include the first processor 121, the first processor 121 does not perform the debugging step, and controls the second switching element 124 according to the target identifier to turn on the path between the first processor 121 and the third processor 1221, or to turn on the path between the first processor 121 and the fourth processor 1222, so as to transmit the debugging signal to the target processor, and the target processor includes the third processor 1221 or the fourth processor 1222.

[0142] If the target processor includes the first processor 121 and at least one of the third processor 1221 and the fourth processor 1222, the first processor 121 obtains the corresponding sub-result according to the debug signal, and then opens the path between the first processor 121 and the third processor 1221 according to the target identifier, or opens the path between the first processor 121 and the fourth processor 1222, so as to transmit the debug signal to the target processor.

[0143] Among them, when the second switch element 124 turns on the path between the first processor 121 and the third processor 1221, the first processor 121 will transmit the received debugging signal to the third processor 1221, so that the third processor 1221 can output the corresponding sub-result to the target bidirectional level converter according to the target identifier; when the second switch element 124 turns on the path between the first processor 121 and the fourth processor 1222, the first processor 121 will transmit the received debugging signal to the fourth processor 1222, so that the fourth processor 1222 can output the corresponding sub-result to the target bidirectional level converter according to the target identifier.

[0144] The target testing device of the above scheme can debug a designated target processor among two or more processors.

[0145] It should be noted that the structure of the second switch element 124 may refer to the structure of the first switch element 123 , which will not be described in detail here.

[0146] Among them, the above embodiment only describes the transmission scenario when there are three processors, but the structural framework when there are more than three processors is similar to the structural framework in the above embodiment, which will not be repeated here.

[0147] It can be understood that by setting the second switch element 124 between the first processor 121 and the third processor 1221, the first processor 121 can control the second switch element 124 to turn on the path corresponding to the third processor 1221 or the path corresponding to the fourth processor 1222, so as to transmit the debugging signal sent by the target debugging device to the third processor 1221 or the fourth processor 1222, so as to realize the fixed-point transmission of the debugging signal and improve the debugging efficiency of the target processor in the target identifier.

[0148] In some embodiments, Fig.13 As shown, the third processor 1221 and the fourth processor 1222 can also be connected through a third switch element 125, the input end of the third switch element 125 is respectively connected to the third processor 1221 and the second output end of the second switch element 124, the first output end of the third switch element 125 is connected to the fourth processor 1222, the second output end of the third switch element 125 is respectively connected to the first bidirectional level converter 11 and the second bidirectional level converter 15, and the third processor 1221 is also connected to the enable end of the third switch element 125, so that the third processor 1221 controls the third switch element 125 to turn on the path between the third processor 1221 and the fourth processor 1222 according to the target identifier, or turns on the path between the third processor 1221 and the first bidirectional level converter 11 and the second bidirectional level converter 15.

[0149] During the debugging process, when the target identifier indicates that the target processors to be debugged are the third processor 1221 and the fourth processor 1222, the third processor 1221 will control the third switch element 125 to turn on the path between the third processor 1221 and the fourth processor 1222, so as to transmit the debugging results and data signals output by the third processor 1221 to the fourth processor 1222, so that the fourth processor 1222 completes the debugging according to the data signal, and outputs the debugging results of the third processor and the debugging results of the fourth processor 1222 to the target bidirectional level converter.

[0150] When the target identifier only indicates that the target processor to be debugged is the third processor 1221, the third processor 1221 will control the third switch element 125 to turn on the path between the third processor 1221 and the first bidirectional level converter 11 and the second bidirectional level converter 15, so that the debugging results and data signals output by the third processor 1221 can be directly transmitted to the target bidirectional level converter to complete the debugging of the third processor 1221.

[0151] It should be noted that although the above embodiment only describes the structural framework when there are three processors (i.e., the first processor 121, the third processor 1221, and the fourth processor 1222), the structural framework when there are more than three processors is similar to the structural framework in the above embodiment, and will not be repeated here.

[0152] It should be noted that the structure of the third switch element 125 may refer to the structure of the first switch element 123 , which will not be described in detail here.

[0153] It can be understood that by setting the third switching element 125 between the third processor 1221 and the fourth processor 1222, when there is no need to debug the fourth processor 1222, the path between the third processor 1221 and the first bidirectional level converter 11 and the second bidirectional level converter 15 can be turned on, allowing the data signal to be directly transmitted to the target debugging device through the target bidirectional level converter, thereby reducing the consumption of the fourth processor 1222 and improving debugging efficiency.

[0154] Among them, the above-mentioned first switch element 123, the second switch element 124 and the third switch element 125 can be combined with each other, and the specific settings are made by those skilled in the art according to actual conditions, and the embodiments of the present application are not limited.

[0155] Fig.14 The following is a schematic diagram of the implementation structure of a server provided in an embodiment of the present application. Fig.14 As shown, the server may include a first debugging device, a connection interface, a controller 13, a first bidirectional level converter 11, a second bidirectional level converter 15, a processor 12 and a switch SW. In this embodiment, the first debugging device is BMC 14, and the connection interface is JTAG interface 16 as an example for description, and the processor 12 includes a first processor CPU1 and a second processor CPU2.

[0156] The JTAG interface 16 is connected to the second bidirectional level converter 15, the mode selection pin TMS of the JTAG interface 16 is connected to the first connection end of the second bidirectional level converter 15, the clock input pin TCK of the JTAG interface 16 is connected to the second connection end of the second bidirectional level converter 15, the test data input pin TDI of the JTAG interface 16 is connected to the third connection end of the second bidirectional level converter 15, and the test data output pin TDO of the JTAG interface 16 is connected to the fourth connection end of the second bidirectional level converter 15. The BMC 14 is connected to the first bidirectional level converter 11, and the connection relationship between the first bidirectional level converter 11 and the BMC 14 is similar.

[0157] The output end of the controller 13 is connected to the fifth connection end of the two bidirectional level converters. The sixth connection ends of the two bidirectional level converters are respectively connected to the mode selection receiving pins of the two processors, the seventh connection ends of the two bidirectional level converters are respectively connected to the clock receiving pins of the two processors, the eighth connection ends of the two bidirectional level converters are connected to the test data receiving pin of the first processor CPU1, and the ninth connection ends of the two bidirectional level converters are connected to the debugging result output pin of the second processor CPU2 (a transmission line is used in the figure to represent the two transmission lines connected to the fifth connection end and the sixth connection end), the first output end of the switch SW is respectively connected to the ninth connection end of the two bidirectional level converters, the second output end of the switch SW is connected to the second processor CPU2, and the second processor CPU2 is also connected to the control end of the switch SW.

[0158] Among them, because the BMC is usually fixed in the server, when the second debugging device is not connected to the connection interface, CPU1 and CPU2 are debugged through BMC14, that is, when the server is normally connected to the external power supply, the control flow diagram of the controller 13 is as follows: Fig.15 As shown, the following steps may be included:

[0159] In step S101 , the controller 13 sends an enable signal to the first bidirectional level converter 11 connected to the BMC 14 , so as to control the first bidirectional level converter connected to the BMC 14 to be in a working state.

[0160] For example, the controller 13 sends an enable signal EN_BMC to the first bidirectional level converter 11 to control the first bidirectional level converter 11 to be in a working state.

[0161] Step S102 , detecting in real time whether the second debugging device is connected to the JTAG interface 16 .

[0162] By way of example, the second debugging device may be XDP.

[0163] Step S103, when it is detected that the XDP is connected to the JTAG interface 16, the controller 13 sends an enable signal to the second bidirectional level converter connected to the XDP to control the second bidirectional level converter 15 connected to the XDP to be in a working state, and the controller 13 sends a control signal to the first bidirectional level converter 11 connected to the BMC 14 to control the first bidirectional level converter 11 to be in a non-working state; when it is detected that the XDP is not connected to the JTAG interface 16, execute step S11.

[0164] For example, if it is detected that the XDP is connected to the JTAG interface 16, that is, the controller 13 detects the in-place signal sent by the XDP, then the enable signal EN_XDP is only sent to the second bidirectional level converter connected to the XDP to control the second bidirectional level converter 15 connected to the XDP to be in a working state, and at the same time, a control signal is sent to the first bidirectional level converter 11 to control the first bidirectional level converter 11 to be in a non-working state.

[0165] When the first bidirectional level converter 11 is in working state, the BMC debugs the processor, and the first bidirectional level converter converts the first debugging signal sent by the BMC into a second debugging signal, and outputs the debugging parameters in the second debugging signal to transmit to the first processor CPU1 and the second processor CPU2, and outputs the input signal in the second debugging signal to the first processor CPU1. After the first processor CPU1 obtains the corresponding first sub-result according to the input signal, it outputs the input signal and the first sub-result to the switch SW. When the second processor CPU2 can execute the debugging process normally, it will send a switch control signal to the switch SW to make the switch SW turn on the connection between the first processor CPU1 and the second processor CPU2, so as to transmit the input signal and the first sub-result to the second processor CPU2, and the second processor CPU2 then outputs a first output signal, and the first output signal includes the first sub-result and the second sub-result corresponding to the second processor CPU2.

[0166] If the second processor CPU2 cannot perform the debugging process normally, the switch SW is controlled to conduct the connection between the first processor CPU1 and the first bidirectional level converter 11 and the second bidirectional level converter 15 to output a first output signal including the first sub-result. After receiving the first output signal, the first bidirectional level converter 11 performs level conversion on the first output signal to obtain and output a second output signal, so that the BMC 14 obtains the debugging result corresponding to the processor according to the second output signal.

[0167] When the second bidirectional level converter 15 is in working state, XDP debugs the processor, and the second bidirectional level converter converts the first debug signal sent by XDP into a second debug signal, and outputs the debug parameters in the second debug signal to transmit to the first processor CPU1 and the second processor CPU2. The subsequent process is consistent with the process in which only BMC14 is connected to one of the JTAG interfaces 16, and will not be repeated here.

[0168] The features disclosed in several product embodiments provided in the embodiments of the present application can be arbitrarily combined without conflict to obtain new product embodiments.

[0169] The above is only an implementation method of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A server, characterized in that: The server includes a first debugging device, a connection interface, a first bidirectional level converter, a second bidirectional level converter, a controller and a processor, wherein the first bidirectional level converter is connected between the processor and the first debugging device, the second bidirectional level converter is connected between the connection interface and the processor, and the first bidirectional level converter and the second bidirectional level converter are also connected to the controller respectively, wherein: The controller is used to control the second bidirectional level converter to be in an operating state when the second debugging device is in a connected state with the connection interface, so as to enable the second debugging device to debug the processor through the second bidirectional level converter, or to control the first bidirectional level converter to be in an operating state when the second debugging device is in a disconnected state with the connection interface, so as to enable the first debugging device to debug the processor through the first bidirectional level converter.

2. The server according to claim 1, characterized in that The processor comprises a first processor and a second processor, wherein: The input end of the first processor is connected to the first bidirectional level converter and the second bidirectional level converter, the output end of the first processor is connected to the input end of the second processor, and the output end of the second processor is respectively connected to the first bidirectional level converter and the second bidirectional level converter, so that after the target debugging device debugs the first processor through the target bidirectional level converter, the target debugging device continues to debug the second processor, wherein the target bidirectional level converter is the bidirectional level converter in a working state between the first bidirectional level converter and the second bidirectional level converter, and the target debugging device is a debugging device connected to the target bidirectional level converter.

3. The server according to claim 2, characterized in that The first processor and the second processor are connected via a first switch element, wherein: The enable end of the first switch element is connected to the second processor, the input end of the first switch element is connected to the first processor, the first output end of the first switch element is connected to the second processor, and the second output end of the first switch element is respectively connected to the first bidirectional level converter and the second bidirectional level converter, so as to control the first switch element to turn on the path between the first processor and the second processor, or to turn on the path between the first processor and the first bidirectional level converter and the second bidirectional level converter according to the target state of the second processor, and the target state includes a normal debugging state or an abnormal debugging state.

4. The server according to claim 2, characterized in that The debugging signal sent by the target debugging device to the processor includes a target identifier indicating the processor to be debugged, the second processor includes a third processor and a fourth processor connected in series, and the first processor and the third processor are connected via a second switch element, wherein: The input end of the second switch element is connected to the first processor, the first output end of the second switch element is connected to the third processor, the second output end of the second switch element is connected to the fourth processor, and the enable end of the second switch element is connected to the first processor, so that the first processor controls the second switch element to turn on the path between the first processor and the third processor, or turns on the path between the first processor and the fourth processor according to the target identifier.

5. The server according to claim 4, characterized in that The third processor and the fourth processor are further connected via a third switch element, wherein: The input end of the third switch element is respectively connected to the third processor and the second output end of the second switch element, the first output end of the third switch element is connected to the fourth processor, the second output end of the third switch element is respectively connected to the first bidirectional level converter and the second bidirectional level converter, and the enable end of the third switch element is connected to the third processor, so that the third processor controls the third switch element to turn on the path between the third processor and the fourth processor according to the target identifier, or turns on the path between the third processor and the first bidirectional level converter and the second bidirectional level converter.

6. The server according to claim 2, characterized in that The debugging signal sent by the target debugging device to the processor includes an instruction signal. The first bidirectional level converter is also connected to the first processor and the second processor respectively. The second bidirectional level converter is also connected to the first processor and the second processor respectively, so that when the target bidirectional level converter is in a working state, the target debugging device transmits the instruction signal to the first processor and the second processor respectively through the target bidirectional level converter. The instruction signal is used for debugging parameters when the first processor and the second processor perform debugging. The debugging parameters include at least one of a debugging clock and a debugging mode.

7. The server according to claim 1, wherein: The processor includes a first processor and a second processor, wherein an input end of the first processor is connected to the first bidirectional level converter and the second bidirectional level converter respectively, an output end of the first processor is connected to the first bidirectional level converter and the second bidirectional level converter respectively, an input end of the second processor is connected to the first bidirectional level converter and the second bidirectional level converter respectively, and an output end of the second processor is connected to the first bidirectional level converter and the second bidirectional level converter respectively, so as to respectively implement debugging of the first processor and the second processor by a target debugging device through a target bidirectional level converter, wherein the target bidirectional level converter is a bidirectional level converter in a working state between the first bidirectional level converter and the second bidirectional level converter, and the target debugging device is a debugging device connected to the target bidirectional level converter.

8. The server according to any one of claims 1 to 7, characterized in that: The controller controls the first bidirectional level converter to be in a working state, including: The controller sends an enable signal to the first bidirectional level converter to control the first bidirectional level converter to be in the working state.

9. The server according to claim 8, characterized in that The controller controls the second bidirectional level converter to be in a working state when the second debugging device is in a connected state with the connection interface, including: When the controller obtains the presence signal of the second debugging device through the connection interface, it is determined that the second debugging device and the connection interface are in the connection state, and the second bidirectional level converter is controlled to be in the working state.

10. The server according to any one of claims 1 to 7, characterized in that: The number of the second debugging devices and the number of the connection interfaces are both two or more, the number of the second bidirectional level converters is two or more, the second bidirectional level converters correspond to the connection interfaces one by one, and the controller is further used for: In the case that there is a one-to-one connection between the second debugging device and the connection interface, a target debugging device with a priority higher than a threshold is determined from two or more second debugging devices according to a preset priority, and a second bidirectional level converter connected to the target debugging device is controlled to be in an operating state.

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