Method for reducing damage of high-resistance structure during implementation of through hole process

Abstract

The invention provides a method for reducing the damage of a high-resistance structure during the implementation of a through hole process, and the method comprises the steps: 1, providing a substrate, and forming a metal layer and a first etching stop layer which are stacked from bottom to top on the substrate, a first resistance layer, a second etching stop layer, an insulating layer, a second resistance layer, a third etching stop layer and a dielectric layer which are stacked from bottom to top are formed on the portion, located in the high-resistance area, of the first etching stop layer, and a dielectric layer is formed on the portion, located in the non-high-resistance area, of the first etching stop layer; step 2, etching the dielectric layer; step 3, etching the exposed first etching stop layer and the third etching stop layer; fourthly, after a mask layer covering the non-high-resistance area is formed, the second resistance layer is etched; 5, after the insulating layer and the second etching stop layer are etched in sequence, the mask layer is removed; and step 6, filling metal in the formed through hole. The two layers of resistors are connected in parallel, the second layer of resistor serves as a buffer layer in the through hole etching process, and loss of the first layer of resistor is reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for reducing damage to a high-resistance structure when implementing a through-hole process. Background Art

[0002] With the continuous development of integrated circuits, there are increasingly higher requirements for the turn-on voltage. However, due to the limitations of the integrated circuit structure and materials, there is not much room for optimization on the gate. The high-resistance process (TiN) came into being and plays the role of voltage division in the circuit. TiN itself is very sensitive to thickness. A thickness change of 1 angstrom will cause a 50Ω change in resistance. In the circuit, in order to ensure the stability of the resistance value, the thickness of TiN must be stable within a certain range. And in order to obtain a high-resistance device with a higher resistance value (630±63Ω), the thickness of TiN is generally made very thin. However, due to the height difference between the high-resistance area and other areas, when the through-hole is etched, the high-resistance area is closer to the plasma area and is in contact with the plasma for a longer time, which will damage the surface of this thinner TiN layer. In severe cases, it may even break through the high-resistance area. Figure 1 As shown, this may lead to abnormal resistance or even failure, ultimately affecting product performance. Summary of the invention

[0003] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a method for reducing damage to high-resistance structures when implementing a through-hole process, so as to solve the problems in the prior art.

[0004] To achieve the above-mentioned purpose and other related purposes, the present application provides a method for reducing damage to high-resistance structures when implementing a through-hole process, comprising:

[0005] Step 1, providing a substrate, forming a metal layer and a first etch stop layer stacked from bottom to top on the substrate, forming a first resistance layer, a second etch stop layer, an insulating layer, a second resistance layer, a third etch stop layer and a dielectric layer stacked from bottom to top on the portion of the first etch stop layer located in the high resistance region, and forming a dielectric layer on the portion of the first etch stop layer located in the non-high resistance region;

[0006] Step 2, etching the dielectric layer;

[0007] Step three, etching the exposed first etch stop layer and the third etch stop layer;

[0008] Step 4, after forming a mask layer covering the non-high resistance area, etching the second resistance layer;

[0009] Step 5, after etching the insulating layer and the second etching stop layer in sequence, removing the mask layer;

[0010] Step six, filling the formed through-hole with metal.

[0011] Preferably, the material of the first resistance layer includes titanium nitride, and the second resistance layer is a HiR layer.

[0012] Preferably, the resistance of the second resistance layer is greater than the resistance of the first resistance layer.

[0013] Preferably, the material of the metal layer includes cobalt, nickel or tungsten.

[0014] Preferably, the material of the first etch stop layer, the second etch stop layer and the third etch stop layer comprises silicon nitride.

[0015] Preferably, the materials of the insulating layer and the dielectric layer include silicon oxide.

[0016] Preferably, the etching in step 2 to step 5 is dry etching.

[0017] Preferably, after step three is completed, a required through hole is formed in the non-high resistance area.

[0018] Preferably, the mask layer includes a bottom anti-reflective coating layer and a photoresist layer stacked from bottom to top.

[0019] Preferably, the metal filled in the through hole includes aluminum.

[0020] As described above, the method for reducing damage to high-resistance structures when implementing a through-hole process provided in the present application has the following beneficial effects: a second layer of resistors is formed on the first layer of resistors (TiN) by connecting resistors in parallel (using thicker high-resistance materials to ensure that the resistance of the second layer of resistors is much greater than that of the first layer of resistors). The second layer of resistors can be used as a buffer layer during the through-hole etching process to reduce the loss of the first layer of resistors. After the two are connected in parallel, the equivalent resistance of the entire circuit will be infinitely close to that of the first layer of resistors. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] Figure 1 It is a schematic diagram showing a cross-sectional structure of a device in which a high-resistance structure is damaged when a through-hole process is implemented according to the prior art;

[0023] Figure 2 A flow chart showing a method for reducing damage to a high-resistance structure when implementing a through-hole process provided by an embodiment of the present application;

[0024] Figure 3A-Figure 3FShown is a schematic diagram of a device cross-sectional structure formed after each step is completed in a method for reducing damage to a high-resistance structure when implementing a through-hole process provided in an embodiment of the present application. DETAILED DESCRIPTION

[0025] The following describes the implementation of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific implementations, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0026] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, rather than all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0027] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating directions or positional relationships, are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0028] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0029] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0030] See also Figure 2 , which shows a flow chart of a method for reducing damage to high-resistance structures when implementing a through-hole process provided by an embodiment of the present application.

[0031] like Figure 2As shown, the method for reducing high-resistance structure damage when implementing a through-hole process includes the following steps:

[0032] Step 1, providing a substrate, forming a metal layer and a first etch stop layer stacked from bottom to top on the substrate, forming a first resistance layer, a second etch stop layer, an insulating layer, a second resistance layer, a third etch stop layer and a dielectric layer stacked from bottom to top on the portion of the first etch stop layer located in the high resistance region, and forming a dielectric layer on the portion of the first etch stop layer located in the non-high resistance region;

[0033] Step 2, etching the dielectric layer;

[0034] Step three, etching the exposed first etch stop layer and the third etch stop layer;

[0035] Step 4, after forming a mask layer covering the non-high resistance area, etching the second resistance layer;

[0036] Step 5, after etching the insulating layer and the second etching stop layer in sequence, removing the mask layer;

[0037] Step six, filling the formed through-hole with metal.

[0038] In step 1, optionally, the substrate is a silicon substrate, a germanium substrate, or a silicon-on-insulator substrate, etc.; or the material of the substrate may also include other materials, such as III-V compounds such as gallium arsenide. Those skilled in the art can select the constituent material of the substrate according to the type of device structure formed on the substrate, so the type of the substrate should not limit the protection scope of the present invention.

[0039] like Figure 3A As shown, a metal layer 300 and a first etch stop layer 301 are stacked from bottom to top on the substrate. As an example, the material of the metal layer 300 includes cobalt, nickel, tungsten, etc., and the material of the first etch stop layer 301 includes silicon nitride.

[0040] Various semiconductor devices, such as MOS tubes, diodes, etc., are formed in different regions of the substrate. An interlayer dielectric layer is formed between the metal layer 300 and the substrate. Optionally, the material of the interlayer dielectric layer is, for example, but not limited to: silicon nitride (Si3N4), silicon oxide (SiO2), fluorinated SiO2 (FSG), hydrogenated carbon oxide (SiCOH), porous SiCOH, borophosphosilicate glass (BPSG), silsesquioxane, carbon (C) doped oxides (i.e., organic silicates) including silicon (Si), carbon (C), oxygen (O) and / or hydrogen (H) atoms, thermosetting polyarylene ether, or other materials with low dielectric constants (<3.9). A copper interconnection structure is formed in the interlayer dielectric layer. For simplicity, the substrate, interlayer dielectric layer and copper interconnection structure are not shown in the legend.

[0041] A first resistance layer 302, a second etch stop layer 303, an insulating layer 305, a second resistance layer 306, a third etch stop layer 307 and a dielectric layer 308 are stacked from bottom to top on the portion of the first etch stop layer 301 located in the high resistance area, and a dielectric layer 308 is formed on the portion of the first etch stop layer 301 located in the non-high resistance area.

[0042] As an example, the material of the first resistance layer 302 includes titanium nitride (TiN), the second resistance layer 306 is a high resistance (HiR) layer (using a thicker high resistance material, mainly formed by high resistance polysilicon, that is, ion doping of polysilicon to adjust the required resistance), the resistance of the second resistance layer 306 is much greater than the resistance of the first resistance layer 302, the material of the second etch stop layer 303 and the third etch stop layer 307 includes silicon nitride, and the material of the insulating layer 305 and the dielectric layer 308 includes silicon oxide.

[0043] In step 2, the dielectric layer 308 is etched, and after the etching is completed, a portion of the first etch stop layer 301 and a portion of the third etch stop layer 307 are exposed. Exemplarily, the etching is dry etching.

[0044] In step three, etching is performed on the exposed first etch stop layer 301 and the third etch stop layer 307. After etching, a portion of the second resistor layer 306 is exposed, and a required through hole is formed in the non-high resistance region. Exemplarily, the etching is dry etching.

[0045] In step 4, after forming a mask layer covering the non-high resistance area, the second resistance layer 306 is etched, and after the etching is completed, a portion of the insulating layer 305 is exposed. Exemplarily, the mask layer includes a bottom anti-reflection coating 309 and a photoresist layer 310 stacked from bottom to top, and the etching is dry etching.

[0046] In step five, after etching the insulating layer 305 and the second etching stop layer 303 in sequence, the mask layer is removed. Exemplarily, the etching is dry etching, and after the etching is completed, the required through hole is formed in the non-high resistance area. Exemplarily, the mask layer is removed by an ashing process.

[0047] In step six, metal 311 is filled in the formed through hole. As an example, a deposition process is first performed to form a metal layer, and then a grinding process is performed to remove the metal layer outside the through hole. Exemplarily, the material of metal 311 includes aluminum.

[0048] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present application in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0049] In summary, the method of reducing the damage of high-resistance structure when implementing the through-hole process of the present application adopts the method of connecting resistors in parallel to form a second layer of resistors on the first layer of resistors (TiN) (using thicker high-resistance materials to ensure that the resistance of the second layer of resistors is much greater than that of the first layer of resistors). The second layer of resistors can be used as a buffer layer in the through-hole etching process to reduce the loss of the first layer of resistors. After the two are connected in parallel, the equivalent resistance of the entire circuit will be infinitely close to the first layer of resistors. Therefore, the present application effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0050] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present application.

Claims

1. A method for reducing damage to high-resistance structures when implementing a through-hole process, characterized in that: The method comprises: Step 1, providing a substrate, on which a metal layer and a first etch stop layer are stacked from bottom to top, a first resistance layer, a second etch stop layer, an insulating layer, a second resistance layer, a third etch stop layer and a dielectric layer are stacked from bottom to top on a portion of the first etch stop layer located in a high resistance region, and the dielectric layer is formed on a portion of the first etch stop layer located in a non-high resistance region; Step 2, etching the dielectric layer; Step three, etching the exposed first etch stop layer and the third etch stop layer; Step 4, after forming a mask layer covering the non-high resistance area, etching the second resistance layer; Step 5, after etching the insulating layer and the second etching stop layer in sequence, removing the mask layer; Step six, filling the formed through-hole with metal.

2. The method according to claim 1, characterized in that: The material of the first resistance layer includes titanium nitride, and the second resistance layer is a HiR layer.

3. The method according to claim 1, characterized in that The resistance of the second resistance layer is greater than the resistance of the first resistance layer.

4. The method according to claim 1, characterized in that: The material of the metal layer includes cobalt, nickel or tungsten.

5. The method according to claim 1, characterized in that The material of the first etch stop layer, the second etch stop layer and the third etch stop layer includes silicon nitride.

6. The method according to claim 1, characterized in that The insulating layer and the dielectric layer are made of silicon oxide.

7. The method according to claim 1, characterized in that The etching in step 2 to step 5 is dry etching.

8. The method according to claim 1, characterized in that After the step three is completed, the required through holes are formed in the non-high resistance area.

9. The method according to claim 1, characterized in that: The mask layer includes a bottom anti-reflection coating layer and a photoresist layer stacked from bottom to top.

10. The method according to claim 1, characterized in that The metal filled in the through hole includes aluminum.

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