Nanometer silicon through hole preparation method and chip packaging structure

Abstract

The invention provides a nanometer silicon through hole preparation method and a chip packaging structure, and relates to the technical field of semiconductors, and the method comprises the steps: obtaining a first wafer; preparing a first deep hole in the first surface of the first wafer through etching; carrying out incomplete filling on the first deep hole by utilizing a dielectric layer material by controlling deposition conditions of CVD (Chemical Vapor Deposition) to obtain a second deep hole with a cavity; performing an IC process on the first surface to prepare an IC device layer; preparing a first metal layer on the surface of the IC device layer by using a first metal material, so that metal connection is realized between the first metal layer and an IC device in the IC device layer, and the first metal layer covers the second deep hole; thinning the second surface of the first wafer until the cavity of the second deep hole is exposed; and filling the second deep hole with the first metal material to obtain the nanometer silicon through hole structure.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for preparing a nano-through silicon via and a chip packaging structure. Background Art

[0002] Through Silicon Via technology is an important semiconductor advanced packaging technology that allows direct electrical connection between silicon wafers through vertical through holes, which can promote the development of integrated circuits to higher integration and smaller size, and meet the ever-increasing requirements for performance and power consumption. At present, the common method of through silicon via in packaging is to make the through silicon via separately on a wafer, and then connect it to the wafer containing logic or storage structure through bonding.

[0003] As the size of through silicon vias gradually decreases, the size of the through-holes and the size of the devices gradually approach each other, and the demand for interconnection increases. However, it is still difficult for existing technologies to make the process of through silicon vias compatible with the IC process and implement them on the same wafer. Summary of the invention

[0004] In view of the above problems, the embodiments of the present application provide a method for preparing a nano-through silicon via and a chip packaging structure to overcome the above problems or at least partially solve the above problems.

[0005] In a first aspect of an embodiment of the present application, a method for preparing a nano-through silicon via is provided, the method comprising: Obtain a first wafer, and determine a first surface of the first wafer, where the first surface is a surface of the first wafer on which an IC process is to be performed; Preparing a first deep hole on the first surface of the first wafer by etching; By controlling the deposition conditions of CVD chemical vapor deposition, the first deep hole is partially filled with a dielectric layer material to obtain a second deep hole with a cavity; Performing an IC process on the first surface to prepare an IC device layer; Using a first metal material, a first metal layer is prepared on the surface of the IC device layer, so that the first metal layer and the IC device in the IC device layer are metal-connected, and the first metal layer covers the second deep hole; Thinning the second surface of the first wafer until the cavity of the second deep hole is exposed; The second deep hole is filled with the first metal material to obtain a nano-silicon via structure.

[0006] In a possible implementation manner, the method of using the first metal material to fill the second deep hole to obtain a nano-silicon via structure includes: Etching the dielectric layer material in the second deep hole until the first metal layer is exposed; The cavity of the second deep hole is filled with metal using the first metal material to obtain the nano-silicon via structure.

[0007] In a possible implementation, the method further includes: A second metal layer is prepared on the second surface by using the first metal material, so that the second metal layer is connected to the first metal layer through the nano-silicon via structure.

[0008] In a possible implementation manner, preparing the first deep hole on the first surface of the first wafer by etching includes: Determining the position of each IC device in the IC process to be performed on the first surface of the first wafer; Determine the position of the first deep hole with the goal of not overlapping the position of each IC device; According to the position of the first deep hole, the first deep hole is etched on the first surface of the first wafer.

[0009] In a possible implementation, the first metal material is one or more of copper, tungsten, ruthenium, and aluminum.

[0010] In a possible implementation manner, the diameter of the nano-through silicon via structure is 100 nm-1 um, and the depth is 1 um-10 um.

[0011] In a possible implementation manner, the depth of the first deep hole is 2-3 um.

[0012] In a possible implementation manner, the dielectric layer material is silicon oxide or silicon nitride.

[0013] In a possible implementation, the deposition conditions of the CVD chemical vapor deposition include: CVD raw material gas concentration and reaction temperature.

[0014] The second aspect of the embodiment of the present application further provides a chip packaging structure, which includes a first wafer, wherein the first wafer includes a nano-silicon via structure, and the nano-silicon via structure is prepared by the nano-silicon via preparation method described in the first aspect of the embodiment of the present application.

[0015] An embodiment of the present application provides a method for preparing a nano-silicon via, the method comprising: obtaining a first wafer, determining a first surface of the first wafer, the first surface being a surface on which an IC process is to be performed on the first wafer; preparing a first deep hole on the first surface of the first wafer by etching; controlling the deposition conditions of CVD chemical vapor deposition, incompletely filling the first deep hole with a dielectric layer material to obtain a second deep hole with a cavity; performing an IC process on the first surface to prepare an IC device layer; preparing a first metal layer on the surface of the IC device layer by using a first metal material, so that a metal connection is achieved between the first metal layer and the IC device in the IC device layer, and the first metal layer covers the second deep hole; thinning from the second surface of the first wafer until the cavity of the second deep hole is exposed; filling the second deep hole with the first metal material to obtain a nano-silicon via structure.

[0016] The nano-silicon via preparation method provided in the present application utilizes CVD chemical vapor deposition to perform incomplete filling in the first deep hole obtained by etching to form a cavity, and to occupy the deep hole (to prepare a second deep hole with a cavity). On this basis, an IC process is performed to prepare a first metal layer, and the IC device in the IC device layer and the deep hole are connected through the first metal layer, and then the deep hole is filled to obtain a nano-silicon via structure, which realizes the adaptation of the processing of the silicon via and the processing of the IC device to the same wafer, thereby improving the interconnection density and flexibility of the wafer packaging. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments of the present application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0018] Figure 1 It is a flow chart of the steps of a method for preparing a nano-through silicon via provided in an embodiment of the present application; Figure 2 It is a schematic structural diagram of a first deep hole formed by a method for preparing a nano-through silicon via provided in an embodiment of the present application; Figure 3 is a schematic structural diagram of a second deep hole formed by a method for preparing a nano-through silicon via provided in an embodiment of the present application; Figure 4 It is a schematic structural diagram of an IC device layer formed by a method for preparing a nano-through silicon via provided in an embodiment of the present application; Figure 5It is a schematic structural diagram of a first metal layer formed by a method for preparing a nano-through silicon via provided in an embodiment of the present application; Figure 6 It is a schematic diagram of a thinned structure formed by a method for preparing a nano-through silicon via provided in an embodiment of the present application; Figure 7 It is a schematic diagram of a structure after etching formed by a method for preparing a nano-through silicon via provided in an embodiment of the present application; Figure 8 It is a schematic diagram of a nano-through silicon via structure formed by a nano-through silicon via preparation method provided in an embodiment of the present application; Fig. 9 It is a schematic diagram of a chip packaging structure formed by a method for preparing a nano-through silicon via provided in an embodiment of the present application; Fig.10 It is a structural schematic diagram of a nano-through silicon via preparation device provided in an embodiment of the present application; Description of the drawings: a first wafer 100 , a first deep hole 101 , a second deep hole 102 of a cavity, an IC device layer 103 , a first metal layer 104 , a nano-silicon via structure 105 , and a second metal layer 106 . DETAILED DESCRIPTION

[0019] The exemplary embodiments of the present application will be described in more detail below in conjunction with the accompanying drawings in the embodiments of the present application. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present application and to enable the scope of the present application to be fully communicated to those skilled in the art.

[0020] Nano-Through-Silicon-Via (nTSV) is a nano-scale through-hole that penetrates the silicon wafer and is filled with metal. TSV technology is an important advanced semiconductor packaging technology that allows direct electrical connection between silicon wafers through vertical through-holes, which can promote the development of integrated circuits to higher integration and smaller size, meeting the requirements for increasing performance and power consumption.

[0021] Through silicon vias have been widely used in advanced packaging, but the aperture is generally between tens and hundreds of microns, and the density is low. In addition, the common method of through silicon vias in packaging is to make the through silicon vias separately on a wafer, and then connect it to the wafer containing logic or storage structures through bonding.

[0022] The small size of nano-silicon vias has a density advantage, which can form a higher interconnection density per unit area, and thus has a higher practical value. In addition, as the size of silicon vias is gradually reduced to the sub-micron scale, the size of the vias is gradually approaching the size of the device, and nano-silicon vias can be connected to structures as small as a few devices, greatly improving the interconnection density and flexibility. However, the existing technology still finds it difficult to make the silicon via process compatible with the IC process and implement it on the same wafer.

[0023] In view of the above problems, the present application proposes a method for preparing a nano-through silicon via and a chip packaging structure to achieve compatibility between the through silicon via process and the IC process and implement them on the same wafer. The following is a detailed description of a method for preparing a nano-through silicon via provided by the present application in conjunction with the accompanying drawings through some embodiments and their application scenarios.

[0024] The first aspect of the present application provides a method for preparing a nano-silicon via, referring to Figure 1 , Figure 1 A flow chart of the steps of a method for preparing a nano-silicon via provided in an embodiment of the present application is shown in FIG. Figure 1 As shown, the method includes: Step S101 , obtaining a first wafer, and determining a first surface of the first wafer, where the first surface is a surface of the first wafer on which an IC process is to be performed.

[0025] In this embodiment, the first wafer can be a bare silicon wafer, and the first wafer has two upper and lower surfaces, namely a first surface and a second surface, and the first surface is the surface on which the IC process is to be performed on the first wafer. The IC process refers to a process flow in which the first wafer is processed in multiple steps so that one or more IC devices are embedded inside or on the surface of the wafer, and electrical connections are achieved in the subsequent packaging process or in the bonded stacking structure formed by multiple wafers. In different application scenarios, the IC processes performed on the wafer are different, and the IC devices involved are different. In this embodiment, the IC process is not specifically limited.

[0026] Step S102 , preparing a first deep hole on the first surface of the first wafer by etching.

[0027] Reference Figure 2 , Figure 2 A schematic diagram of the structure of a first deep hole formed by a method for preparing a nano-silicon through-hole is shown. Figure 2 As shown, according to the size of the through silicon via to be prepared, a first deep hole 101 is prepared on the first surface of the first wafer 100 by etching. Figure 2As shown, the height of the first deep hole can be determined according to actual needs, at least it cannot be the same as the thickness of the wafer, that is, it cannot be converted into a through-hole structure. Among them, the position of the first deep hole 101 (that is, the position of the silicon through hole required in the end) can be determined according to actual application requirements. Since the IC process needs to be performed on the first surface in subsequent steps, when determining the position of the first deep hole 101, it is necessary to fully consider the impact on the subsequent IC process, for example, the position of the first deep hole cannot occupy the position of the IC device.

[0028] In a possible implementation manner, the depth of the first deep hole is 2-3 um. The diameter of the first deep hole may be 100 nm-1 um.

[0029] In a possible implementation manner, the step S102, preparing a first deep hole on the first surface of the first wafer by etching, includes: Step S1021 , determining the position of each IC device in the IC process to be executed on the first surface of the first wafer.

[0030] Step S1022 , determining the position of the first deep hole with the goal of not overlapping the position of each IC device.

[0031] Step S1023 , etching the first deep hole on the first surface of the first wafer according to the position of the first deep hole.

[0032] In this embodiment, according to the IC process to be performed (i.e., the IC process to be performed in step S104), the positions of the involved IC devices on the first surface are determined, such as the position of the chip, the position of the metal PAD, etc. With the goal that the position of the first deep hole does not overlap with the positions of the IC devices, the position of the first deep hole is determined from the remaining first surface, and then etching is performed to obtain the first deep hole.

[0033] Step S103, by controlling the deposition conditions of CVD chemical vapor deposition, the first deep hole is partially filled with a dielectric layer material to obtain a second deep hole with a cavity.

[0034] Specifically, refer to Figure 3 , Figure 3 A schematic diagram of the structure of a second deep hole formed by a method for preparing a nano-Through Silicon Via is shown. Figure 3 As shown, the embodiment of the present application adopts chemical vapor deposition to deposit a layer of dielectric layer material into the first deep hole. Since the aperture of the first deep hole is relatively small relative to the height of the deep hole, the faster deposition rate will cause the opening of the deep hole to be filled before the interior of the first deep hole, so that the interior of the first deep hole is not completely filled, forming the following Figure 3The second deep hole 102 with a cavity is shown. Then, the excess dielectric layer material on the first surface is removed by oxygen plasma etching, so that the first surface remains a smooth plane.

[0035] In a possible implementation manner, the dielectric layer material is silicon oxide or silicon nitride.

[0036] In a possible implementation, the deposition conditions of the CVD chemical vapor deposition include: CVD raw material gas concentration and reaction temperature.

[0037] Specifically, the first deep hole can be incompletely filled by controlling the two conditions of the raw gas concentration and temperature of the vapor deposition. By increasing the raw gas concentration or lowering the temperature, the dielectric layer material is caused to accumulate at the opening of the first deep hole. In the actual application process of CVD deposition, due to different processes, the raw gas used is different, and the concentration and reaction temperature will also vary greatly. In the embodiment of the present application, the specific value range of the raw gas concentration and the reaction temperature is not limited. For example, when using the PECVD method, ethyl silicate TEOS is used as a raw material to deposit 300nm thick silicon dioxide of general quality, the reaction temperature is between 250℃-400℃, and the raw gas composition volume ratio (ie, raw gas concentration) is TEOS: oxygen = 1:5-1:10. It should be noted that the actual process parameters still need to be adjusted in combination with the quality of the required film, the deposition rate, and the equipment itself. Therefore, the data provided in the above example can only be used as a reference for "typical examples".

[0038] Step S104: performing an IC process on the first surface to prepare an IC device layer.

[0039] In the embodiment of the present application, the specific scheme of the IC process is not limited. The IC process may include embedding the chip in the buried groove after etching, or using a dual damascene wiring process to prepare one or more metal interconnect structures. Figure 4 , Figure 4 A schematic diagram of the structure of an IC device layer formed by a method for preparing a nano-Through Silicon Via is shown. Figure 4 As shown, different IC processes ultimately result in different structures. There may be IC devices (such as chips, metal interconnect structures, etc.) embedded in the first wafer, or there may be IC devices and related dielectric materials fixed on the first surface of the first wafer. In the embodiment of the present application, they may be uniformly represented as a hierarchical structure, namely, the IC device layer 103. Figure 4 As shown, during the IC process, the structure of the second deep hole is not affected, so that the surface of the IC device layer finally prepared is located on the same horizontal plane as the surface of the second deep hole.

[0040] Step S105, using a first metal material to prepare a first metal layer on the surface of the IC device layer, so that the first metal layer and the IC devices in the IC device layer are metal-connected, and the first metal layer covers the second deep hole.

[0041] In the embodiment of the present application, the first metal layer is used to realize the metal connection between some IC devices in the IC device layer and the second deep hole, and the first metal layer may include metal interconnect structures of different shapes. The specific structure and preparation method of the first metal layer will change with the change of IC process, and will be designed according to the actual process requirements, and will not be limited in the embodiment of the present application. Figure 5 , Figure 5 A schematic diagram of the structure of a first metal layer formed by a method for preparing a nano-Through Silicon Via is shown. Figure 5 As shown, the first metal layer may contain metal structures connected between IC devices in the IC device layer, or may contain related dielectric materials that play a fixing or filling role, or may contain metal structures connected to the second deep hole. The connection between the first metal layer and the second deep hole does not destroy the original structure of the second deep hole, which means that the metal component in the first metal layer covers the top of the second deep hole, that is, the opening of the original first deep hole. In the embodiment of the present application, it can be uniformly represented as a hierarchical structure located above the IC device layer, that is, the first metal layer 104.

[0042] In a possible implementation, the first metal material is one or more of copper, tungsten, ruthenium, and aluminum.

[0043] Step S106, thinning the second surface of the first wafer until the cavity of the second deep hole is exposed.

[0044] In this embodiment, a multi-step thinning method can be used to thin the surface of the first wafer facing away from the first surface (i.e., the second surface) to expose the cavity of the second deep hole. The thinning process generally uses a multi-step thinning method (mechanical thinning-CMP-dry etching) to achieve the required silicon layer thickness. Figure 6 , Figure 6 A schematic diagram of a thinned structure formed by a method for preparing a nano-Through Silicon Via is shown. Figure 6 As shown, the back side (i.e., the second surface) of the first wafer is thinned until the cavity of the second deep hole is exposed. Alternatively, the thinning thickness is calculated according to the required height of the through silicon via, so that the height of the second deep hole remaining after thinning is the same as the final required height of the through silicon via.

[0045] Step S107, using the first metal material to fill the second deep hole to obtain a nano-silicon via structure.

[0046] In a possible implementation manner, the step S107, using the first metal material to fill the second deep hole to obtain a nano-silicon via structure, includes: Step S1071, etching the dielectric layer material in the second deep hole until the first metal layer is exposed.

[0047] Specifically, refer to Figure 7 , Figure 7 A schematic diagram of a structure after etching formed by a method for preparing a nano-Through Silicon Via is shown. Figure 7 As shown, after the thinning process in step S106, since a dielectric layer material is still deposited at the other end of the second deep hole, in step S1071, the dielectric layer material in the second deep hole is etched until the first metal layer at the bottom is exposed.

[0048] Step S1072: Use the first metal material to fill the cavity of the second deep hole with metal to obtain the nano-silicon via structure.

[0049] Specifically, refer to Figure 8 , Figure 8 A schematic diagram of a nano-through silicon via structure formed by a method for preparing a nano-through silicon via is shown. Figure 8 As shown, after the etching is completed, the second deep hole is filled by metal deposition to form a nano silicon through hole structure 105, and the silicon through hole is metal-connected to the first metal layer. Thus, the nano silicon through hole structure is metal-connected to the relevant IC device in the IC device through the first metal layer (the metal component therein). The first metal material is the same as the metal material used to prepare the first metal layer. The first metal material is one or more of copper, tungsten, ruthenium, and aluminum.

[0050] In a possible implementation, the diameter of the nano-silicon through hole structure is 100nm-1um, and the depth is 1um-10um. Correspondingly, the diameter of the first deep hole and the second deep hole in the previous steps S102-S106 is 100nm-1um. Since the depth of the second deep hole (i.e., the height of the deep hole) will be reduced to a certain extent when thinning from the second surface in step S106, the depth of the first deep hole and the second deep hole in steps S102-S105 will slightly exceed 1um-10um. Further, the depth of the nano-silicon through hole structure is 2-3um.

[0051] In a possible implementation, the method further includes: Step S108, using the first metal material to prepare a second metal layer on the second surface, so that the second metal layer is connected to the first metal layer through the nano-silicon via structure.

[0052] In this embodiment, after the through hole is filled with metal to prepare the nano-silicon through hole structure, the excess first metal material on the second surface can be removed to keep the second surface smooth. Then, the second metal layer is further prepared on the second surface, so that the upper surface (the first metal layer on the first surface) and the lower surface (the second metal layer on the second surface) of the first wafer can be connected through the processed nano-silicon through hole structure, forming a connection channel from the front metal layer to the back metal layer that runs through the silicon wafer. In particular, when preparing the second metal layer, the same first metal material as the first metal layer and the nano-silicon through hole structure can be used, and the first metal material can be one or more of copper, tungsten, ruthenium, and aluminum.

[0053] In the embodiment of the present application, the second metal layer may include metal interconnect structures of different shapes. The specific structure and preparation method of the second metal layer are designed according to actual process requirements and are not limited in the embodiment of the present application. Fig. 9 , Fig. 9 A schematic diagram of a chip packaging structure formed by a nano-silicon via preparation method is shown. Fig. 9 As shown, a back metal layer, i.e., a second metal layer 106, is formed on the back of the first wafer. The connection between the second metal layer 106 and the nano-Through Silicon Via structure 105 does not destroy the original structure of the TSV, which means that the metal component in the second metal layer covers the bottom of the TSV 106. In the embodiment of the present application, it can be uniformly represented as a hierarchical structure located on the second surface of the first wafer, i.e., the second metal layer 106, completing the TSV processing from the front metal layer to the back metal layer.

[0054] The nano-silicon via preparation method provided in the present application utilizes CVD chemical vapor deposition to perform incomplete filling in the first deep hole obtained by etching to form a cavity and occupy the deep hole (preparing a second deep hole with a cavity). On this basis, the IC process is performed to prepare a first metal layer, and the IC device in the IC device layer and the deep hole are connected through the first metal layer, and then the deep hole is filled to obtain a nano-silicon via structure, so that the processing of the silicon via and the processing of the IC device can be adapted to the same wafer, thereby improving the interconnection density and flexibility of the wafer packaging. The present application provides a nano-silicon via processing method that is compatible with the manufacture of nano-IC devices on the same silicon wafer, and provides an excellent solution with high adaptability for achieving high-density vertical interconnection. In addition, the solution for leaving holes for the nano-silicon via structure does not require high-precision lithography alignment.

[0055] A second aspect of an embodiment of the present application further provides a chip packaging structure, which includes a first wafer, wherein the first wafer includes a nano-silicon via structure, and the nano-silicon via structure is prepared by the nano-silicon via preparation method described in the first aspect.

[0056] Specifically, the chip packaging structure is as follows Fig. 9 As shown, the chip packaging structure includes: a first wafer 100, an IC device layer 103, a first metal layer 104, a nano-silicon through hole structure 105, and a second metal layer 106. Among them, the first metal layer 104 and the second metal layer 106 are connected through the nano-silicon through hole structure 105, the IC device in the IC device layer 103 is connected to the metal device in the first metal layer 104, and the metal device in the first metal layer 104 is connected to the nano-silicon through hole structure 105. Among them, the specific structure of the IC device layer is determined by the specific IC process, and the structure of the IC device layer is not limited in this embodiment. Exemplarily, the IC device layer may include a plurality of chips embedded in the buried groove, a metal pad connected to the chip, and a dielectric layer material that plays a fixing and filling role. Correspondingly, in this embodiment, the specific structure of the first metal layer and the second metal layer is not limited, as long as the first metal layer and the second metal layer contain: a metal interconnect structure connected to the nano-silicon through hole structure.

[0057] The third aspect of the embodiment of the present application provides a through silicon via preparation device, which is used to perform the steps in the nano-through silicon via preparation method provided in the first aspect, referring to Fig.10 , Fig.10 A schematic diagram of the structure of a through silicon via preparation device is shown. Fig.10 As shown, the device comprises: A wafer acquisition module, used for acquiring a first wafer and determining a first surface of the first wafer, where the first surface is a surface of the first wafer on which an IC process is to be performed; An etching module, used for preparing a first deep hole on the first surface of the first wafer by etching; A first filling module, used for incompletely filling the first deep hole with a dielectric layer material by controlling the deposition conditions of CVD chemical vapor deposition to obtain a second deep hole with a cavity; An IC process execution module, used for executing an IC process on the first surface to prepare an IC device layer; A first metal layer preparation module, used for preparing a first metal layer on the surface of the IC device layer using a first metal material, so that the first metal layer and the IC device in the IC device layer are metal-connected, and the first metal layer covers the second deep hole; A thinning module, used for thinning the second surface of the first wafer until the cavity of the second deep hole is exposed; The second filling module is used to fill the second deep hole with the first metal material to obtain a nano-silicon via structure.

[0058] In a possible implementation manner, the second filling module includes: A first etching submodule, used for etching the dielectric layer material in the second deep hole until the first metal layer is exposed; The filling submodule is used to use the first metal material to perform metal filling on the cavity of the second deep hole to obtain the nano-silicon via structure.

[0059] In a possible implementation, the device further includes: The second metal layer preparation module is used to prepare a second metal layer on the second surface using the first metal material, so that the second metal layer is connected to the first metal layer through the nano-silicon via structure.

[0060] In a possible implementation, the etching module includes: An IC device position determination submodule, used to determine the position of each IC device on the first surface of the first wafer in the IC process to be performed; A first deep hole position determination submodule, used to determine the position of the first deep hole with the goal of not overlapping the position of each IC device; The second etching submodule is used to etch the first deep hole on the first surface of the first wafer according to the position of the first deep hole.

[0061] In a possible implementation, the first metal material is one or more of copper, tungsten, ruthenium, and aluminum.

[0062] In a possible implementation manner, the diameter of the nano-through silicon via structure is 100 nm-1 um, and the depth is 1 um-10 um.

[0063] In a possible implementation manner, the depth of the first deep hole is 2-3 um.

[0064] In a possible implementation manner, the dielectric layer material is silicon oxide or silicon nitride.

[0065] In a possible implementation, the deposition conditions of the CVD chemical vapor deposition include: CVD raw material gas concentration and reaction temperature.

[0066] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0067] The embodiments of the present application are described with reference to the flowcharts and / or block diagrams of the methods, devices, electronic devices, and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0068] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0069] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0070] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present application.

[0071] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0072] The above is a detailed introduction to a method for preparing a nano-silicon via and a chip packaging structure provided by the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for a person skilled in the art, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A method for preparing nano-through silicon vias, characterized in that: The method comprises: Obtain a first wafer, and determine a first surface of the first wafer, where the first surface is a surface of the first wafer on which an IC process is to be performed; Preparing a first deep hole on the first surface of the first wafer by etching; By controlling the deposition conditions of CVD chemical vapor deposition, the first deep hole is partially filled with a dielectric layer material to obtain a second deep hole with a cavity; Performing an IC process on the first surface to prepare an IC device layer; Using a first metal material, a first metal layer is prepared on the surface of the IC device layer, so that the first metal layer and the IC device in the IC device layer are metal-connected, and the first metal layer covers the second deep hole; Thinning the second surface of the first wafer until the cavity of the second deep hole is exposed; The second deep hole is filled with the first metal material to obtain a nano-silicon via structure.

2. The method for preparing nano-through silicon vias according to claim 1, characterized in that: The method of filling the second deep hole with the first metal material to obtain a nano-silicon through-hole structure includes: Etching the dielectric layer material in the second deep hole until the first metal layer is exposed; The cavity of the second deep hole is filled with metal using the first metal material to obtain the nano-silicon via structure.

3. The method for preparing nano-through silicon vias according to claim 1, characterized in that: The method further comprises: A second metal layer is prepared on the second surface by using the first metal material, so that the second metal layer is connected to the first metal layer through the nano-silicon via structure.

4. The method for preparing nano-through silicon vias according to claim 1, characterized in that: The step of preparing a first deep hole on the first surface of the first wafer by etching comprises: Determining the position of each IC device in the IC process to be performed on the first surface of the first wafer; Determine the position of the first deep hole with the goal of not overlapping the position of each IC device; According to the position of the first deep hole, the first deep hole is etched on the first surface of the first wafer.

5. The method for preparing nano-through silicon vias according to claim 1, characterized in that: The first metal material is one or more of copper, tungsten, ruthenium and aluminum.

6. The method for preparing nano-through silicon vias according to claim 1, characterized in that: The nano-silicon through hole structure has a diameter of 100nm-1um and a depth of 1um-10um.

7. The method for preparing nano-through silicon vias according to claim 1, characterized in that: The depth of the first deep hole is 2-3 um.

8. The method for preparing nano-through silicon vias according to claim 1, characterized in that: The dielectric layer material is silicon oxide or silicon nitride.

9. The method for preparing nano-through silicon vias according to claim 1, characterized in that: The deposition conditions of the CVD chemical vapor deposition include: CVD raw material gas concentration and reaction temperature.

10. A chip packaging structure, characterized in that: The chip packaging structure includes a first wafer, wherein the first wafer includes a nano-through silicon via structure, and the nano-through silicon via structure is prepared by the nano-through silicon via preparation method according to any one of claims 1-9.

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