Method for manufacturing nanometer silicon through hole on silicon wafer with IC (integrated circuit) device and packaging structure

Abstract

The invention provides a method for manufacturing a nanometer silicon through hole in a silicon wafer with an IC device and a packaging structure, and relates to the technical field of semiconductors, and the method comprises the steps: obtaining a first silicon wafer, arranging an IC device on a first surface of the first silicon wafer through the execution of an IC technology, and forming an IC device layer; preparing a metal pad on the surface of the IC device layer; depositing and growing a dielectric layer on the IC device layer by using a dielectric layer material; preparing a first through hole in the growth dielectric layer, wherein the first through hole is located above the metal pad and is connected with the upper surface of the metal pad; preparing a first metal layer on the surface of the growth dielectric layer; a second through hole is formed in the second surface of the first silicon wafer, penetrates through the first silicon wafer and the IC device layer, is located below the metal pad and is connected with the lower surface of the metal pad; and preparing a second metal layer on the second surface to obtain the through-silicon-via structure.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method and a packaging structure for manufacturing nano-through silicon vias on a silicon wafer having an IC device. Background Art

[0002] Through Silicon Via technology is an important semiconductor advanced packaging technology that allows direct electrical connection between silicon wafers through vertical through holes, which can promote the development of integrated circuits to higher integration and smaller size, and meet the ever-increasing requirements for performance and power consumption. At present, the common method of through silicon via in packaging is to make the through silicon via separately on a wafer, and then connect it to the wafer containing logic or storage structure through bonding.

[0003] As the size of through silicon vias gradually decreases, the size of the through-holes and the size of the devices gradually approach each other, and the demand for interconnection increases. However, it is still difficult for existing technologies to make the process of through silicon vias compatible with the IC process and implement them on the same wafer. Summary of the invention

[0004] In view of the above problems, embodiments of the present application provide a method and a packaging structure for manufacturing nano-through silicon vias on a silicon wafer having an IC device, so as to overcome the above problems or at least partially solve the above problems.

[0005] According to a first aspect of an embodiment of the present application, a method for manufacturing a nano-through silicon via on a silicon wafer having an IC device is provided, the method comprising: Obtain a first silicon wafer, wherein one or more IC devices are arranged on a first surface of the first silicon wafer by performing an IC process to form an IC device layer; Using a first metal material to prepare a metal pad on the surface of the IC device layer; Depositing a growing dielectric layer on the IC device layer using a dielectric layer material; Preparing a first through hole filled with the first metal material in the growth medium layer, wherein the first through hole is located above the metal pad and connected to the upper surface of the metal pad; Using the first metal material, a first metal layer is prepared on the surface of the growth medium layer; A second through hole is prepared on the second surface of the first silicon wafer and passes through the first silicon wafer and the IC device layer, wherein the second through hole is located below the metal pad and connected to the lower surface of the metal pad; A second metal layer is prepared on the second surface using the first metal material to obtain a through silicon via structure.

[0006] In a possible implementation manner, preparing a first through hole filled with the first metal material in the growth medium layer includes: According to the position of the metal pad, a hole is punched on the surface of the growth medium layer until the surface of the metal pad at the bottom is exposed to obtain a through hole; Filling the first metal material into the through hole obtained by punching; Excess first metal material on the surface of the growth medium layer is removed to obtain the first through hole.

[0007] In a possible implementation manner, preparing a second through hole on the second surface of the first silicon wafer and passing through the first silicon wafer and the IC device layer includes: Etching a deep hole from the second surface of the first silicon wafer until the metal pad is exposed at the bottom of the deep hole; Filling the deep holes obtained by etching with the first metal material; The redundant first metal material on the second surface is removed to obtain the second through hole.

[0008] In a possible implementation, the first metal material is one or more of copper, tungsten, ruthenium, and aluminum.

[0009] In a possible implementation manner, the diameters of the first through hole and the second through hole are 100 nm-1 um.

[0010] In a possible implementation manner, the dielectric layer material is silicon oxide or silicon nitride.

[0011] In a possible implementation manner, the second through hole has a depth of 1 um-10 um.

[0012] The second aspect of the embodiment of the present application also provides a chip packaging structure, characterized in that the chip packaging structure includes a first silicon wafer, the first silicon wafer includes a through silicon via structure, and the through silicon via structure is prepared by the method for manufacturing nano-silicon vias on a silicon wafer with IC devices described in the first aspect of the embodiment of the present application.

[0013] The embodiment of the present application provides a method for manufacturing nano silicon vias on a silicon wafer with IC devices, the method comprising: obtaining a first silicon wafer, on the first surface of which one or more IC devices are provided by performing an IC process to form an IC device layer; preparing a metal pad on the surface of the IC device layer using a first metal material; depositing a growth medium layer on the IC device layer using a dielectric layer material; preparing a first through hole filled with the first metal material in the growth medium layer, the first through hole being located above the metal pad and connected to the upper surface of the metal pad; preparing a first metal layer on the surface of the growth medium layer using the first metal material; preparing a second through hole on the second surface of the first silicon wafer, passing through the first silicon wafer and the IC device layer, the second through hole being located below the metal pad and connected to the lower surface of the metal pad; preparing a second metal layer on the second surface using the first metal material to obtain a silicon via structure.

[0014] The method for preparing a through silicon via provided in the present application reserves a metal pad on the front side (i.e., the surface on the side of the silicon wafer on which the IC device is prepared), relies on photolithography for alignment, and punches a hole from the back side (i.e., the second surface) to connect to the reserved metal pad, thereby forming a metal through hole passing through the silicon wafer. The through hole is used to connect the first metal layer on the upper surface of the silicon wafer and the second metal layer on the lower surface of the silicon wafer, thereby achieving the adaptation of the processing of the through silicon via and the processing of the IC device on the same wafer, thereby improving the interconnection density and flexibility of wafer packaging. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments of the present application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0016] Figure 1 It is a flowchart of the steps of a method for manufacturing nano-silicon vias on a silicon wafer having an IC device provided in an embodiment of the present application; Figure 2 It is a structural schematic diagram of an IC device layer provided in an embodiment of the present application; Figure 3 is a structural schematic diagram of a metal pad provided in an embodiment of the present application; Figure 4 is a schematic structural diagram of a growth medium layer provided in an embodiment of the present application; Figure 5 is a schematic diagram of an intermediate structure of a first through hole provided in an embodiment of the present application; Figure 6 is a schematic structural diagram of a first through hole provided in an embodiment of the present application; Figure 7 is a schematic structural diagram of a first metal layer provided in an embodiment of the present application; Figure 8 is a schematic diagram of an intermediate structure of a second through hole provided in an embodiment of the present application; Fig. 9 is a schematic structural diagram of a second through hole provided in an embodiment of the present application; Fig.10 is a schematic diagram of the structure of a through silicon via provided in an embodiment of the present application; Fig.11 It is a structural schematic diagram of a through silicon via preparation device provided in an embodiment of the present application; Description of the drawings: first silicon wafer 100 , IC device layer 101 , metal pad 102 , growth medium layer 103 , first through hole 104 , first metal layer 105 , second through hole 106 , second metal layer 107 . DETAILED DESCRIPTION

[0017] The exemplary embodiments of the present application will be described in more detail below in conjunction with the accompanying drawings in the embodiments of the present application. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present application and to enable the scope of the present application to be fully communicated to those skilled in the art.

[0018] Nano-Through-Silicon-Via (nTSV) is a nano-scale through-hole that penetrates the silicon wafer and is filled with metal. TSV technology is an important advanced semiconductor packaging technology that allows direct electrical connection between silicon wafers through vertical through-holes, which can promote the development of integrated circuits to higher integration and smaller size, meeting the requirements for increasing performance and power consumption.

[0019] Through silicon vias have been widely used in advanced packaging, but the aperture is generally between tens and hundreds of microns, and the density is low. In addition, the common method of through silicon vias in packaging is to make the through silicon vias separately on a wafer, and then connect it to the wafer containing logic or storage structures through bonding.

[0020] The small size of nano-silicon vias has a density advantage, which can form a higher interconnection density per unit area, and thus has a higher practical value. In addition, as the size of silicon vias is gradually reduced to the sub-micron scale, the size of the vias is gradually approaching the size of the device, and nano-silicon vias can be connected to structures as small as a few devices, greatly improving the interconnection density and flexibility. However, the existing technology still finds it difficult to make the silicon via process compatible with the IC process and implement it on the same wafer.

[0021] In view of the above problems, the embodiment of the present application proposes a method and packaging structure for manufacturing nano-through silicon vias on a silicon wafer with an IC device, so as to make the through silicon via process compatible with the IC process and implemented on the same wafer. In combination with the accompanying drawings, the method for manufacturing nano-through silicon vias on a silicon wafer with an IC device provided by the embodiment of the present application is described in detail through some embodiments and their application scenarios.

[0022] The first aspect of the present application provides a method for manufacturing nano-silicon vias on a silicon wafer having an IC device, referring to Figure 1 , Figure 1 A flowchart of a method for manufacturing nano-silicon vias on a silicon wafer having an IC device is provided in an embodiment of the present application, such as Figure 1 As shown, the method includes: Step S101 , obtaining a first silicon wafer, on a first surface of which one or more IC devices are provided by performing an IC process to form an IC device layer.

[0023] Specifically, the first silicon wafer has two upper and lower surfaces, namely, a first surface and a second surface, and the first surface is a surface on which the IC process is performed on the first silicon wafer and one or more IC devices are provided. The IC process refers to a process flow in which the first silicon wafer is subjected to multi-step processing so that one or more IC devices are embedded inside or on the surface of the wafer, and electrical connections are achieved in a subsequent packaging process or in a bonded stacking structure formed by multiple wafers. In different application scenarios, the IC process performed on the silicon wafer is different, and the IC devices involved are different. In this embodiment, the IC process is not specifically limited.

[0024] In a possible implementation, the method further includes: performing an IC process on the first surface to prepare an IC device layer.

[0025] In the embodiment of the present application, the specific scheme of the IC process is not limited. The IC process may include embedding the chip in the buried groove after etching, or using a dual damascene wiring process to prepare one or more metal interconnect structures. Figure 2 , Figure 2 A schematic diagram of the structure of an IC device layer is shown. Figure 2As shown, different IC processes may ultimately result in different structures. There may be IC devices (such as chips, metal interconnect structures, etc.) embedded in the first wafer, or there may be IC devices and related dielectric materials fixed on the first surface of the first wafer. In the embodiment of the present application, they may be uniformly represented as a hierarchical structure, namely, the IC device layer 101.

[0026] Step S102: preparing a metal pad on the surface of the IC device layer using a first metal material.

[0027] Reference Figure 3 , Figure 3 A schematic diagram of the structure of a metal pad is shown. Figure 3 As shown, the metal pad 102 is located on the upper surface of the IC device layer (the surface away from the first surface). The shape and position of the metal pad can be determined according to the actual process requirements and are not limited in the embodiments of the present application. The metal pad is used to connect the first through hole (corresponding to the first metal layer on the upper surface of the first silicon wafer) and the second through hole (corresponding to the second metal layer on the lower surface of the first silicon wafer), so the metal pad can also be connected to one or more IC devices in the IC device layer (which need to be metal-connected to the silicon through hole structure). Since it is necessary to prepare a second through hole below the metal pad in the subsequent steps, the position reserved for the second through hole needs to be considered when determining the position of the metal pad. That is, the position of the metal pad cannot completely overlap with the position of each IC device in the IC device layer. If the two overlap, the IC device will be damaged when etching the second through hole.

[0028] In a possible implementation, the first metal material is one or more of copper, tungsten, ruthenium, and aluminum.

[0029] In a possible implementation manner, the step S102, preparing a metal pad on the surface of the IC device layer using a first metal material, includes: Step S1021, determining the positions of the various IC devices in the IC device layer, and the positions of the candidate IC devices that need to be connected to the through silicon via structure.

[0030] Step S1022 , determining the position of the metal pad with the goal of making the position of the metal pad contact and connect with the position of the candidate IC device but not overlapping.

[0031] Step S1023: preparing the metal pad on the first surface according to the position of the metal pad.

[0032] In this embodiment, according to the IC process to be performed, the positions of the various IC devices involved on the first surface are determined, such as the position of the chip, the position of the metal interconnection structure, etc. The position of the metal pad is determined with the goal that the position of the metal pad does not overlap with the position of each IC device and contacts the candidate IC device, and then the metal pad is prepared.

[0033] Step S103 , depositing a dielectric layer on the IC device layer using a dielectric layer material.

[0034] Specifically, a CVD chemical vapor deposition method can be used to deposit a dielectric layer material on the IC device layer to obtain a grown dielectric layer. Figure 4 , Figure 4 A schematic diagram of the structure of a growth medium layer is shown. Figure 4 As shown, the thickness of the growth medium layer 103 needs to be greater than the thickness of the metal pad 102, and considering that the first through hole needs to be prepared in the growth medium layer later, the growth medium layer 103 prepared in this step needs to be high enough, that is, the thickness of the growth medium layer 103 needs to be greater than or equal to the sum of the thickness of the metal pad 102 and the thickness of the first through hole. In a possible implementation, the dielectric layer material is silicon oxide or silicon nitride.

[0035] Step S104 , preparing a first through hole filled with the first metal material in the growth medium layer, wherein the first through hole is located above the metal pad and connected to the upper surface of the metal pad.

[0036] In a possible implementation manner, the step S104 of preparing a first through hole filled with the first metal material in the growth medium layer includes: Step S1041 , drilling a hole on the surface of the growth medium layer according to the position of the metal pad until the surface of the bottom metal pad is exposed to obtain a through hole.

[0037] Reference Figure 5 , Figure 5 A schematic diagram of the intermediate structure of a first through hole is shown, such as Figure 5As shown, according to the size of the silicon through hole to be prepared, a through hole is prepared on the surface of the growth medium layer 103 (can be etched). Among them, the position of the through hole (that is, the position of the first through hole) needs to correspond to the position of the metal pad. Optionally, the diameter of the through hole is 100nm-1um. The depth of the through hole is 1um-10um. In this step, the depth of the prepared through hole can be the same as the thickness of the growth medium layer. Optionally, the first metal material is one or more of copper, tungsten, ruthenium, and aluminum. The first metal material used in step S1041 is the same as the first metal material used in step S102.

[0038] Step S1042, filling the first metal material into the through hole obtained by drilling.

[0039] Step S1043 , removing excess first metal material on the surface of the growth medium layer to obtain the first through hole.

[0040] Reference Figure 6 , Figure 6 A schematic diagram of the structure of a first through hole is shown, such as Figure 6 As shown, the first metal material is filled in the through hole prepared in the growth medium layer, and then the excess first metal material on the surface of the growth medium layer is removed to keep the surface of the growth medium layer smooth and flat, thereby preparing one or more first through holes 104. That is, the position of the first through hole corresponds to the position of the metal pad one by one, so that the first through hole is metal-connected to the corresponding IC device in the IC device layer through the metal pad. Optionally, the diameter of the first through hole is 100nm-1um. The depth of the first through hole is 1um-10um. In this step, the depth of the prepared first through hole 104 can be the same as the thickness of the growth medium layer 103.

[0041] Step S105 : using the first metal material to prepare a first metal layer on the surface of the growth medium layer.

[0042] A first metal layer is prepared on the surface of the growth medium layer using a first metal material, so that the first metal layer and the IC device in the IC device layer are metal-connected through a first through hole and a metal pad, and the first metal layer covers the first through hole. In the embodiment of the present application, the first metal layer may include metal interconnect structures of different shapes. The specific structure and preparation method of the first metal layer will vary with the changes in the IC process, and will be designed according to actual process requirements, and will not be limited in the embodiment of the present application. Figure 7 , Figure 7 A schematic diagram of the structure of a first metal layer is shown, such as Figure 7As shown, the first metal layer may contain a metal structure connected to the first through hole, or may contain a related dielectric material that plays a fixing or filling role. The connection between the first metal layer and the first through hole does not destroy the original structure of the first through hole, which means that the metal component in the first metal layer covers the top of the first through hole. In the embodiment of the present application, it can be uniformly represented as a hierarchical structure located above the growth medium layer, that is, the first metal layer 105. Optionally, the first metal material is one or more of copper, tungsten, ruthenium, and aluminum.

[0043] Step S106, preparing a second through hole on the second surface of the first silicon wafer, passing through the first silicon wafer and the IC device layer, wherein the second through hole is located below the metal pad and connected to the lower surface of the metal pad.

[0044] In a possible implementation manner, step S106, preparing on the second surface of the first silicon wafer a second through hole passing through the first silicon wafer and the IC device layer, includes: Step S1061, etching a deep hole from the second surface of the first silicon wafer until the metal pad is exposed at the bottom of the deep hole.

[0045] Reference Figure 8 , Figure 8 A schematic diagram of the intermediate structure of a second through hole is shown, such as Figure 8 As shown, etching is performed from the back side (i.e., the second surface) of the first silicon wafer, so that the etched deep hole passes through the first silicon wafer and the IC device layer on the first surface of the first silicon wafer, until the bottom of the etched deep hole exposes the lower surface of the metal pad (i.e., the surface where the metal pad contacts the IC device layer). Among them, the position of the deep hole (i.e., the position of the second through hole) needs to correspond to the position of the metal pad one by one. In this embodiment, position alignment can be achieved by using photolithography technology, which reduces the process difficulty. In addition, the position of the deep hole also needs to avoid the various IC devices in the IC device layer to avoid damaging the IC device during etching. Optionally, the diameter of the deep hole is 100nm-1um. The depth of the deep hole is 1um-10um.

[0046] Step S1062: Fill the deep holes obtained by etching with the first metal material.

[0047] Step S1063, removing excess first metal material on the second surface to obtain the second through hole.

[0048] Reference Fig. 9 , Fig. 9 A schematic diagram of the structure of a second through hole is shown, such as Fig. 9As shown, the first metal material is filled into the deep hole obtained by etching from the back side (second surface) of the first silicon wafer, and then the excess first metal material on the second surface is removed to keep the second surface smooth and flat, thereby preparing one or more second through holes 106. That is, the position of the second through hole 106 corresponds to the position of the metal pad 102 one by one, so that the second through hole is metal-connected to the corresponding IC device in the IC device layer through the metal pad. The first through hole and the second through hole are connected through the metal pad.

[0049] In a possible implementation manner, the diameters of the first through hole and the second through hole are 100 nm-1 um.

[0050] In a possible implementation manner, the second through hole has a depth of 1 um-10 um.

[0051] Step S107 , using the first metal material to prepare a second metal layer on the second surface to obtain a through silicon via structure.

[0052] Reference Fig.10 , Fig.10 A schematic diagram of the structure of a through silicon via is shown in FIG. Fig.10 As shown, in this embodiment, the second metal layer 107 is further prepared on the second surface, so that the upper surface (the first metal layer on the first surface) and the lower surface (the second metal layer on the second surface) of the first silicon wafer can be connected through the processed silicon via structure (first via-metal pad-second via), forming a connection channel from the front metal layer to the back metal layer that runs through the silicon wafer. When preparing the second metal layer, the same first metal material as the first metal layer and the silicon via structure can be used, and the first metal material can be one or more of copper, tungsten, ruthenium, and aluminum.

[0053] In the embodiment of the present application, the second metal layer 107 may include metal interconnect structures of different shapes. The specific structure and preparation method of the second metal layer are designed according to the actual process requirements and are not limited in the embodiment of the present application. The connection between the second metal layer and the through silicon via structure (the second through hole in the through silicon via structure) does not destroy the original structure of the through silicon via, which means that the metal component in the second metal layer covers the bottom of the second through hole 106. In the embodiment of the present application, it can be uniformly represented as a hierarchical structure located on the second surface of the first silicon wafer, that is, the second metal layer 107, completing the through silicon via processing from the front metal layer to the back metal layer.

[0054] The silicon through hole preparation method provided in the present application reserves a metal pad on the front side (i.e., the surface on the side of the silicon wafer where the IC device is prepared), relies on photolithography for alignment, and punches a hole from the back side (i.e., the second surface) to connect to the reserved metal pad, thereby forming a metal through hole passing through the silicon wafer, and using the through hole to connect the first metal layer on the upper surface of the silicon wafer and the second metal layer on the lower surface of the silicon wafer, so as to achieve the adaptation of the silicon through hole processing and IC device processing to the same wafer, thereby improving the interconnection density and flexibility of wafer packaging. In addition, the solution of leaving holes for the silicon through hole structure does not require high-precision photolithography alignment.

[0055] The second aspect of the embodiment of the present application also provides a chip packaging structure, which includes a first silicon wafer, wherein the first silicon wafer includes a through silicon via structure, and the through silicon via structure is prepared by the method for manufacturing nano-silicon vias on a silicon wafer with an IC device described in the first aspect of the embodiment of the present application.

[0056] Specifically, the chip packaging structure is as follows Fig.10 As shown, the chip packaging structure includes: a first silicon wafer 100, an IC device layer 101, a metal pad 102, a growth medium layer 103, a first through hole 104, a first metal layer 105, a second through hole 106, and a second metal layer 107. Among them, the first metal layer 105 and the second metal layer 107 are connected through a silicon through hole structure, and the silicon through hole structure includes: a first through hole 104, a metal pad 102 and a second through hole 106. The IC device in the IC device layer 101 is connected to the metal pad 102, and thus connected to the silicon through hole structure. Among them, the specific structure of the IC device layer is determined by the specific IC process, and the structure of the IC device layer is not limited in this embodiment. Exemplarily, the IC device layer may include a plurality of chips embedded in the buried groove, a metal pad connected to the chip, and a dielectric layer material that plays a fixing and filling role. Correspondingly, in this embodiment, the specific structure of the first metal layer and the second metal layer is not limited, as long as the first metal layer and the second metal layer include: a metal interconnect structure connected to the silicon through hole structure.

[0057] The third aspect of the embodiment of the present application provides a through silicon via preparation device, which is used to perform the steps of the method for manufacturing nano through silicon vias on a silicon wafer with an IC device provided in the first aspect, referring to Fig.11 , Fig.11 A schematic diagram of the structure of a through silicon via preparation device is shown. Fig.11 As shown, the device comprises: A silicon wafer acquisition module, used for acquiring a first silicon wafer, on a first surface of which one or more IC devices are arranged by performing an IC process to form an IC device layer; A metal pad preparation module, used for preparing a metal pad on the surface of the IC device layer using a first metal material; A growth medium layer preparation module, used for depositing a growth medium layer on the IC device layer using a medium layer material; a first through-hole preparation module, used for preparing a first through-hole filled with the first metal material in the growth medium layer, wherein the first through-hole is located above the metal pad and connected to the upper surface of the metal pad; A first metal layer preparation module, used for preparing a first metal layer on the surface of the growth medium layer using the first metal material; A second through-hole preparation module is used to prepare, on the second surface of the first silicon wafer, a second through-hole passing through the first silicon wafer and the IC device layer, wherein the second through-hole is located below the metal pad and connected to the lower surface of the metal pad; The second metal layer preparation module is used to prepare a second metal layer on the second surface using the first metal material to obtain a through silicon via structure.

[0058] In a possible implementation manner, preparing a first through hole filled with the first metal material in the growth medium layer includes: According to the position of the metal pad, a hole is punched on the surface of the growth medium layer until the surface of the metal pad at the bottom is exposed to obtain a through hole; Filling the first metal material into the through hole obtained by punching; Excess first metal material on the surface of the growth medium layer is removed to obtain the first through hole.

[0059] In a possible implementation manner, preparing a second through hole on the second surface of the first silicon wafer and passing through the first silicon wafer and the IC device layer includes: Etching a deep hole from the second surface of the first silicon wafer until the metal pad is exposed at the bottom of the deep hole; Filling the deep holes obtained by etching with the first metal material; The redundant first metal material on the second surface is removed to obtain the second through hole.

[0060] In a possible implementation, the first metal material is one or more of copper, tungsten, ruthenium, and aluminum.

[0061] In a possible implementation manner, the diameters of the first through hole and the second through hole are 100 nm-1 um.

[0062] In a possible implementation manner, the dielectric layer material is silicon oxide or silicon nitride.

[0063] In a possible implementation manner, the second through hole has a depth of 1 um-10 um.

[0064] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0065] The embodiments of the present application are described with reference to the flowcharts and / or block diagrams of the methods, devices, electronic devices, and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0066] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0067] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0068] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present application.

[0069] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0070] The above is a detailed introduction to a method and packaging structure for manufacturing nano-silicon vias on a silicon wafer with IC devices provided by the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for general technicians in this field, according to the ideas of the present application, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A method for manufacturing nano-through silicon vias on a silicon wafer having an IC device, characterized in that: The method comprises: Obtain a first silicon wafer, wherein one or more IC devices are arranged on a first surface of the first silicon wafer by performing an IC process to form an IC device layer; Using a first metal material to prepare a metal pad on the surface of the IC device layer; Depositing a growing dielectric layer on the IC device layer using a dielectric layer material; Preparing a first through hole filled with the first metal material in the growth medium layer, wherein the first through hole is located above the metal pad and connected to the upper surface of the metal pad; Using the first metal material, a first metal layer is prepared on the surface of the growth medium layer; A second through hole is prepared on the second surface of the first silicon wafer and passes through the first silicon wafer and the IC device layer, wherein the second through hole is located below the metal pad and connected to the lower surface of the metal pad; A second metal layer is prepared on the second surface using the first metal material to obtain a through silicon via structure.

2. The method for manufacturing nano-through silicon vias on a silicon wafer having an IC device according to claim 1, characterized in that: The step of preparing a first through hole filled with the first metal material in the growth medium layer comprises: According to the position of the metal pad, a hole is punched on the surface of the growth medium layer until the surface of the metal pad at the bottom is exposed to obtain a through hole; Filling the first metal material into the through hole obtained by punching; Excess first metal material on the surface of the growth medium layer is removed to obtain the first through hole.

3. The method for manufacturing nano-through silicon vias on a silicon wafer having an IC device according to claim 1, characterized in that: A second through hole is prepared on the second surface of the first silicon wafer and passes through the first silicon wafer and the IC device layer, comprising: Etching a deep hole from the second surface of the first silicon wafer until the metal pad is exposed at the bottom of the deep hole; Filling the deep holes obtained by etching with the first metal material; The redundant first metal material on the second surface is removed to obtain the second through hole.

4. The method for manufacturing nano-through silicon vias on a silicon wafer having an IC device according to claim 1, characterized in that: The first metal material is one or more of copper, tungsten, ruthenium and aluminum.

5. The method for manufacturing nano-through silicon vias on a silicon wafer having an IC device according to claim 1, characterized in that: The diameters of the first through hole and the second through hole are 100 nm-1 um.

6. The method for manufacturing nano-through silicon vias on a silicon wafer having an IC device according to claim 1, characterized in that: The dielectric layer material is silicon oxide or silicon nitride.

7. The method for manufacturing nano-through silicon vias on a silicon wafer of an IC device according to claim 1, characterized in that: The second through hole has a depth of 1 um-10 um.

8. A chip packaging structure, characterized in that: The chip packaging structure includes a first silicon wafer, wherein the first silicon wafer includes a through silicon via structure, and the through silicon via structure is prepared by the method for manufacturing nano through silicon vias on a silicon wafer with an IC device according to any one of claims 1-7.

Images