Signal period determination method and device, equipment, medium and program product

Abstract

The embodiment of the invention discloses a signal period determination method and device, equipment, a medium and a program product. Comprising the following steps: acquiring a to-be-measured signal, a basic clock signal, a frequency increasing multiple and a split-phase number; performing frequency multiplication and phase splitting processing on the basic clock signal according to the frequency multiplication multiple and the phase splitting number to obtain a plurality of frequency multiplication phase splitting clock signals; sampling the to-be-measured signal for at least two periods through the basic clock signal and each frequency multiplication phase-splitting clock signal, and determining a counting result corresponding to each period; and determining the signal period of the to-be-detected signal according to each counting result. As the sampling times are greatly increased, the precision and accuracy of periodic measurement of the to-be-measured signal are improved, and the shooting stability of an industrial camera triggered according to the to-be-measured signal is further improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor device precision measurement technology, and in particular to a signal period determination method, device, equipment, medium and program product. Background Art

[0002] With the continuous advancement of science and technology, the application of semiconductor equipment in high-tech fields such as electronics, communications, and computers has become increasingly important, and has also had a significant impact on many other industries. In semiconductor equipment, industrial cameras are key imaging components, and their performance is directly related to the overall working effect and product quality of the equipment. Based on the working principle of industrial cameras, the stability of the trigger signal used to trigger the industrial camera for shooting is crucial to ensure the clarity of the image. Since the allowable fluctuation range of the trigger signal is usually relatively small, about 0.5% of the average period of the trigger signal, the accuracy of the trigger signal has also become an important factor affecting the shooting stability of industrial cameras.

[0003] At present, there are two main methods for measuring the trigger signal of industrial cameras: one is to observe with an oscilloscope, but the cost of high-quality oscilloscopes is high, and the functions of oscilloscopes do not cover the statistical requirements for the trigger signal period; the other is to sample the signal through a field programmable gate array (FPGA) to determine the period of the trigger signal and analyze the stability of the trigger signal accordingly. However, the traditional counter counting method used in FPGA will introduce a certain degree of systematic error when counting the signal period, which makes it difficult to meet the accuracy measurement requirements of high-precision trigger signals. Summary of the invention

[0004] The present invention provides a signal period determination method, apparatus, device, medium and program product, which perform higher density sampling on the signal required for period measurement when FPGA performance permits, reduce the influence of FPGA sampling clock period on counting period, improve the resolution and accuracy of time measurement, and improve the accuracy and precision of signal period measurement.

[0005] In a first aspect, an embodiment of the present invention provides a method for determining a signal period, comprising:

[0006] Obtain the signal to be tested, the basic clock signal, the frequency multiplication factor and the number of phase divisions;

[0007] The basic clock signal is multiplied and phase-split according to the frequency multiplication factor and the phase-split number to obtain a multiplied and phase-split clock signal with the number of phase-splits;

[0008] The signal to be measured is sampled for at least two cycles respectively by using the basic clock signal and each frequency-multiplied phase-splitting clock signal to determine the counting result corresponding to each cycle;

[0009] The signal period of the signal to be measured is determined according to each counting result.

[0010] In a second aspect, an embodiment of the present invention further provides a signal period determination device, comprising:

[0011] An information acquisition module is used to obtain the signal to be tested, the basic clock signal, the frequency increase multiple and the phase division number;

[0012] The clock determination module is used to perform frequency multiplication and phase division processing on the basic clock signal according to the frequency multiplication factor and the phase division number to obtain a frequency multiplication and phase division clock signal with a number of phase divisions;

[0013] A counting result determination module is used to sample the signal to be measured for at least two cycles using the basic clock signal and each frequency-multiplied phase-splitting clock signal, and determine the counting result corresponding to each cycle;

[0014] The signal period determination module is used to determine the signal period of the signal to be measured according to each counting result.

[0015] In a third aspect, an embodiment of the present invention further provides a signal period determination device, including:

[0016] at least one processor; and a memory communicatively coupled to the at least one processor;

[0017] The memory stores a programmable program that can be executed by at least one processor, and the programmable program is executed by at least one processor so that the at least one processor can implement the signal period determination method of any embodiment of the present invention.

[0018] In a fourth aspect, an embodiment of the present invention further provides a storage medium comprising executable instructions, and the executable instructions, when executed by a programmable processor, are used to execute the signal period determination method of any embodiment of the present invention.

[0019] In a fifth aspect, an embodiment of the present invention further provides a program product, including a programmable program, which, when executed by a processor, is used to execute the signal period determination method of any embodiment of the present invention.

[0020] The embodiments of the present invention provide a method, device, equipment, medium and program product for determining a signal period, which obtains a signal to be measured, a basic clock signal, a frequency increase multiple and a phase number; performs frequency multiplication and phase splitting processing on the basic clock signal according to the frequency increase multiple and the phase splitting number to obtain a frequency-multiplied and phase-split clock signal with a number of phase splits; samples the signal to be measured for at least two periods respectively using the basic clock signal and each frequency-multiplied and phase-split clock signal to determine a counting result corresponding to each period; and determines the signal period of the signal to be measured according to each counting result. By adopting the above technical solution, before counting and sampling the signal to be measured, the basic clock signal used for traditional counting is first multiplied and phase-split based on the obtained frequency increase multiple and phase split number. The frequency multiplication process can increase the frequency of the basic clock signal, and the phase split process can delay the clock signal after the frequency multiplication with an equal phase difference to obtain a frequency-multiplied and phase-split clock signal after several frequency multiplications. Then, when the signal to be measured is sampled by each frequency-multiplied and phase-split clock signal, it is equivalent to sampling the original basic clock signal once while sampling the frequency increase multiple multiplied by the phase split number to obtain a counting result corresponding to the period of the signal to be measured. Due to the substantial increase in the number of sampling times, the precision and accuracy of the measurement of the period of the signal to be measured are improved, thereby improving the shooting stability of the industrial camera triggered by the signal to be measured.

[0021] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0023] Figure 1 A flowchart of a method for determining a signal period provided in Embodiment 1 of the present invention;

[0024] Figure 2 A flowchart of a method for determining a signal period provided in Embodiment 2 of the present invention;

[0025] Figure 3 A timing diagram of a frequency-multiplied phase-split clock signal provided in the second embodiment of the present invention;

[0026] Figure 4 An example diagram of sampling timing of a signal to be tested and each clock signal provided in the second embodiment of the present invention;

[0027] Figure 5 A flowchart of a method for sampling a signal to be tested for at least two cycles by using each frequency-multiplied phase-splitting clock signal to determine a fine count value corresponding to each cycle, provided in the second embodiment of the present invention;

[0028] Figure 6 A diagram showing an example of a structure of a cache register corresponding to each frequency-multiplied phase-split clock signal provided in the second embodiment of the present invention;

[0029] Figure 7 An output example diagram of a cache register corresponding to each frequency-multiplied phase-split clock signal provided in the second embodiment of the present invention;

[0030] Figure 8 An output example diagram of a cache register when reading encoded data provided by the second embodiment of the present invention;

[0031] Fig. 9 A schematic diagram of the structure of a signal period determination device provided in Embodiment 3 of the present invention;

[0032] Fig.10 A schematic diagram of the structure of a signal period determination device provided in Embodiment 4 of the present invention. DETAILED DESCRIPTION

[0033] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0034] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0035] Embodiment 1

[0036] Figure 1A flowchart of a signal period determination method provided in the first embodiment of the present invention. The embodiment of the present invention can be applied to the case of high-precision detection of the period of a trigger signal used to trigger an industrial camera to shoot. The signal period determination method can be executed by a signal period determination device, which can be implemented by software and / or hardware, and the signal period determination device can be configured in a signal period determination device. The optional signal period determination device can be an electronic device, which can be a notebook, a desktop computer, a smart tablet, a programmable device, etc., and the embodiment of the present invention does not limit this.

[0037] like Figure 1 As shown, a method for determining a signal period provided by an embodiment of the present invention specifically includes the following steps:

[0038] S101, obtaining a signal to be tested, a basic clock signal, a frequency multiplication factor and a phase division number.

[0039] In the present embodiment, the signal to be measured can be specifically understood as a signal that needs to be measured for a signal period. For example, the signal to be measured can be a trigger signal for triggering an industrial camera to take pictures. The basic clock signal can be specifically understood as a synchronous pulse signal provided for the circuit in the electronic circuit to ensure that each part of the circuit can operate according to the timing. For example, the basic clock signal can be a clock signal provided by the clock source in the FPGA to synchronize the logic operation and data transmission inside the FPGA. The frequency increase multiple can be specifically understood as a multiple value corresponding to an integer multiple of its original frequency. The phase division number can be specifically understood as a number of signals with different phases that are divided into multiple parts or phase intervals.

[0040] Specifically, when it is necessary to determine the period of a certain signal, the signal to be tested whose period needs to be determined will be obtained first. At the same time, before determining the period of the signal to be tested, a basic clock signal for triggering the sampling of the signal to be tested will be obtained, as well as a frequency multiplier and phase division number for processing the basic clock signal to increase the sampling frequency of the signal to be tested.

[0041] S102, performing frequency multiplication and phase splitting processing on the basic clock signal according to the frequency multiplication factor and the phase splitting number, to obtain a frequency multiplied and phase splitting clock signal with the number of phase splittings.

[0042] Specifically, the basic clock signal is first multiplied according to the frequency increase multiple, so that the frequency of the basic clock signal is increased to the frequency increase multiple of the original frequency. Then, the clock signal after the frequency increase is subjected to phase splitting, that is, the clock signal after the frequency increase is subjected to multiple phase delay processing according to the phase splitting number, and a multiplied phase splitting clock signal can be obtained after each phase delay processing, and together with the multiplied phase splitting clock signal with zero phase delay, a multiplied phase splitting clock signal with multiple phase splitting is formed.

[0043] S103 , sampling the signal to be measured for at least two cycles using the basic clock signal and each frequency-multiplied phase-splitting clock signal, and determining a counting result corresponding to each cycle.

[0044] Specifically, in order to more accurately determine the period of the signal to be measured, it is necessary to sample the signal to be measured for at least two periods, so as to jointly determine the accurate signal period of the signal to be measured based on the results of multi-period sampling. When sampling each period of the signal to be measured, the basic clock signal of the FPGA itself can be used to perform low-frequency sampling using the traditional counter counting method, and at the same time, the signal to be measured can be sampled at a high frequency using each multiplied and phase-split clock signal after multiplication and phase splitting, and the results obtained by sampling the basic clock signal and each multiplied and phase-split clock signal in one period are jointly determined as the counting result corresponding to the period.

[0045] S104, determining the signal period of the signal to be measured according to each counting result.

[0046] Specifically, since the sampling results obtained by the basic clock signal in each counting result can roughly count the signal period of the signal to be measured, and the sampling results obtained by each frequency-multiplied phase-splitting clock signal in each counting result can count the signal period of the signal to be measured with high precision, the rough signal period of the signal to be measured can be determined from the coarse-grained angle corresponding to the basic clock signal according to the counting results obtained by sampling adjacent periods, and the fine-resolution signal period of the signal to be measured can be determined from the fine-grained angle corresponding to the frequency-multiplied phase-splitting clock signal, and the two can be combined to comprehensively determine the signal period of the signal to be measured.

[0047] The technical solution of this embodiment is to obtain a signal to be measured, a basic clock signal, a frequency increase multiple and a phase number; perform frequency multiplication and phase splitting processing on the basic clock signal according to the frequency increase multiple and the phase splitting number to obtain a number of frequency-multiplied and phase-split clock signals; sample the signal to be measured using the basic clock signal and each frequency-multiplied and phase-split clock signal for at least two cycles respectively to determine the counting result corresponding to each cycle; and determine the signal period of the signal to be measured based on each counting result. By adopting the above technical solution, before counting and sampling the signal to be measured, the basic clock signal used for traditional counting is first multiplied and phase-split based on the obtained frequency increase multiple and phase split number. The frequency multiplication process can increase the frequency of the basic clock signal, and the phase split process can delay the clock signal after the frequency multiplication with an equal phase difference to obtain a frequency-multiplied and phase-split clock signal after several frequency multiplications. Then, when the signal to be measured is sampled by each frequency-multiplied and phase-split clock signal, it is equivalent to sampling the original basic clock signal once while sampling the frequency increase multiple multiplied by the phase split number to obtain a counting result corresponding to the period of the signal to be measured. Due to the substantial increase in the number of sampling times, the precision and accuracy of the measurement of the period of the signal to be measured are improved, thereby improving the shooting stability of the industrial camera triggered by the signal to be measured.

[0048] Embodiment 2

[0049] Figure 2 A flow chart of a signal period determination method provided for Embodiment 2 of the present invention. The embodiment of the present invention is further optimized on the basis of the above-mentioned optional technical solutions. After the basic clock signal is multiplied according to the frequency increase factor, the multiplied clock signal obtained by the multiplication processing is equally divided into phases according to the number of phase divisions, so that the multiplied phase-divided clock signals obtained by the phase divisions have the same delayed phase difference, and then the signal to be measured is sampled for at least two cycles using the basic clock signal and each multiplied phase-divided clock signal respectively, the result obtained by sampling the basic clock signal is determined as a coarse count value, and the result obtained by sampling each multiplied phase-divided clock signal is determined as a fine count value, the counting result for the signal to be measured is determined from both coarse and fine dimensions, and then the signal period of the signal to be measured is comprehensively determined based on the counting results in the two dimensions. Among them, when determining the fine count value, the preset coding area is divided in the register corresponding to each multiplied phase clock signal to complete the accurate reading of the coding data related to the fine count value, thereby improving the accuracy of the fine count value determination, and further improving the accuracy of the signal period determined based on the fine count value and the coarse count value. The precision and accuracy of the measurement of the signal period to be measured are improved, thereby improving the shooting stability of the industrial camera triggered by the signal to be measured.

[0050] like Figure 2 As shown, a method for determining a signal period provided by an embodiment of the present invention specifically includes the following steps:

[0051] S201, obtaining a signal to be tested, a basic clock signal, a frequency multiplication factor and a phase division number.

[0052] S202: Perform frequency multiplication processing on the basic clock signal according to the frequency increase factor to determine a frequency multiplied clock signal.

[0053] Specifically, after obtaining the basic clock signal, the frequency of the basic clock signal can be determined, and then the frequency multiplier corresponding to the frequency increase multiple can be determined based on the frequency increase multiple, and the basic clock signal is input into the frequency multiplier for frequency amplification, so that the frequency of the basic clock signal becomes the frequency increase multiple of the original frequency, and the resulting signal is determined as the multiplied clock signal.

[0054] For example, assuming that the basic clock signal is CLK, its frequency is M, and the frequency multiplier is L, then an L multiplier can be constructed. After CLK is input into the L multiplier, a clock signal C0 is obtained. The frequency of C0 is ML, that is, C0 is the multiplied clock signal corresponding to the basic clock signal.

[0055] S203, performing equal phase division processing on the frequency-multiplied clock signal according to the phase division number to obtain the frequency-multiplied phase division clock signals with the number of phase divisions.

[0056] The delayed phase difference between two adjacent frequency-multiplied phase-splitting clock signals is the same; the delayed phase difference is the ratio of 360 degrees to the number of phase divisions.

[0057] Specifically, after obtaining the number of phase divisions, the ratio of 360 degrees to the number of phase divisions is determined as the delayed phase difference that needs to be distinguished between two adjacent clock signals during the phase division process, and then the frequency-multiplied clock signal is equally divided and phase-divided according to the delayed phase difference to obtain a number of frequency-multiplied phase-divided clock signals. In other words, the undelayed frequency-multiplied clock signal can be used as a frequency-multiplied phase-divided clock signal, and then the frequency-multiplied clock signal is delayed by the delayed phase difference as a new frequency-multiplied phase-divided clock signal, and then the delayed frequency-multiplied phase-divided clock signal is further delayed by the delayed phase difference as a new frequency-multiplied phase-divided clock signal, and so on, until a number of frequency-multiplied phase-divided clock signals are obtained.

[0058] Continuing with the above example, Figure 3 A timing diagram of a frequency-multiplied phase-splitting clock signal provided in the second embodiment of the present invention is shown in FIG. Figure 3 As shown, assuming that the phase division number n=4, the doubled clock signal C0 is equally divided into phases, and the corresponding delayed phase difference is 90 degrees. That is, after the phase division processing, the doubled clock signal C0 with a delay of 0 degrees, the doubled clock signal C90 with a delay of 90 degrees, the doubled clock signal C180 with a delay of 180 degrees and the doubled clock signal C270 with a delay of 270 degrees can be obtained, a total of 4 doubled clock signals.

[0059] S204: Sample the signal to be measured for at least two cycles using the basic clock signal to determine a coarse count value corresponding to each cycle.

[0060] Specifically, the rising edge and / or falling edge of the signal to be tested are sampled for at least two cycles of the signal to be tested by the basic clock signal. If only the rising edge of the signal to be tested is counted, the state of the signal to be tested can be sampled each time the basic clock signal reaches a rising edge. If it is detected that the signal to be tested jumps from a low level to a high level, it can be considered that a rising edge of the signal to be tested is captured, and the count value is increased by one at this time; if only the falling edge of the signal to be tested is counted, the state of the signal to be tested can be sampled each time the basic clock signal reaches a rising edge. If it is detected that the signal to be tested jumps from a high level to a low level, it can be considered that a falling edge of the signal to be tested is captured, and the count value is increased by one at this time; if the rising edge and falling edge of the signal to be tested are counted at the same time, the state of the signal to be tested can be sampled each time the basic clock signal reaches a rising edge. If it is detected that the signal to be tested jumps from a high level to a low level, it can be considered that a rising edge or a falling edge of the signal to be tested is captured, and the count value is increased by one at this time. Then the above-determined count value can be used as a rough count value of the corresponding cycle of the signal to be tested.

[0061] S205 , sampling the signal to be measured for at least two cycles using each frequency-multiplied phase-split clock signal, and determining a fine count value corresponding to each cycle.

[0062] Specifically, since different multiplied-frequency phase-splitting clock signals have the same frequency and different starting positions, that is, the rising edge positions of the clocks of different multiplied-frequency phase-splitting clock signals are different, when sampling the corresponding rising edge and / or falling edge within the period of the signal to be measured, the output jump time of the register triggered by different multiplied-frequency phase-splitting clock signals is different. At this time, each multiplied-frequency phase-splitting clock signal can be used to sample the signal to be measured for at least two periods of the signal to be measured according to its own frequency, and the sampling results can be stored in the register corresponding to the multiplied-frequency phase-splitting clock signal in sequence, and then the output values ​​of the registers corresponding to each multiplied-frequency phase-splitting clock signal during the sampling process of at least two periods of the signal to be measured are combined to determine the detailed count value corresponding to each period of the signal to be measured.

[0063] It can be understood that when each frequency-multiplied phase-split clock signal samples the signal to be measured, it can sample the rising edge of the signal to be measured when the rising edge of the clock of the frequency-multiplied phase-split clock signal arrives, or it can sample the falling edge of the signal to be measured when the rising edge of the clock of the frequency-multiplied phase-split clock signal arrives, or it can sample the rising edge or falling edge of the signal to be measured when the rising edge of the clock of the frequency-multiplied phase-split clock signal arrives. The embodiment of the present invention does not limit this.

[0064] For example, Figure 4A sampling timing diagram of a signal to be tested and each clock signal provided in the second embodiment of the present invention is shown as follows: Figure 4 As shown, from top to bottom, they are CLK signal, signal to be tested, C0 signal, C90 signal, C180 signal and C270 signal. The rising edge of the signal to be tested arrives in the second quadrant of the first cycle of the CLK signal. Then, when the rising edge of the clock in the second cycle of the CLK signal arrives, the count value of the signal to be tested will be increased by one, and the corresponding processing will be continued thereafter to finally obtain the corresponding rough count value. For C0 signal, C90 signal, C180 signal and C270 signal, when the signal to be tested is pulled high, since C180 is the fastest rising edge of the clock after the signal to be tested is pulled high, the register corresponding to the C180 signal will jump first, followed by the register corresponding to C270, the register corresponding to the C0 signal and the register corresponding to the C90 signal. By analogy, the sampling results can be stored in the register corresponding to the multiplied frequency phase-splitting clock signal in sequence, and the fine count value of the sampling results of each multiplied frequency clock signal can be determined based on the final output content of the register.

[0065] Optional, Figure 5 The second embodiment of the present invention provides a flow chart of a method for sampling a signal to be tested for at least two cycles by using each frequency-multiplied phase-splitting clock signal to determine a fine count value corresponding to each cycle, such as Figure 5 As shown, the specific steps include:

[0066] S2051. For each cycle of the signal to be measured, the rising edge trigger determined by the sampling frequency and delayed phase of each frequency-multiplied phase-splitting clock signal is used to sample the signal to be measured, and the sampling results are cached in registers corresponding to each frequency-multiplied phase-splitting clock signal.

[0067] For example, Figure 6 A structural example diagram of a cache register corresponding to each frequency-multiplied phase-split clock signal provided in the second embodiment of the present invention is shown as follows: Figure 6 As shown, in the embodiment of the present invention, the 7-level register is taken as an example. Figure 4 After the test signal shown in is input, since C180 is the fastest clock rising edge after the test signal is pulled high, the first register to jump is A31. Since the test signal input to it has been pulled high, its output value should jump to 1, followed by A41. At the same time, since A11 jumps only when the next C0 rising edge arrives, and A21 has not yet reached its corresponding rising edge, at this moment the outputs of A11 and A21 are still 0, while the outputs of A31 and A41 have jumped to 1. Therefore, after the next C0 rising edge arrives, the outputs of the first-level registers are A12=0, A22=0, A32=0 and A42=1 respectively. Figure 6In the second embodiment of the present invention, blue represents that the register output is 1, and white represents that the register output is 0.

[0068] Continuing with the above example, Figure 7 The output example diagram of a cache register corresponding to each frequency-multiplied phase-split clock signal provided in the second embodiment of the present invention is as follows: Figure 6 After the C0 clock rising edge shown in the figure arrives, the output of the cache register corresponding to each multiplied phase clock signal is as follows: Figure 7 As shown. That is, at each rising edge of C0, the data in each cache register will be shifted back. In the above manner, the sampling of the signal to be tested is triggered according to the sampling frequency and delayed phase of each multiplied phase clock signal, and the sampling results are cached in the registers corresponding to each multiplied phase clock signal.

[0069] S2052: When the code reading register in each register meets the preset code reading condition, the code data is read from the code reading register.

[0070] The coding read register is a register located in a preset coding area among the registers, and the preset coding area is determined according to the number of phase divisions.

[0071] In this embodiment, the preset coding area can be specifically understood as a set of registers located in the last phase sequence in the registers corresponding to each multiplied phase clock signal, which is set to ensure that each multiplied phase clock signal has sampled the signal to be tested within the period of the signal to be tested. The coding reading register can be understood as a register located in the preset coding area, and the coding value will be determined based on its output value. The preset coding reading condition can be specifically understood as a condition pre-set according to actual conditions to ensure that each multiplied phase clock signal has completed one sampling of the signal to be tested before coding reading.

[0072] Continuing with the above example, Figure 4 or Figure 6The area corresponding to the last four columns of cache registers in the cache register shown in is determined as the preset coding area, and each register located in the preset coding area is determined as a coding reading register. Since the register data will be shifted back with each C0 rising edge, when the CLK signal rising edge arrives, if the output of the register in the preset coding area is not all 0 or not all 1, it can be considered that in the previous CLK cycle, each frequency-multiplied phase-split clock signal has sampled the rising edge or falling edge of the signal to be measured. At this time, it can be considered that the output result of the register in the preset coding area can reflect the sampling of the signal to be measured by each frequency-multiplied phase-split clock signal. It can also be considered that the preset coding reading condition can be that when the CLK signal rising edge arrives, the registers in the preset coding area are not all 0 or not all 1. When this condition is met, the coding data can be read from each coding reading register in the preset coding area based on the preset coding reading method.

[0073] Continuing with the above example, Figure 8 This is an example diagram of the output of a cache register when reading encoded data provided by the second embodiment of the present invention, such as Figure 8 As shown, since the signal to be tested in the above example arrives in the second quadrant of CLK, the register data has not been moved to the preset coding area at the next CLK rising edge. The corresponding data will appear in the register in the preset coding area only when the next CLK rising edge arrives. Figure 8 This is an example of register output after 6 C0 cycles corresponding to this situation. In this case, the code value can be obtained by reading the code of each register in the preset code area as 03FF.

[0074] S2053. Determine a detailed count value corresponding to a period according to a corresponding relationship between the coding data and a preset coding count.

[0075] Specifically, according to actual conditions, the correspondence between the constructed code value and the fine count value can be used as a preset code count correspondence, and then after determining the code data of the signal to be tested, the count value corresponding to the code data can be determined according to the preset code count correspondence, and the count value can be determined as the fine count value. It can be understood that the resolution of the fine count value is the reciprocal of the product of the frequency of the multiplied frequency phase-splitting clock signal and the number of phase divisions.

[0076] Exemplarily, the preset encoding count correspondence relationship may be a decoding table. Taking the above embodiment as an example, the encoded data in the embodiment of the present invention may be 16-bit data, and the corresponding decoding table is represented by the following table:

[0077]

[0078] It is understandable that there is no obvious sequence between S204 and S205 , and the embodiment of the present invention only takes sequential execution as an example.

[0079] S206: Determine the coarse count value and the fine count value corresponding to each cycle as the counting result of the cycle.

[0080] S207: Determine the difference between the rough count values ​​of two adjacent cycles in each counting result as a first difference value.

[0081] Specifically, since the coarse count value indicates the coarse-grained counting result for the period of the signal to be measured, the difference between the coarse count values ​​corresponding to the periods of two adjacent signals to be measured can be used to reflect the period situation of the signal to be measured at a coarse granularity. At this time, the difference between the coarse count values ​​of two adjacent periods in each counting result can be determined as the first difference.

[0082] It is understandable that, when there are more than two counting results, the differences between the rough counting values ​​of adjacent cycles may be summed and averaged to determine the first difference value, so as to increase the stability and accuracy of the first difference value, and the embodiment of the present invention is not limited to this.

[0083] Exemplarily, taking the counting results including only two cycles as an example, in the counting results within the two cycles, the rough counting values ​​are P1 and P2 respectively, and the first difference can be expressed as (P2-P1).

[0084] S208. Determine the difference between the detailed count values ​​of two adjacent cycles in each counting result as a second difference value.

[0085] Specifically, since the fine count value indicates the fine-grained counting result for the period of the signal to be measured, the difference between the fine count values ​​corresponding to the periods of two adjacent signals to be measured can be used to reflect the period situation of the signal to be measured at a fine granularity. At this time, the difference between the fine count values ​​of two adjacent periods in each counting result can be determined as the second difference.

[0086] It is understandable that, when there are more than two counting results, the differences between the fine count values ​​of adjacent cycles may be summed and averaged to determine the second difference value, so as to increase the stability and accuracy of the second difference value, and the embodiment of the present invention is not limited to this.

[0087] Exemplarily, taking the counting results including only two cycles as an example, in the counting results within the two cycles, the detailed count values ​​are F1 and F2 respectively, and the first difference can be expressed as (F2-F1).

[0088] It is understandable that there is no obvious sequence between S207 and S208, and the embodiment of the present invention only takes sequential execution as an example.

[0089] S209: Determine a signal period of the signal to be measured according to a ratio between each first difference and the frequency of the basic clock signal, and a ratio between each second difference and the frequency of the frequency-multiplied phase-split clock signal.

[0090] Continuing with the above example, assuming that the frequency of the basic clock signal is M, the frequency multiplication factor is L, and the number of phase divisions is n, the signal period of the signal to be measured can be expressed as (P2-P1) / M+(F2-F1) / (M*L*n).

[0091] The technical solution of this embodiment is that after the basic clock signal is multiplied according to the frequency increase multiple, the multiplied clock signal obtained by the multiplication process is equally divided according to the number of phase divisions, so that the multiplied phase division clock signals obtained by the phase divisions have the same delayed phase difference, and then the basic clock signal and each multiplied phase division clock signal are respectively sampled for at least two cycles of the signal to be measured, and the sampling result of the basic clock signal is determined as a coarse count value, and the sampling result of each multiplied phase division clock signal is determined as a fine count value, and the counting result for the signal to be measured is determined from the coarse and fine dimensions, and then the signal period of the signal to be measured is comprehensively determined according to the counting results in the two dimensions. Among them, when determining the fine count value, the accurate reading of the encoding data related to the fine count value is completed by dividing the preset coding area in the register corresponding to each multiplied phase division clock signal, thereby improving the accuracy of the determination of the fine count value, further improving the accuracy of the signal period determined according to the fine count value and the coarse count value, and improving the precision and accuracy of the measurement of the period of the signal to be measured, thereby improving the shooting stability of the industrial camera triggered by the signal to be measured.

[0092] Embodiment 3

[0093] Fig. 9 A schematic diagram of the structure of a signal period determination device provided in Embodiment 3 of the present invention is shown in FIG. Fig. 9 As shown, the signal period determination device includes an information acquisition module 31 , a clock determination module 32 , a counting result determination module 33 and a signal period determination module 34 .

[0094] Among them, the information acquisition module 31 is used to obtain the signal to be measured, the basic clock signal, the frequency increase multiple and the number of phase divisions; the clock determination module 32 is used to perform frequency multiplication and phase division processing on the basic clock signal according to the frequency increase multiple and the number of phase divisions to obtain a frequency-multiplied and phase-splitting clock signal with a number of phase divisions; the counting result determination module 33 is used to sample the signal to be measured through the basic clock signal and each frequency-multiplied and phase-splitting clock signal for at least two cycles respectively, and determine the counting result corresponding to each cycle; the signal period determination module 34 is used to determine the signal period of the signal to be measured according to each counting result.

[0095] The technical solution of the embodiment of the present invention is that before counting and sampling the signal to be measured, the basic clock signal used for traditional counting is first multiplied and phase-split based on the acquired frequency increase multiple and phase split number. The frequency multiplication process can increase the frequency of the basic clock signal, and the phase split process can delay the multiplied clock signal with an equal phase difference to obtain a frequency-multiplied and phase-split clock signal after several times of phase split. Then, when the signal to be measured is sampled and processed by each frequency-multiplied and phase-split clock signal, it is equivalent to sampling the original basic clock signal once and sampling the frequency increase multiple times the phase split number to obtain a counting result corresponding to the period of the signal to be measured. Due to the substantial increase in the number of sampling times, the precision and accuracy of the measurement of the period of the signal to be measured are improved, thereby improving the shooting stability of the industrial camera triggered by the signal to be measured.

[0096] Optionally, the clock determination module 32 is specifically configured to:

[0097] Perform frequency multiplication processing on the basic clock signal according to the frequency multiplication factor to determine the frequency multiplied clock signal;

[0098] The frequency-multiplied clock signal is equally divided and phase-split according to the phase-split number to obtain the frequency-multiplied phase-split clock signal with the phase-split number;

[0099] The delayed phase difference between two adjacent frequency-multiplied phase-splitting clock signals is the same; the delayed phase difference is the ratio of 360 degrees to the number of phase divisions.

[0100] Optionally, the counting result determination module 33 includes:

[0101] A coarse count value determination unit, used to sample the signal to be measured for at least two cycles using a basic clock signal to determine a coarse count value corresponding to each cycle;

[0102] A fine count value determination unit, used to sample the signal to be measured for at least two cycles through each frequency-multiplied phase-split clock signal, and determine the fine count value corresponding to each cycle;

[0103] The counting result determining unit is used to determine the coarse counting value and the fine counting value corresponding to each cycle as the counting result of the cycle.

[0104] Optionally, a detailed count value determination unit is specifically used to:

[0105] For each cycle of the signal to be measured, the sampling of the signal to be measured is triggered according to the sampling frequency and delayed phase of each frequency-multiplied phase-splitting clock signal, and the sampling results are cached in registers corresponding to each frequency-multiplied phase-splitting clock signal;

[0106] When the code reading register in each register meets the preset code reading condition, the code data is read from the code reading register;

[0107] The fine count value corresponding to the period is determined according to the corresponding relationship between the coding data and the preset coding count.

[0108] Optionally, the coding read register is a register in each register that is located in a preset coding area, and the preset coding area is determined according to the number of phase divisions.

[0109] Optionally, the signal period determination module 34 is specifically configured to:

[0110] The difference between the rough count values ​​of two adjacent cycles in each counting result is determined as a first difference value;

[0111] The difference between the fine count values ​​of two adjacent cycles in each counting result is determined as a second difference value;

[0112] The signal period of the signal to be measured is determined according to the ratio of each first difference to the frequency of the basic clock signal, and the ratio of each second difference to the frequency of the multiplied frequency phase-splitting clock signal.

[0113] The signal period determination device provided in the embodiment of the present invention can execute the signal period determination method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0114] Embodiment 4

[0115] Fig.10 A schematic diagram of the structure of a signal period determination device provided for Embodiment 4 of the present invention. The signal period determination device 40 may be intended to represent various forms of digital computers, such as laptop computers, desktop computers, workbenches, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The signal period determination device 40 may also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.

[0116] like Fig.10As shown, the signal period determination device 40 includes at least one processor 41, and a memory connected to the at least one processor 41, such as a read-only memory (ROM) 42, a random access memory (RAM) 43, etc., wherein the memory stores a programmable program that can be executed by at least one processor, and the processor 41 can perform various appropriate actions and processes according to the programmable program stored in the read-only memory (ROM) 42 or the programmable program loaded from the storage unit 48 to the random access memory (RAM) 43. In RAM 43, various programs and data required for the operation of the signal period determination device 40 can also be stored. The processor 41, ROM 42 and RAM 43 are connected to each other via a bus 44. An input / output (I / O) interface 45 is also connected to the bus 44. Optionally, the processor can be an FPGA.

[0117] A number of components in the signal period determination device 40 are connected to an I / O interface 45, including: an input unit 46, such as a keyboard, a mouse, etc.; an output unit 47, such as various types of displays, speakers, etc.; a storage unit 48, such as a disk, an optical disk, etc.; and a communication unit 49, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 49 allows the signal period determination device 40 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0118] The processor 41 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 41 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 41 performs the various methods and processes described above, such as a signal period determination method.

[0119] In some embodiments, the signal period determination method may be implemented as a programmable program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 48. In some embodiments, part or all of the programmable program may be loaded and / or installed on the signal period determination device 40 via the ROM 42 and / or the communication unit 49. When the programmable program is loaded into the RAM 43 and executed by the processor 41, one or more steps of the signal period determination method described above may be performed. Alternatively, in other embodiments, the processor 41 may be configured to perform the signal period determination method in any other appropriate manner (e.g., by means of firmware).

[0120] Optionally, an embodiment of the present invention further provides a programmable program product, including a programmable program, which, when executed by a processor, implements the signal period determination method provided by any embodiment of the present invention.

[0121] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include: being implemented in one or more programmable programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0122] Programmable programs for implementing the method of the present invention may be written in any combination of one or more programming languages. These programmable programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the programmable program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The programmable program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0123] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a programmable program for use by or in conjunction with an instruction execution system, device, or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0124] To provide interaction with a user, the systems and techniques described herein may be implemented on a signal period determination device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or trackball), through which a user may provide input to the signal period determination device. Other types of devices may also be used to provide interaction with a user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0125] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0126] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by programmable programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

[0127] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0128] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for determining a signal period, characterized in that: include: Obtain the signal to be tested, the basic clock signal, the frequency multiplication factor and the number of phase divisions; Perform frequency multiplication and phase splitting processing on the basic clock signal according to the frequency multiplication factor and the phase splitting number to obtain a frequency multiplied and phase splitting clock signal with the phase splitting number; The signal to be measured is sampled for at least two cycles respectively by using the basic clock signal and each of the frequency-multiplied phase-splitting clock signals to determine a counting result corresponding to each cycle; The signal period of the signal to be measured is determined according to each of the counting results.

2. The signal period determination method according to claim 1, characterized in that: The method of performing frequency multiplication and phase splitting processing on the basic clock signal according to the frequency multiplication factor and the phase splitting number to obtain the frequency multiplied and phase splitting clock signals with the phase splitting number includes: Perform frequency multiplication processing on the basic clock signal according to the frequency multiplication factor to determine a frequency multiplied clock signal; Performing equal phase division processing on the frequency-multiplied clock signal according to the phase division number to obtain the frequency-multiplied phase division clock signals with the phase division number; Among them, the delayed phase difference between two adjacent frequency-doubled phase-splitting clock signals is the same; the delayed phase difference is the ratio of 360 degrees to the phase number.

3. The signal period determination method according to claim 1, characterized in that: The sampling of the signal to be measured for at least two cycles by respectively using the basic clock signal and each of the frequency-multiplied phase-splitting clock signals to determine the counting result corresponding to each cycle includes: Sampling the signal to be measured for at least two cycles using the basic clock signal to determine a coarse count value corresponding to each cycle; Sampling the signal to be measured for at least two cycles by using each of the frequency-multiplied phase-splitting clock signals to determine a fine count value corresponding to each cycle; The coarse count value and the fine count value corresponding to each cycle are determined as the counting result of the cycle.

4. The signal period determination method according to claim 3, characterized in that: The sampling of the signal to be measured for at least two cycles by each of the frequency-multiplied phase-splitting clock signals to determine the fine count value corresponding to each cycle includes: For each cycle of the signal to be measured, the rising edge triggering of the signal to be measured is determined according to the sampling frequency and the delayed phase of each of the frequency-multiplied phase-splitting clock signals, and the sampling results are cached in registers corresponding to each of the frequency-multiplied phase-splitting clock signals; When the code reading register in each of the registers meets the preset code reading condition, the code data is read from the code reading register; The fine count value corresponding to the period is determined according to the corresponding relationship between the coded data and the preset coded count.

5. The signal period determination method according to claim 4, characterized in that: The encoding reading register is a register located in a preset encoding area among the registers, and the preset encoding area is determined according to the phase number.

6. The signal period determination method according to claim 3, characterized in that: The step of determining the signal period of the signal to be tested according to each of the counting results comprises: Determine the difference between the rough count values ​​of two adjacent cycles in each of the counting results as a first difference value; Determine the difference between the fine count values ​​of two adjacent cycles in each of the counting results as a second difference value; The signal period of the signal to be measured is determined according to the ratio of each of the first differences to the frequency of the basic clock signal, and the ratio of each of the second differences to the frequency of the multiplied frequency phase-split clock signal.

7. A signal period determination device, characterized in that: include: An information acquisition module is used to obtain the signal to be tested, the basic clock signal, the frequency increase multiple and the phase division number; A clock determination module, configured to perform frequency multiplication and phase division processing on the basic clock signal according to the frequency multiplication factor and the phase division number, so as to obtain a frequency multiplication and phase division clock signal with the phase division number; A counting result determination module, used to sample the signal to be measured for at least two cycles respectively through the basic clock signal and each of the frequency-multiplied phase-splitting clock signals, and determine the counting result corresponding to each cycle; A signal period determination module is used to determine the signal period of the signal to be measured according to each of the counting results.

8. A signal period determination device, characterized in that: include: at least one processor; and a memory communicatively coupled to the at least one processor; The memory stores a programmable program executable by the at least one processor, and the programmable program is executed by the at least one processor so that the at least one processor can execute the signal period determination method according to any one of claims 1 to 6.

9. A storage medium containing executable instructions, characterized in that: When the executable instructions are executed by a programmable processor, they are used to execute the signal period determination method according to any one of claims 1 to 6.

10. A program product, comprising a programmable program, wherein when the programmable program is executed by a processor, the signal period determination method according to any one of claims 1 to 6 is implemented.

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