Amplifier circuit with common-mode rejection

Abstract

The invention discloses an amplifier circuit with common-mode rejection, and belongs to the technical field of integrated circuits. The amplifier circuit comprises a first input end, a second input end, a first phase inverter, a second phase inverter, a third phase inverter, a fourth phase inverter, a fifth phase inverter, a sixth phase inverter, a seventh phase inverter, an eighth phase inverter, a first output end, a second output end and a switch. Wherein the first input end and the second input end are used for inputting differential signals to be processed; the first phase inverter to the eighth phase inverter are used for realizing common-mode rejection, and the switch is used for realizing dynamic amplification processing of differential signals; and the first output end and the second output end are used for outputting a processing result of the differential signal. The power consumption of the amplifier is reduced, and common-mode rejection can be improved under the condition that the performance of the amplifier is not affected.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuits, and in particular to an amplifier circuit with common-mode suppression. Background Art

[0002] High-speed and high-precision analog-to-digital converters (ADCs) are widely used and demanded in fields such as high-bandwidth real-time oscilloscopes, 5G and WIFI 6 / 7 wireless communications, and high-resolution radars. Pipeline or time-interleaved pipeline ADCs are the mainstream architectures for high-speed and high-precision ADCs, but the disadvantages of pipeline architectures are complex design, high power consumption, and the need for inter-stage gain calibration. Unlike pipeline architectures, successive approximation (SAR) ADCs have simple structures, low power consumption, and good robustness, but SAR architectures are mainly suitable for high-speed, medium- and low-precision applications.

[0003] The comparator is a key module that affects the conversion speed and accuracy of the SAR ADC. Currently, the commonly used comparators often have problems such as slow speed and high noise. In order to overcome these problems of the comparator, a pre-amplifier module is usually added to the front end of the comparator, which can effectively speed up the comparator's settling speed and suppress the comparator's noise.

[0004] Static amplifiers based on inverters are widely used due to their high current efficiency. However, due to their pseudo-differential structure, the common-mode gain is equivalent to the differential-mode gain, which makes the circuit sensitive to common-mode changes. Therefore, how to improve the common-mode rejection without affecting the performance of the amplifier so that it can be better used in high-speed and high signal-to-noise ratio SAR ADCs is an urgent problem to be solved. Summary of the invention

[0005] The invention provides an amplifier circuit with common-mode suppression to solve the technical problem of low common-mode suppression existing in the existing amplifier.

[0006] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0007] An amplifier circuit with common mode suppression comprises: a first input terminal, a second input terminal, a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, a first output terminal, a second output terminal and a switch; wherein,

[0008] The first input terminal and the second input terminal are used to input a differential signal to be processed;

[0009] The first inverter, the second inverter, the third inverter, the fourth inverter, the fifth inverter, the sixth inverter, the seventh inverter, the eighth inverter and the switch are used to process the input differential signal; wherein the first inverter, the second inverter, the third inverter, the fourth inverter, the fifth inverter, the sixth inverter, the seventh inverter and the eighth inverter realize common mode suppression, and the switch realizes dynamic amplification processing of the differential signal;

[0010] The first output terminal and the second output terminal are used to output the processing result of the differential signal.

[0011] Further, the output end of the first inverter is electrically connected to the input end of the third inverter, the output end of the fifth inverter and the input end of the sixth inverter; the input end of the first inverter is electrically connected to the first input end and the input end of the seventh inverter; the output end of the third inverter is electrically connected to the first output end and the output end of the eighth inverter; the output end of the second inverter is electrically connected to the input end of the fourth inverter, the output end of the sixth inverter and the input end of the fifth inverter; the input end of the second inverter is electrically connected to the second input end and the input end of the eighth inverter; the output end of the fourth inverter is electrically connected to the second output end and the output end of the seventh inverter; the input end of the sixth inverter is electrically connected to the first port of the switch, and the input end of the fifth inverter is electrically connected to the second port of the switch.

[0012] Further, the first inverter, the second inverter, the third inverter, the fourth inverter, the fifth inverter, the sixth inverter, the seventh inverter and the eighth inverter have the same structure, and all include an inverter input terminal, an inverter output terminal, a first transistor and a second transistor;

[0013] The gates of the first transistor and the second transistor are electrically connected and electrically connected to the inverter input terminal; the drains of the first transistor and the second transistor are electrically connected and electrically connected to the inverter output terminal.

[0014] Furthermore, the first transistor is an NMOS transistor; and the second transistor is a PMOS transistor.

[0015] Furthermore, the switch includes a third transistor; the gate of the third transistor is connected to an external clock signal; the drain of the third transistor serves as the first port of the switch, and the source serves as the second port of the switch.

[0016] Furthermore, the third transistor is an NMOS transistor.

[0017] Furthermore, when the clock signal is at a high level, the third transistor is turned on, and the amplifier circuit with common-mode suppression amplifies the input differential signal; when the clock signal is at a low level, the third transistor is turned off, and the amplifier circuit with common-mode suppression stops working. During the stage when the amplifier circuit stops working, it can be used to compare the input differential signal and complete the conversion of analog signals to digital signals.

[0018] The beneficial effects brought about by the technical solution provided by the present invention include at least:

[0019] The amplifier circuit with common-mode suppression provided by the present invention realizes common-mode suppression through the first inverter to the eighth inverter; realizes dynamic amplification processing of differential signals through switches, thereby reducing the power consumption of the amplifier. The common-mode suppression can be improved without affecting the performance of the amplifier, so that it can be better applied to high-speed and high-signal-to-noise ratio SAR ADC, solving the problem of low common-mode suppression existing in existing amplifiers. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0021] Figure 1 is a schematic structural diagram of an amplifier circuit with common-mode suppression provided by an embodiment of the present invention;

[0022] Figure 2 It is a comparison circuit similar to the basic structure of the present invention;

[0023] Figure 3 is a performance diagram of an amplifier circuit with common-mode rejection provided by an embodiment of the present invention under different temperatures, processes, and voltages;

[0024] Figure 4 This is the trigger timing of the amplifier circuit with common-mode suppression provided by the embodiment of the present invention.

[0025] Component marking instructions:

[0026] 1. First inverter; 2. Second inverter; 3. Third inverter; 4. Fourth inverter;

[0027] 5. fifth inverter; 6. sixth inverter; 7. seventh inverter; 8. eighth inverter;

[0028] Mn1, a first transistor; Mp1, a second transistor; Mn2, a third transistor; S1, a switch;

[0029] CLK, clock signal; Vip, first input terminal; Vin, second input terminal; Vop, first output terminal;

[0030] Von, second output terminal; P1, first port; P2, second port. DETAILED DESCRIPTION

[0031] In order to make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0032] First of all, it should be noted that in the embodiments of the present invention, words such as "exemplarily" and "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "exemplary" in the present invention should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of the word "exemplarily" is intended to present the concept in a concrete way. In addition, in the embodiments of the present invention, the meaning expressed by "and / or" can be both, or it can be either of the two.

[0033] This embodiment provides an amplifier circuit with common-mode suppression, including a pseudo-differential Class AB structure with a double-ended input and a double-ended output, for amplifying an input differential signal to obtain a differential signal while suppressing common-mode gain. Figure 1 As shown, the amplifier circuit with common-mode suppression includes: a first input terminal Vip, a second input terminal Vin, a first inverter 1, a second inverter 2, a third inverter 3, a fourth inverter 4, a fifth inverter 5, a sixth inverter 6, a seventh inverter 7, an eighth inverter 8, a first output terminal Vop, a second output terminal Von and a switch S1; wherein the first input terminal Vip and the second input terminal Vin are used to input a differential signal to be processed; the first inverter 1, the second inverter 2, the third inverter 3, the fourth inverter 4, the fifth inverter 5, the sixth inverter 6, the seventh inverter 7, the eighth inverter 8, a first output terminal Vop, a second output terminal Von and a switch S1; wherein the first input terminal Vip and the second input terminal Vin are used to input a differential signal to be processed; the first inverter 1, the second inverter 2, the third inverter 3, the fourth inverter 4, the fifth inverter 5, the sixth inverter 6, the seventh inverter 7, the eighth inverter 8, the first output terminal Vop, the second output terminal Von and a switch S1 The fifth inverter 5, the sixth inverter 6, the seventh inverter 7, the eighth inverter 8 and the switch S1 are used to process the input differential signal; wherein the first inverter 1, the second inverter 2, the third inverter 3, the fourth inverter 4, the fifth inverter 5, the sixth inverter 6, the seventh inverter 7 and the eighth inverter 8 are used to achieve common mode suppression, and the switch S1 is used to achieve dynamic amplification processing of the differential signal; the first output terminal Vop and the second output terminal Von are used to output the processing result of the differential signal.

[0034] Specifically, the output end of the first inverter 1 is electrically connected to the input end of the third inverter 3, the output end of the fifth inverter 5 and the input end of the sixth inverter 6; the input end of the first inverter 1 is electrically connected to the first input end Vip and the input end of the seventh inverter 7; the output end of the third inverter 3 is electrically connected to the first output end Vop, and is electrically connected to the output end of the eighth inverter 8; the output end of the second inverter 2 is electrically connected to the input end of the fourth inverter 4, the output end of the sixth inverter 6 and the input end of the fifth inverter 5; the input end of the second inverter 2 is electrically connected to the second input end Vin and the input end of the eighth inverter 8; the output end of the fourth inverter 4 is electrically connected to the second output end Von, and is electrically connected to the output end of the seventh inverter 7; the input end of the sixth inverter 6 is electrically connected to the first port P1 of the switch S1, and the input end of the fifth inverter 5 is electrically connected to the second port P2 of the switch S1.

[0035] Further, the first inverter 1, the second inverter 2, the third inverter 3, the fourth inverter 4, the fifth inverter 5, the sixth inverter 6, the seventh inverter 7 and the eighth inverter 8 have the same structure, and all include an inverter input terminal, an inverter output terminal, a first transistor Mn1 and a second transistor Mp1; wherein the gates of the first transistor Mn1 and the second transistor Mp1 are electrically connected, and are electrically connected to the inverter input terminal; the drains of the first transistor Mn1 and the second transistor Mp1 are electrically connected, and are electrically connected to the inverter output terminal. Specifically, in this embodiment, the first transistor Mn1 is an NMOS tube; the second transistor Mp1 is a PMOS tube.

[0036] Further, the switch S1 includes a third transistor Mn2; the gate of the third transistor Mn2 is connected to the external clock signal CLK; the drain of the third transistor Mn2 serves as the first port P1 of the switch S1, and the source of the third transistor Mn2 serves as the second port P2 of the switch S1. Specifically, in this embodiment, the third transistor Mn2 is an NMOS tube.

[0037] Assuming that the MOS tubes included in the first inverter 1 to the eighth inverter 8 are of the same size, the differential mode gain of the amplifier is , the common-mode gain is ; where g m is the transconductance of the first inverter 1 to the eighth inverter 8, g ds is the conductance of the first inverter 1 to the eighth inverter 8.

[0038] See also Figure 2, which shows a comparative circuit similar to the basic structure of the present invention. Figure 2 As shown, the similar structure includes a differential amplifier based on an inverter structure and a differential amplifier based on a dual inverter structure, which uses the same MOS tube size as the first inverter 1 in the present invention, and the differential mode gain of the inverter structure is , the common-mode gain is ; The differential mode gain of the dual inverter structure is , the common-mode gain is ; The performance results obtained under the same process library and the same power supply voltage are shown in Table 1.

[0039] Table 1 Performance comparison of various fully differential amplifiers based on inverter structures

[0040]

[0041] It can be seen from Table 1 that the amplifier circuit with common-mode rejection of the present invention has a lower common-mode gain under the condition of similar differential-mode gain, that is, has better common-mode rejection.

[0042] See also Figure 3 , which shows the performance of the amplifier circuit with common mode suppression of the present invention under different temperatures, processes, and voltages. Figure 3 As shown, the amplifier circuit with common-mode suppression of the present invention has a certain common-mode suppression capability under various processes.

[0043] See also Figure 4 , which shows the trigger timing of the amplifier circuit with common mode suppression of the present invention. Figure 4 As shown, when the clock signal CLK is at a high level, the third transistor Mn2 is turned on, and the amplifier amplifies the input differential signal; when the clock signal CLK is at a low level, the third transistor Mn2 is turned off, and the amplifier stops working. In this embodiment, the amplifier stopping working stage can be used for comparing differential amplified signals to complete the conversion of analog signals to digital signals.

[0044] In addition, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. The terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprises a..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0045] Finally, it should be noted that the above is only a preferred embodiment of the present invention. It should be pointed out that although the preferred embodiment of the present invention has been described, for ordinary technicians in this technical field, once the basic creative concept of the present invention is known, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the protection scope of the present invention. Therefore, the attached claims are intended to be interpreted as including the preferred embodiment and all changes and modifications that fall within the scope of the embodiments of the present invention.

Claims

1. An amplifier circuit with common-mode suppression, characterized in that: include: a first input terminal, a second input terminal, a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, a first output terminal, a second output terminal, and a switch; wherein, The first input terminal and the second input terminal are used to input a differential signal to be processed; The first inverter, the second inverter, the third inverter, the fourth inverter, the fifth inverter, the sixth inverter, the seventh inverter, the eighth inverter and the switch are used to process the input differential signal; wherein the first inverter, the second inverter, the third inverter, the fourth inverter, the fifth inverter, the sixth inverter, the seventh inverter and the eighth inverter realize common mode suppression, and the switch realizes dynamic amplification processing of the differential signal; The first output terminal and the second output terminal are used to output the processing result of the differential signal.

2. The amplifier circuit with common mode rejection as claimed in claim 1, characterized in that: The output end of the first inverter is electrically connected to the input end of the third inverter, the output end of the fifth inverter and the input end of the sixth inverter; the input end of the first inverter is electrically connected to the first input end and the input end of the seventh inverter; the output end of the third inverter is electrically connected to the first output end and the output end of the eighth inverter; the output end of the second inverter is electrically connected to the input end of the fourth inverter, the output end of the sixth inverter and the input end of the fifth inverter; the input end of the second inverter is electrically connected to the second input end and the input end of the eighth inverter; the output end of the fourth inverter is electrically connected to the second output end and the output end of the seventh inverter; An input terminal of the sixth inverter is electrically connected to the first port of the switch, and an input terminal of the fifth inverter is electrically connected to the second port of the switch.

3. The amplifier circuit with common mode rejection as claimed in claim 1, characterized in that: The first inverter, the second inverter, the third inverter, the fourth inverter, the fifth inverter, the sixth inverter, the seventh inverter and the eighth inverter have the same structure, and all include: an inverter input terminal, an inverter output terminal, a first transistor and a second transistor; The gates of the first transistor and the second transistor are electrically connected and electrically connected to the inverter input terminal; the drains of the first transistor and the second transistor are electrically connected and electrically connected to the inverter output terminal.

4. The amplifier circuit with common mode rejection as claimed in claim 3, characterized in that: The first transistor is an NMOS transistor; the second transistor is a PMOS transistor.

5. The amplifier circuit with common mode rejection as claimed in claim 2, characterized in that: The switch includes a third transistor; the gate of the third transistor is connected to an external clock signal; the drain of the third transistor serves as the first port of the switch, and the source serves as the second port of the switch.

6. The amplifier circuit with common mode rejection as claimed in claim 5, characterized in that: The third transistor is an NMOS transistor.

7. The amplifier circuit with common mode rejection as claimed in claim 5, characterized in that: When the clock signal is at a high level, the third transistor is turned on, and the amplifier circuit with common-mode suppression amplifies the input differential signal; when the clock signal is at a low level, the third transistor is turned off, and the amplifier circuit with common-mode suppression stops working. During the amplifier circuit stopping working stage, it can be used to compare the input differential signal and complete the conversion of analog signals to digital signals.

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