Delay-locked loop circuit, and locking test method and related device thereof

Abstract

The invention provides a delay-locked loop circuit, a locking test method thereof and a related device. The DLL circuit comprises: a master control loop comprising a voltage-controlled delay line, the voltage-controlled delay line comprising a plurality of stages of first delay units connected in series, the voltage-controlled delay line being configured to generate a plurality of stages of phase clock signals for delaying a reference clock signal according to a bias voltage, the main control loop is used for controlling the locking state of the DLL circuit according to the phase difference between a reference clock signal and a feedback phase clock signal generated by the voltage-controlled delay line; and the ring oscillator comprises multiple stages of second delay units which are in loop connection, and is used for outputting an oscillation signal according to the bias voltage so as to calculate the delay time of the second delay units according to the frequency of the oscillation signal, comparing the delay time of the second delay units with a standard value, and determining the locking state of the DLL according to a comparison result. Wherein the standard value is the delay time of the first delay unit when the DLL circuit is in a correct locking state, so that the mass production test cost of the DLL circuit is reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a delay phase-locked loop circuit and a locking test method and related devices thereof. Background Art

[0002] As the clock frequency range becomes wider and wider, how to ensure that the delay looked loop (DLL) circuit correctly locks and outputs multi-phase clocks at various frequencies has become a key requirement for DLL design. For ps-level high-precision clock signals, in a simulation experiment environment, a high-precision oscilloscope can be used under a specific program to display the phase clock signals output by adjacent delay units in the voltage-controlled delay line in the delay looked loop circuit to measure the delay time between the phase clock signals output by adjacent delay units, thereby comparing the delay time with the standard value to determine the locking state of the delay looked loop circuit. Obviously, this locking test method can generally only be implemented in a laboratory environment and cannot cover mass production testing, which increases the mass production test cost of the delay looked loop circuit. Summary of the invention

[0003] In view of the above problems, the present disclosure provides a delay locked loop circuit and a lock test method and related devices thereof, aiming to reduce the mass production test cost of the delay locked loop circuit.

[0004] According to a first aspect of the present disclosure, a delay locked loop circuit is provided, comprising: A main control loop, comprising a voltage-controlled delay line, the voltage-controlled delay line comprising a plurality of first delay units connected in series, the voltage-controlled delay line being used to generate a plurality of phase clock signals that delay a reference clock signal according to a bias voltage, the main control loop being used to control a locking state of the delay-locked loop circuit according to a phase difference between the reference clock signal and a feedback phase clock signal generated by the voltage-controlled delay line; A ring oscillator comprises a multi-stage second delay unit connected in a loop, which is used to output an oscillation signal according to the bias voltage, so as to calculate the delay time of the second delay unit according to the frequency of the oscillation signal, compare the delay time of the second delay unit with a standard value, and determine the locking state of the delay phase-locked loop circuit according to the comparison result, wherein the standard value is the delay time of the first delay unit when the delay phase-locked loop circuit is in a correctly locked state.

[0005] Optionally, the second delay unit has the same circuit structure and load as the first delay unit, and the delay time of the second delay unit is the same as the delay time of the first delay unit.

[0006] Optionally, the delay locked loop circuit further includes: A frequency divider, connected to the ring oscillator, for performing frequency division processing on the oscillation signal; A universal input-output interface is connected to the frequency divider and is used to output the oscillation signal after the frequency division processing, so as to calculate the delay time of the second delay unit according to the frequency of the oscillation signal after the frequency division processing, compare the delay time of the second delay unit with the standard value, and determine the locking state of the delay phase-locked loop circuit according to the comparison result.

[0007] Optionally, if the delay time of the second delay unit is equal to the standard value, the delay phase-locked loop circuit is in a correctly locked state; If the delay time of the second delay unit is equal to the product of the standard value and the first value, the delay phase-locked loop circuit is in a harmonic locking state, and the first value is an integer and greater than 1; The standard value is the quotient of the period of the reference clock signal and the number of first delay units in the voltage-controlled delay line.

[0008] Optionally, the main control loop further includes: A phase detector, used to perform phase detection on the reference clock signal and the feedback phase clock signal generated by the voltage-controlled delay line, and output a phase detection signal corresponding to the phase difference between the reference clock signal and the feedback phase clock signal generated by the voltage-controlled delay line; A charge pump, used for generating a phase difference current corresponding to the phase detection signal; A low-pass filter, used for converting the phase difference current into a voltage signal and generating a control voltage; The bias generating circuit is used to generate the bias voltage according to the control voltage, and provide the bias voltage to the first delay unit and the second delay unit to control the delay time of the first delay unit and the second delay unit.

[0009] Optionally, the first delay unit includes: A first transistor to a fourth transistor connected in series, wherein a first channel end of the first transistor is connected to a power supply, a second channel end of the first transistor is connected to a first channel end of the second transistor, a second channel end of the second transistor is connected to a first channel end of the third transistor, a second channel end of the third transistor is connected to a first channel end of the fourth transistor, and a second channel end of the fourth transistor is grounded, a control end of the first transistor and a control end of the fourth transistor receive the bias voltage, a first connection node of the control end of the second transistor and a control end of the third transistor receive a previous stage phase clock signal output by a previous stage first delay unit, and a second connection node of the second channel end of the second transistor and the first channel end of the third transistor provides a current stage phase clock signal; The first connection node of the first-stage first delay unit receives the reference clock signal, and the second connection node of the last-stage first delay unit provides the feedback phase clock signal.

[0010] Optionally, the second delay unit includes: A first transistor to a fourth transistor connected in series, wherein a first channel end of the first transistor is connected to a power supply, a second channel end of the first transistor is connected to a first channel end of the second transistor, a second channel end of the second transistor is connected to a first channel end of the third transistor, a second channel end of the third transistor is connected to a first channel end of the fourth transistor, a second channel end of the fourth transistor is grounded, a control end of the first transistor and a control end of the fourth transistor receive the bias voltage, a first connection node of the control end of the second transistor and a control end of the third transistor receive an output signal of a second delay unit of a previous stage, and a second connection node of the second channel end of the second transistor and the first channel end of the third transistor provides an output signal of a second delay unit of a current stage; The first connection node of the first-stage second delay unit is connected to the second connection node of the last-stage second delay unit, and the second connection node of the last-stage second delay unit provides the oscillation signal.

[0011] According to a second aspect of the present disclosure, a lock test method for a delay locked loop circuit is provided, wherein the delay locked loop circuit comprises a main control loop and a ring oscillator, wherein the main control loop comprises a voltage-controlled delay line, wherein the voltage-controlled delay line comprises a plurality of first delay units connected in series, wherein the voltage-controlled delay line is used to generate a plurality of phase clock signals of a delayed reference clock signal according to a bias voltage, wherein the main control loop is used to control a lock state of the delay locked loop circuit according to a phase difference between the reference clock signal and a feedback phase clock signal generated by the voltage-controlled delay line, wherein the ring oscillator comprises a plurality of second delay units connected in a loop, wherein the ring oscillator outputs an oscillation signal according to the bias voltage, and wherein the method comprises: Calculating the delay time of the second delay unit according to the frequency of the oscillation signal; The delay time of the second delay unit is compared with a standard value, and the locking state of the delay phase-locked loop circuit is determined according to the comparison result, wherein the standard value is the delay time of the first delay unit when the delay phase-locked loop circuit is in a correctly locked state.

[0012] According to a third aspect of the present disclosure, a clock generation chip is provided, comprising: Delay locked loop circuit as described above.

[0013] According to a fourth aspect of the present disclosure, there is provided an electronic device, including: Clock generating chip as described above.

[0014] The present disclosure brings the following beneficial effects: In the delay phase-locked loop circuit provided by the present disclosure, the main control loop includes a voltage-controlled delay line, the voltage-controlled delay line includes a plurality of first delay units connected in series, the voltage-controlled delay line is used to generate a multi-stage phase clock signal of a delayed reference clock signal according to a bias voltage, the main control loop is used to control the locking state of the delay phase-locked loop circuit according to the phase difference between the reference clock signal and the feedback phase clock signal generated by the voltage-controlled delay line, the ring oscillator includes a plurality of second delay units connected in a loop, which are used to output an oscillation signal according to the bias voltage, so as to calculate the delay time of the second delay unit according to the frequency of the oscillation signal, and the frequency of the second delay unit is calculated. The delay time is compared with a standard value, and the locking state of the delay phase-locked loop circuit is determined according to the comparison result. The standard value is the delay time of the first delay unit when the delay phase-locked loop circuit is in a correctly locked state. In this way, in the mass production test stage, it is only necessary to test the frequency of the oscillation signal output by the ring oscillator to calculate the delay time of the second delay unit, that is, to obtain the delay time of the first delay unit in the current voltage-controlled delay line, and compare the calculated delay time of the second delay unit with the standard value. According to the comparison result, the locking state of the delay phase-locked loop circuit can be determined, which reduces the mass production test cost of the delay phase-locked loop circuit.

[0015] In addition, by adding a simple circuit structure (i.e., a ring oscillator) to the delay-locked loop circuit, it is possible to determine whether the delay-locked loop circuit is correctly locked during the testing phase of the chip production process. Chips that fail to function due to process deviations that exceed the adjustment range can be discovered early, thereby reducing subsequent chip production costs.

[0016] Other features and advantages of the present disclosure will be described in the following description, and partly become apparent from the description, or understood by practicing the present disclosure. The purpose and other advantages of the present disclosure are realized and obtained by the structures particularly pointed out in the description and the drawings.

[0017] In order to make the above-mentioned objectives, features and advantages of the present disclosure more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which: Figure 1 It is a structural schematic diagram of a delay phase-locked loop circuit in the related art; Figure 2 A schematic diagram of the structure of a delay phase-locked loop circuit provided according to an embodiment of the present disclosure; Figure 3 A schematic diagram of the structure of a voltage-controlled delay line provided according to an embodiment of the present disclosure; Figure 4 A schematic diagram of the structure of a ring oscillator provided according to an embodiment of the present disclosure; Figure 5 A schematic diagram of a flow chart of a lock test method for a delay phase-locked loop circuit provided according to an embodiment of the present disclosure; Figure 6 The present invention is a schematic diagram of the structure of an electronic device provided according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] Various embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.

[0020] Figure 1 FIG. 1 is a schematic diagram of a delay phase-locked loop circuit in the related art. Figure 1As shown, the delay phase-locked loop circuit 100 includes a phase detector (PD) 110, a charge pump (CP) 120, a low pass filter (LPF) 130, and a voltage controlled delay line (VCDL) 140. The phase detector 110 performs phase detection on the reference clock signal Clkin and the feedback phase clock signal ClkFB generated by the voltage controlled delay line 140, and outputs a phase detection signal UP / DOWN corresponding to the phase difference between the two. The charge pump 120 generates a phase difference current corresponding to the phase detection signal UP / DOWN. The low pass filter 130 converts the phase difference current into a voltage signal and generates a control voltage Vctrl'. The voltage controlled delay line 140 generates a multi-stage phase clock signal of the delayed reference clock signal Clkin by adjusting the delay time of the reference clock signal Clkin according to the control voltage Vctrl', and feeds the feedback phase clock signal ClkFB back to the phase detector 110. If the feedback phase clock signal ClkFB delays one cycle of the reference clock signal Clkin, the delay phase-locked loop circuit 100 is in a correctly locked state. If the feedback phase clock signal ClkFB delays n cycles of the reference clock signal Clkin (where n is an integer and n>1), the delay phase-locked loop circuit 100 is in a harmonic locked state. At present, for a ps-level high-precision clock signal, in a simulation experiment environment, a high-precision oscilloscope can be used to display the phase clock signals output by adjacent delay units in the voltage-controlled delay line 140 under a specific program to measure the delay time between the phase clock signals output by adjacent delay units, thereby comparing the delay time with a standard value to determine the locking state of the delay phase-locked loop circuit 100. Obviously, this locking test method can generally only be tested in a laboratory environment, and cannot cover mass production testing, which increases the mass production test cost of the delay phase-locked loop circuit 100.

[0021] Based on this, the embodiments of the present disclosure provide a delay locked loop circuit and a lock test method and related devices thereof, so as to reduce the mass production test cost of the delay locked loop circuit.

[0022] Figure 2 FIG. 1 is a schematic diagram of a delay phase-locked loop circuit according to an embodiment of the present disclosure. Figure 2As shown, the delay phase-locked loop circuit 200 includes a main control loop 300 and a ring oscillator 260. In some embodiments, the main control loop 300 includes a phase detector 210, a charge pump 220, a low-pass filter 230, a voltage-controlled delay line 240, and a bias generating circuit 250. The voltage-controlled delay line 240 includes a plurality of first delay units connected in series (not shown in the figure). The ring oscillator 260 includes a plurality of second delay units connected in a loop (not shown in the figure). The second delay unit has the same circuit structure and load as the first delay unit, and the delay time of the second delay unit is the same as the delay time of the first delay unit.

[0023] In some embodiments, the main control loop 300 controls the locking state of the delay locked loop circuit 200 according to the phase difference between the reference clock signal Clkin and the feedback phase clock signal ClkFB generated by the voltage-controlled delay line 240. In some embodiments, the phase detector 210 performs phase detection on the reference clock signal Clkin and the feedback phase clock signal ClkFB generated by the voltage-controlled delay line 240, and outputs a phase detection signal UP / DOWN corresponding to the phase difference between the two. The charge pump 220 generates a phase difference current corresponding to the phase detection signal UP / DOWN. The low-pass filter 230 converts the phase difference current into a voltage signal and generates a control voltage Vctrl. The bias generation circuit 250 generates a bias voltage VBP / VBN according to the control voltage Vctrl, and provides the bias voltage VBP / VBN to the first delay unit in the voltage-controlled delay line 240 and the second delay unit in the ring oscillator 260 to control the delay time of the first delay unit and the second delay unit. The voltage-controlled delay line 240 generates a multi-stage phase clock signal that delays the reference clock signal Clkin according to the bias voltage VBP / VBN, and feeds back the feedback phase clock signal ClkFB to the phase detector 210 . Figure 3 FIG. 1 is a schematic diagram of the structure of a voltage-controlled delay line provided according to an embodiment of the present disclosure. Figure 3As shown, in some embodiments, the voltage-controlled delay line 240 includes a plurality of first delay units 310 connected in series, namely, a first delay unit 310-1 to a first delay unit 310-N, wherein N is a positive integer and N is an even number. The first delay unit 310-1 to the first delay unit 310-N have the same circuit structure. Taking the first delay unit 310-1 as an example, the first delay unit 310-1 includes a first transistor MP1, a second transistor MP2, a third transistor MN2 and a fourth transistor MN1 connected in series. The first path end (source end) of the first transistor MP1 is connected to the power supply, the second path end (drain end) of the first transistor MP1 is connected to the first path end (source end) of the second transistor MP2, the second path end (drain end) of the second transistor MP2 is connected to the first path end (drain end) of the third transistor MN2, the second path end (source end) of the third transistor MN2 is connected to the first path end (drain end) of the fourth transistor MN1, the second path end (source end) of the fourth transistor MN1 is grounded, the control end (gate end) of the first transistor MP1 receives the bias voltage VBP, the control end (gate end) of the fourth transistor MN1 receives the bias voltage VBN, the first connection node Q of the control end (gate end) of the second transistor MP2 and the control end (gate end) of the third transistor MN2 receives the previous stage phase clock signal output by the previous stage first delay unit, and the second connection node R of the second path end (drain end) of the second transistor MP2 and the first path end (drain end) of the third transistor MN2 provides the current stage phase clock signal. The second connection node R of the previous stage first delay unit 310 is connected to the first connection node Q of the current stage first delay unit 310. The first connection node Q of the first delay unit 310-1 of the first stage receives the reference clock signal Clkin, and the second connection node R of the last delay unit 310-N provides the feedback phase clock signal ClkFB. In some embodiments, the first connection node Q of the first delay unit 310 at the even position in the voltage-controlled delay line 240 is connected in series with the buffer 320 and the transmission gate 330 in sequence, and outputs the even-stage phase clock signal through the transmission gate 330, for example, PHASE <0> 、PHASE <2> 、PHASE <4> 、......、PHASE <n-2>In some embodiments, the first connection node Q of the first delay unit 310 at an odd position in the voltage-controlled delay line 240 is connected in series with the buffer 320 and the uncontrolled high-speed inverter 340, and the inverter 340 outputs an odd-level phase clock signal, for example, PHASE <1> 、PHASE <3> 、PHASE <5> 、......、PHASE <n-1>.

[0024] In some embodiments, the delay locked loop circuit 200 further includes an error prevention circuit 290. The error prevention circuit 290 generates an adjustment signal according to the phase difference between the reference clock signal Clkin and the feedback phase clock signal ClkFB generated by the voltage-controlled delay line 240, so that the phase detector 210 can adjust the phase detection signal UP / DOWN according to the adjustment signal, thereby adjusting the phase difference between the feedback phase clock signal ClkFB and the reference clock signal Clkin, and preventing the delay locked loop circuit 200 from entering an error locking state.

[0025] It can be understood that if the feedback phase clock signal ClkFB is delayed by one cycle of the reference clock signal Clkin and remains unchanged, the delay phase locked loop circuit 200 is in a correct locked state. If the feedback phase clock signal ClkFB is delayed by n cycles of the reference clock signal Clkin (where n is an integer and n>1), the delay phase locked loop circuit 200 is in a harmonic locked state.

[0026] In some embodiments, the ring oscillator 260 outputs an oscillation signal Fosc according to the bias voltage VBP / VBN, so as to calculate the delay time of the second delay unit according to the frequency of the oscillation signal Fosc, compare the delay time of the second delay unit with the standard value, and determine the locking state of the delay phase-locked loop circuit 200 according to the comparison result. It should be noted that the standard value is the delay time of the first delay unit when the delay phase-locked loop circuit 200 is in a correctly locked state. That is, the standard value is the quotient of the period T of the reference clock signal Clkin and the number of the first delay units in the voltage-controlled delay line 240. For example, again referring to Figure 3 , the standard value is T / N. Figure 4 FIG. 1 is a schematic diagram of the structure of a ring oscillator provided according to an embodiment of the present disclosure. Figure 4 As shown, in some embodiments, the ring oscillator 260 includes a multi-stage second delay unit 410 connected in a loop, namely, the second delay unit 410-1 to the second delay unit 410-P, where P is a positive integer and an odd number. The second delay unit 410-1 to the second delay unit 410-P have the same circuit structure. And the second delay unit 410 has the same circuit structure and load as the first delay unit 310. In some embodiments, in order to ensure good matching, on the layout, the second delay unit 410 of the ring oscillator 260 is placed together with the first delay unit 310 of the voltage-controlled delay line 240 and the layout is matched. Taking the second delay unit 410-1 as an example, the second delay unit 410-1 includes a first transistor MP1, a second transistor MP2, a third transistor MN2 and a fourth transistor MN1 connected in series. The first path end (source end) of the first transistor MP1 is connected to the power supply, the second path end (drain end) of the first transistor MP1 is connected to the first path end (source end) of the second transistor MP2, the second path end (drain end) of the second transistor MP2 is connected to the first path end (drain end) of the third transistor MN2, the second path end (source end) of the third transistor MN2 is connected to the first path end (drain end) of the fourth transistor MN1, the second path end (source end) of the fourth transistor MN1 is grounded, the control end (gate end) of the first transistor MP1 receives the bias voltage VBP, the control end (gate end) of the fourth transistor MN1 receives the bias voltage VBN, the first connection node Q of the control end (gate end) of the second transistor MP2 and the control end (gate end) of the third transistor MN2 receives the output signal of the second delay unit of the previous stage, and the second connection node R of the second path end (drain end) of the second transistor MP2 and the first path end (drain end) of the third transistor MN2 provides the output signal of the second delay unit of the current stage. The second connection node R of the second delay unit 410 of the previous stage is connected to the first connection node Q of the second delay unit 410 of the current stage. The first connection node Q of the first-stage second delay unit 410-1 is connected to the second connection node R of the last-stage second delay unit 410-P. The second connection node R of the last-stage second delay unit 410-P provides an oscillation signal Fosc. In some embodiments, the second connection node R of the previous-stage second delay unit 410 and the first connection node Q of the next-stage second delay unit 410 in the adjacent second delay units 410 in the ring oscillator 260 are both connected to the uncontrolled high-speed inverter 420. It can be understood that the frequency f1 of the oscillation signal Fosc generated by the ring oscillator 260 can be expressed as follows: f1=1 / (2*P*Td) (1) Wherein, Td is the delay time of each second delay unit 410 when locked, and P is the number of second delay units 410 in the ring oscillator 260. It is easy to understand that in the chip mass production test stage, the frequency f1 of the oscillation signal Fosc generated by the ring oscillator 260 can be measured, and the delay time Td of each second delay unit 410 when locked can be calculated by formula (1). Since the second delay unit 410 in the ring oscillator 260 and the first delay unit 310 in the voltage-controlled delay line 240 have the same circuit structure and load, it can be considered that the second delay unit 410 in the ring oscillator 260 and the first delay unit 310 in the voltage-controlled delay line 240 have the same delay time. The calculated delay time Td of the second delay unit 410 when locked is compared with a standard value (for example, T / N). If the delay time Td is equal to the standard value, the delay phase-locked loop circuit 200 is in a correctly locked state. If the delay time Td is equal to the product of the standard value and n (where n is an integer and n>1), the delay phase-locked loop circuit 200 is in a harmonic locked state.

[0027] In some embodiments, considering the frequency limit of the signal that can be output by the general purpose input and output (GPIO) interface, the delay phase-locked loop circuit 200 further includes a frequency divider 270 and a GPIO interface 280. The frequency divider 270 is connected to the ring oscillator 260, and performs frequency division processing on the oscillation signal Fosc generated by the ring oscillator 260 (for example, the frequency division factor of the frequency divider 270 is M, M is a positive integer and M>1). The GPIO interface 280 is connected to the frequency divider 270, and outputs the oscillation signal Fclkout after the frequency division processing. For example, referring again to Figure 4 , the frequency f2 of the oscillation signal Fclkout after frequency division can be expressed as follows: f2=f1 / M=1 / (2*P*Td*M) (2) Wherein, Td is the delay time of each second delay unit 410 when locked, P is the number of second delay units 410 in the ring oscillator 260, and M is the frequency division factor of the frequency divider 270. It is easy to understand that in the chip mass production test stage, the frequency f2 of the oscillation signal Fclkout after the frequency division process can be measured, and the delay time Td of each second delay unit 410 when locked can be calculated by formula (2). Since the second delay unit 410 in the ring oscillator 260 and the first delay unit 310 in the voltage-controlled delay line 240 have the same circuit structure and load, it can be considered that the second delay unit 410 in the ring oscillator 260 and the first delay unit 310 in the voltage-controlled delay line 240 have the same delay time. The calculated delay time Td of the second delay unit 410 when locked is compared with the standard value (for example, T / N). If the delay time Td is equal to the standard value, the delay phase-locked loop circuit 200 is in a correctly locked state. If the delay time Td is equal to the product of the standard value and n (where n is an integer and n>1), the delay phase-locked loop circuit 200 is in a harmonic locked state. In an example, the frequency f2 of the oscillation signal Fclkout after frequency division is 40 MHz, the number P of the second delay units 410 in the ring oscillator 260 is 9, and the frequency division factor M of the frequency divider 270 is 16. The delay time Td of the second delay unit 410 when locked can be calculated to be 86.81 ps. The frequency of the reference clock signal Clkin is 180 MHz, and the number N of the first delay units 310 in the voltage-controlled delay line 240 is 64. The standard value, that is, the delay time generated by each first delay unit 310 in the correctly locked state, is approximately 86.8 ps. Therefore, it can be determined that the calculated delay time Td is equal to the standard value, and the delay phase-locked loop circuit 200 is in a correctly locked state.

[0028] Figure 5 The present invention is a flowchart of a lock test method for a delay phase-locked loop circuit provided according to an embodiment of the present disclosure. The delay phase-locked loop circuit includes a main control loop and a ring oscillator. The main control loop includes a voltage-controlled delay line. The voltage-controlled delay line includes a plurality of first delay units connected in series. The voltage-controlled delay line is used to generate a plurality of phase clock signals that delay a reference clock signal according to a bias voltage. The main control loop is used to control the lock state of the delay phase-locked loop circuit according to the phase difference between the reference clock signal and the feedback phase clock signal generated by the voltage-controlled delay line. The ring oscillator includes a plurality of second delay units connected in a loop. The ring oscillator outputs an oscillation signal according to the bias voltage. Reference Figure 5 , the locking test method includes steps S510 to S520.

[0029] In step S510, the delay time of the second delay unit is calculated according to the frequency of the oscillation signal.

[0030] In step S520, the delay time of the second delay unit is compared with a standard value, and the locking state of the delay phase-locked loop circuit is determined according to the comparison result, wherein the standard value is the delay time of the first delay unit when the delay phase-locked loop circuit is in a correctly locked state.

[0031] Since the process of determining the locking state of the delay locked loop circuit using the locking test method in the embodiment of the present disclosure has been described in detail above, it will not be repeated here.

[0032] The present disclosure also provides an electronic device, such as Figure 6 As shown, it includes a memory 620, a processor 610, and a program stored in the memory 620 and executable on the processor 610. When the program is executed by the processor 610, each process of each embodiment of the above-mentioned locking test method can be implemented, and the same technical effect can be achieved. To avoid repetition, it will not be described here.

[0033] Those skilled in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructions, or by controlling related hardware through instructions, and the instructions can be stored in a computer-readable storage medium and loaded and executed by a processor. To this end, the embodiments of the present disclosure also provide a storage medium, on which a computer program or instruction is stored, and when the computer program or instruction is executed by the processor, each process of each embodiment of the above lock test method can be implemented.

[0034] Since the instructions stored in the storage medium can execute the steps in the lock test method provided in the embodiment of the present disclosure, the beneficial effects that can be achieved by the lock test method provided in the embodiment of the present disclosure can be achieved. For details, please refer to the previous embodiment, which will not be repeated here. The specific implementation of each of the above operations can be referred to the previous embodiment, which will not be repeated here.

[0035] In summary, in the delay phase-locked loop circuit of the embodiment of the present disclosure, the main control loop includes a voltage-controlled delay line, the voltage-controlled delay line includes a plurality of first delay units connected in series, the voltage-controlled delay line is used to generate a multi-stage phase clock signal of a delayed reference clock signal according to a bias voltage, the main control loop is used to control the locking state of the delay phase-locked loop circuit according to the phase difference between the reference clock signal and the feedback phase clock signal generated by the voltage-controlled delay line, the ring oscillator includes a plurality of second delay units connected in a loop, which are used to output an oscillation signal according to the bias voltage, so as to calculate the delay time of the second delay unit according to the frequency of the oscillation signal, and the second delay unit is used to generate a multi-stage phase clock signal of a delayed reference clock signal according to the bias voltage. The delay time of the unit is compared with a standard value, and the locking state of the delay phase-locked loop circuit is determined according to the comparison result. The standard value is the delay time of the first delay unit when the delay phase-locked loop circuit is in a correctly locked state. In this way, in the mass production test stage, it is only necessary to test the frequency of the oscillation signal output by the ring oscillator to calculate the delay time of the second delay unit, that is, to obtain the delay time of the first delay unit in the current voltage-controlled delay line, and compare the calculated delay time of the second delay unit with the standard value. According to the comparison result, the locking state of the delay phase-locked loop circuit can be determined, which reduces the mass production test cost of the delay phase-locked loop circuit.

[0036] In addition, by adding a simple circuit structure (i.e., a ring oscillator) to the delay-locked loop circuit, it is possible to determine whether the delay-locked loop circuit is correctly locked during the testing phase of the chip production process. Chips that fail to function due to process deviations that exceed the adjustment range can be discovered early, thereby reducing subsequent chip production costs.

[0037] Finally, it should be noted that: Obviously, the above embodiments are only examples for clearly illustrating the present disclosure, and are not intended to limit the implementation methods. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from this are still within the scope of protection of the present disclosure.

Claims

1. A delay locked loop circuit, comprising: A main control loop, comprising a voltage-controlled delay line, the voltage-controlled delay line comprising a plurality of first delay units connected in series, the voltage-controlled delay line being used to generate a plurality of phase clock signals that delay a reference clock signal according to a bias voltage, the main control loop being used to control a locking state of the delay-locked loop circuit according to a phase difference between the reference clock signal and a feedback phase clock signal generated by the voltage-controlled delay line; A ring oscillator comprises a multi-stage second delay unit connected in a loop, which is used to output an oscillation signal according to the bias voltage, so as to calculate the delay time of the second delay unit according to the frequency of the oscillation signal, compare the delay time of the second delay unit with a standard value, and determine the locking state of the delay phase-locked loop circuit according to the comparison result, wherein the standard value is the delay time of the first delay unit when the delay phase-locked loop circuit is in a correctly locked state.

2. The delay locked loop circuit according to claim 1, wherein: The second delay unit has the same circuit structure and load as the first delay unit, and the delay time of the second delay unit is the same as the delay time of the first delay unit.

3. The delay locked loop circuit according to claim 1, wherein: The delay locked loop circuit also includes: A frequency divider, connected to the ring oscillator, for performing frequency division processing on the oscillation signal; A universal input-output interface is connected to the frequency divider and is used to output the oscillation signal after the frequency division processing, so as to calculate the delay time of the second delay unit according to the frequency of the oscillation signal after the frequency division processing, compare the delay time of the second delay unit with the standard value, and determine the locking state of the delay phase-locked loop circuit according to the comparison result.

4. The delay locked loop circuit according to claim 1 or 3, wherein: If the delay time of the second delay unit is equal to the standard value, the delay phase-locked loop circuit is in a correctly locked state; If the delay time of the second delay unit is equal to the product of the standard value and the first value, the delay phase-locked loop circuit is in a harmonic locking state, and the first value is an integer and greater than 1; The standard value is the quotient of the period of the reference clock signal and the number of first delay units in the voltage-controlled delay line.

5. The delay locked loop circuit according to claim 1, wherein: The main control loop also includes: A phase detector, used to perform phase detection on the reference clock signal and the feedback phase clock signal generated by the voltage-controlled delay line, and output a phase detection signal corresponding to the phase difference between the reference clock signal and the feedback phase clock signal generated by the voltage-controlled delay line; A charge pump, used for generating a phase difference current corresponding to the phase detection signal; A low-pass filter, used for converting the phase difference current into a voltage signal and generating a control voltage; The bias generating circuit is used to generate the bias voltage according to the control voltage, and provide the bias voltage to the first delay unit and the second delay unit to control the delay time of the first delay unit and the second delay unit.

6. The delay locked loop circuit according to claim 1, wherein: The first delay unit comprises: A first transistor to a fourth transistor connected in series, wherein a first channel end of the first transistor is connected to a power supply, a second channel end of the first transistor is connected to a first channel end of the second transistor, a second channel end of the second transistor is connected to a first channel end of the third transistor, a second channel end of the third transistor is connected to a first channel end of the fourth transistor, and a second channel end of the fourth transistor is grounded, a control end of the first transistor and a control end of the fourth transistor receive the bias voltage, a first connection node of the control end of the second transistor and a control end of the third transistor receive a previous stage phase clock signal output by a previous stage first delay unit, and a second connection node of the second channel end of the second transistor and the first channel end of the third transistor provides a current stage phase clock signal; The first connection node of the first-stage first delay unit receives the reference clock signal, and the second connection node of the last-stage first delay unit provides the feedback phase clock signal.

7. The delay locked loop circuit according to claim 1, wherein: The second delay unit comprises: A first transistor to a fourth transistor connected in series, wherein a first channel end of the first transistor is connected to a power supply, a second channel end of the first transistor is connected to a first channel end of the second transistor, a second channel end of the second transistor is connected to a first channel end of the third transistor, a second channel end of the third transistor is connected to a first channel end of the fourth transistor, a second channel end of the fourth transistor is grounded, a control end of the first transistor and a control end of the fourth transistor receive the bias voltage, a first connection node of the control end of the second transistor and a control end of the third transistor receive an output signal of a second delay unit of a previous stage, and a second connection node of the second channel end of the second transistor and the first channel end of the third transistor provides an output signal of a second delay unit of a current stage; The first connection node of the first-stage second delay unit is connected to the second connection node of the last-stage second delay unit, and the second connection node of the last-stage second delay unit provides the oscillation signal.

8. A lock test method for a delay locked loop circuit, the delay locked loop circuit comprising a main control loop and a ring oscillator, the main control loop comprising a voltage-controlled delay line, the voltage-controlled delay line comprising a plurality of first delay units connected in series, the voltage-controlled delay line being used to generate a plurality of phase clock signals that delay a reference clock signal according to a bias voltage, the main control loop being used to control a lock state of the delay locked loop circuit according to a phase difference between the reference clock signal and a feedback phase clock signal generated by the voltage-controlled delay line, the ring oscillator comprising a plurality of second delay units connected in a loop, the ring oscillator outputting an oscillation signal according to the bias voltage, comprising: Calculating the delay time of the second delay unit according to the frequency of the oscillation signal; The delay time of the second delay unit is compared with a standard value, and the locking state of the delay phase-locked loop circuit is determined according to the comparison result, wherein the standard value is the delay time of the first delay unit when the delay phase-locked loop circuit is in a correctly locked state.

9. A clock generation chip, comprising: A delay locked loop circuit as claimed in any one of claims 1 to 7.

10. An electronic device, comprising: A clock generating chip as claimed in claim 9.

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