Eight-channel input and output data acquisition device

Abstract

The invention discloses an eight-channel input and output data acquisition device which comprises an analog signal input interface, a first signal conditioning module, an A / D conversion module, an EMIF circuit, a DSP processing module, an SPI output circuit, a D / A conversion module, a second signal conditioning module and an analog output interface. The analog signal input interface receives analog signals of eight channels, the analog signals are filtered by the first signal conditioning module and then are transmitted to the A / D conversion module through the EMIF circuit, the A / D conversion module carries out analog-to-digital conversion, digital signals are transmitted to the DSP processing module through the EMIF circuit, the DSP processing module processes the digital signals, and the digital signals are transmitted to the analog-to-digital conversion module through the EMIF circuit. The processed eight-channel digital signal is transmitted to a D / A conversion module through an SPI output circuit, the D / A conversion module performs analog-to-digital conversion, and an analog signal is amplified and subjected to low-pass filtering through a second signal conditioning module and then is output to an analog output interface; high-speed data processing and analysis are achieved, the real-time requirement is met, a built-in FPGA is not needed, development and debugging are easy, and the development and maintenance cost is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of data acquisition, and in particular to an eight-channel input and output data acquisition device. Background Art

[0002] In modern industrial control and scientific research, it is often necessary to collect and process multiple physical quantities simultaneously. Although there are many types of data acquisition devices on the market, they often cannot fully meet the needs of specific application scenarios in terms of the number of channels, input and output flexibility, development complexity and cost-effectiveness.

[0003] For example, some data acquisition devices have built-in FPGA and DSP processing modules. The built-in FPGA is used to achieve high-speed real-time data processing, so that the data acquisition equipment can quickly process a large amount of sensor data and perform data filtering, sampling, calculation and conversion in real time. The DSP processing module is used to process the data collected by the sensors in real time according to customer needs. Therefore, for the needs of multiple channels and high-speed processing, existing data acquisition devices usually have built-in FPGA and DSP processing modules at the same time.

[0004] However, when the data acquisition device has built-in FPGA and DSP processing modules, the developer is required to have the ability to develop C language and Verilog at the same time. The program complexity is high, and the development complexity and cost are high. At the same time, due to the built-in FPGA, the cost of the data acquisition device increases a lot, and the FPGA and DSP processing modules need to be debugged together after they are started and closed, which increases the development time and maintenance cost. Other devices have insufficient compatibility in input and output types and cannot meet the needs of complex application scenarios.

[0005] Therefore, there is an urgent need for a data acquisition device that can achieve high-speed real-time data processing and is easy to develop and debug. Summary of the invention

[0006] To solve the above problems, the purpose of the present invention is to provide an eight-channel input and output data acquisition device, which can simultaneously collect multiple physical quantities and can simultaneously collect and output data from eight channels, thereby improving the efficiency and speed of data acquisition; without the need for a built-in FPGA, high-speed data processing and analysis can be achieved, while still meeting real-time requirements, and development and debugging are simple, thereby reducing development and maintenance costs.

[0007] The technical solution adopted by the present invention is: The present invention provides an eight-channel input and output data acquisition device, comprising an analog signal input interface, a first signal conditioning module, an A / D conversion module, an EMIF circuit, a DSP processing module, an SPI output circuit, a D / A conversion module, a second signal conditioning module and an analog output interface connected in sequence; The analog signal input interface receives eight-channel analog signals. The analog signals are filtered by the first signal conditioning module and then transmitted to the A / D conversion module through the EMIF circuit. The A / D conversion module converts the eight-channel analog signals into eight-channel digital signals. The digital signals are transmitted to the DSP processing module through the EMIF circuit. The DSP processing module collects, processes and analyzes the digital signals. The processed eight-channel digital signals are transmitted to the D / A conversion module through the SPI output circuit. The D / A conversion module converts the eight-channel digital signals into eight-channel analog signals. The analog signals are amplified and low-pass filtered by the second signal conditioning module and then output to the analog output interface to realize the output of eight-channel signals.

[0008] Further, the first signal conditioning module includes eight ESD protection and signal filtering circuits, and the analog signals of the eight channels flow into the corresponding ESD protection and signal filtering circuits respectively, and the structure and composition of each ESD protection and signal filtering circuit are the same, wherein one ESD protection and signal filtering circuit includes a diode D14, a filter U25, resistors R81, R63, R79, R80, operational amplifiers U26A, U26B, and capacitors C44, C50, C126, C129, C127, and C128, and the filter U25 is composed of capacitors and inductors, and the structure and composition of each ESD protection and signal filtering circuit are the same; The cathode of diode D14 is connected to the analog input port ANA_IN_P1 and the filter U25, and the anode is analog grounded. Pin 1 of filter U25 is connected to the cathode of diode D14, pin 2 is analog grounded, pin 3 is connected to one end of resistor R81, and the other end of R81 is connected to the non-inverting input of operational amplifier U26A. The inverting input of operational amplifier U26A is connected to one end of resistor R63, and the other end of resistor R63 is connected to the output of operational amplifier U26A. The positive power supply pin of operational amplifier U26A is connected to a 5V analog voltage source, and the negative power supply pin is grounded. The output end of amplifier U26A is connected to one end of resistor R79, the other end of resistor R79 is connected to one end of capacitor C44 and one end of resistor R80, the other end of capacitor C44 is connected to the inverting input and output ends of operational amplifier U26B, the other end of resistor R80 is connected to one end of capacitor C50 and the non-inverting input end of operational amplifier U26B, the other end of capacitor C50 is analog grounded, the positive power supply pin (pin 8) of operational amplifier U26B is connected to a 5V analog voltage source, the negative power supply pin is grounded, and the output end of operational amplifier U26B is connected to AD module input interface ADC_IN1.

[0009] Furthermore, the A / D conversion module uses the AD7606 chip, the input pins V1-V8 of the AD7606 chip are respectively connected to eight ESD protection and signal filtering circuits, the V1GND-V8 GND pins of the AD7606 chip are analog grounded, the CONVST_A and CONVST_B of the AD7606 chip are connected, and the PAR / SER / BYTE_SEL, RANGE, CS, RD / SCLK, PEF_SELECT, The STBY and RESET pins are connected to one end of R208, R845, R857, R856, R852 and R854 respectively, and the other ends of R208, R845, R857, R856, R852, R854 and R855 are connected to the AVDD_3V3 analog power supply. One end of R208, R845 and R852 is also connected to the resistors R215, R846 and R853 respectively and then analog grounded. The AVCC0, AVCC1, AVCC2 and AVCC3 pins of the AD7606 chip are connected to each other and then to the AVCC_5V_P power supply. One end of the capacitors C162, C163, C160, C161, C158 and C159 are connected to the AVCC_5V_P power supply and the other end is analog grounded. The DB0-DB15 pins of the AD7606 chip are connected to the resistor array. The REFCAPA and REFCAPB pins of the AD7606 chip are connected to one end of capacitor C48, and the other end of capacitor C48 is analog grounded. The REFGND0 and REFGND1 pins of the AD7606 chip are analog grounded. The REFIN / REFOUT pin of the AD7606 chip is connected to one end of capacitor C52 and ADC_VERF, and the other end of capacitor C52 is analog grounded. The REGND0 and REGND1 pins of the AD7606 chip are connected to one end of capacitors C657 and C51 respectively, and the other end of capacitors C657 and C51 are analog grounded. The VDRIVE pin of the AD7606 chip is connected to one end of capacitors C53 and C656 and AVDD_3V3, and the other end of capacitors C53 and C656 are analog grounded. The AGND0-AGND5 of the AD7606 chip are analog grounded.

[0010] Furthermore, the EMIF circuit adopts the SOM TL665x chip U16D. U16D has a total of 50 pins from C1 to C50, among which C1 is used as the DSP_NMIZ pin for the non-masked interrupt of the controller, C3 is used as the DSP_HOUT pin and connected to the test point TP4 for outputting the signal, C5 and C7 pins are used as the DSP_CORESEL0 and DSP_CORESEL1 pins for selecting a specific core or working mode, C11 pin is used as the DSP_LRESETZ pin for the reset function of the DSP, C12 pin is grounded, C13 pin is used as the DSP_RESETSTAT pin for indicating the reset status, and C15 is used as the DSP_RESETSTAT pin for indicating the reset status. As DSP_LRESETNMIENZ pin, it is used to control the reset and non-maskable interrupt function of DSP. C17 is used as DSP_RESETZ pin for reset. C19 pin is used as DSP_BOOTCOMPLETE pin and connected to test point TP11 to indicate the startup status of DSP. C21 pin is grounded. C14, C16, C18, C20, C22, C24, C26, C28, C30, C32, C34, C36, C38, C40, C42 and C44 pins are used as DSP_EMIFSD00-D15 pins to receive data transmitted by AD7606. C23, C25, C27, C29, C31, C33, C35, C37, C39, C41, C43, C45, C47, C46, ​​C48 and C50 are used as DSP_EMIFSA00-A15 pins. DSP_EMIFSA00-A15 represents the 16 pins of the EMIF address bus, which are used to read data from external devices through the EMIF bus and then put the data into memory for subsequent processing or use.

[0011] Furthermore, the SPI output circuit adopts the SOM TL665x chip U16E. U16E has D1-D50 pins, D3 and D5 are used as DSP_TIMI0 and DSP_TIMI1 pins for DSP timer and timing functions, D7 and D9 are used as DSP_TIMO0 and DSP_TIMO1 pins for DSP timer output functions, D13 and D15 are used as DSP_SDA and DSP_SCL pins respectively for external communication, D19, D21, D29 and D31 pins are used as DSP_UART1_RST, DSP_UART1_TXD, DSP_UART_RST and DSP_UART_TXD pins respectively, UART is a debugging serial port, UART1 is a 485 communication interface, D23, D25, D33 and D35 are used as DSP_UART1_CTS and DSP_UART1_RTS, DSP_UART_CTS and DSP_UART_RTS pins respectively, which are used for serial communication control signals. D39 and D41 pins are used as DSP_SSPMOS1 and DSP_SSPMOS0 pins, which are used for serial or parallel data transmission of DSP processing module; D43, D45 and D47 pins are used as DSP_SSPCK, DSP_SSPCS1 and DSP_ SSPCS0 pins respectively, which are used for clock signals of serial synchronous interface and control communication with external devices. DSP_SSPCS1 and DSP_ SSPCS0 are chip select pins, and the software driver controls the level of each pin at the corresponding time through timing; D48 and D50 pins are used as SYS_nRESET and SYS_IO interfaces respectively, which are used for system reset and processing system input and output respectively. The other pins of U16E are all grounded.

[0012] Furthermore, the D / A conversion module adopts the AD5676BRUZ chip, and the SCLK, SDI, SDO, SYNC*, LDAC*, GAIN, RESET* and RSTSEL pins of the AD5676BRUZ chip are respectively connected to resistors R222, R223, R224, R225, R226, R227, R228 and R273, and the SDI, LDAC*, GAIN, RESET* and RSTSEL pins of the AD5676BRUZ chip are respectively connected to one end of resistors R232, R233, R234, R236 and R235, and the other ends of resistors R232, R233, R234, R236 and R235 are connected to VDD_1 VB_BRD, the VDD pin of the AD5676BRUZ chip is connected to one end of the capacitor C167 and one end of C165, and the other end of C167 and C165 is analog grounded. The VL pin of the AD5676BRUZ chip is connected to one end of the capacitor C168 and one end of C169, and the other end of C168 and C169 is analog grounded. The VOUT0-VOUT7 pins of the AD5676BRUZ chip are used as the DC output interface of eight channels. The VREF interface of the AD5676BRUZ chip is connected to one end of the resistor R274, and the other end of the resistor R274 is connected to one end of the capacitor C166 and VREF_2V5A. The other end of the capacitor C166 is analog grounded, and the GND interface of the AD5676BRUZ chip is analog grounded.

[0013] Further, the second signal conditioning module includes eight amplifying and filtering circuits, each of which has the same structure and composition, wherein one of the amplifying and filtering circuits includes resistors R277, R241, R278, R242, R244, R243, capacitors C183, C184, operational amplifiers U52A and U52B; One end of resistor R277 is connected to VREF_2V5A power supply, and the other end is connected to one end of resistor R242 and the inverting input end of operational amplifier U52A, the other end of resistor R242 is connected to the output end of operational amplifier U52A and one end of resistor R244, one end of resistor R241 is connected to the digital signal output interface of D / A conversion module, the other end of resistor R241 is connected to one end of resistor R278 and the non-inverting input end of operational amplifier, the other end of resistor R278 is analog grounded, the positive power supply pin of operational amplifier U52A is connected to AVCC_5V_P power supply, and the negative power supply pin of operational amplifier U52A is connected to AVCC_5V _N is grounded, the other end of resistor R244 is connected to one end of capacitor C183 and one end of resistor R243, the other end of capacitor C183 is connected to the inverting input of operational amplifier U52B and the output of operational amplifier U52B, the other end of resistor R243 is connected to one end of capacitor C184 and the non-inverting input of operational amplifier U52B, the other end of capacitor C184 is analog grounded, the positive power supply pin of operational amplifier U52B is connected to AVCC_5V_P power supply, the negative power supply pin of operational amplifier U52B is connected to AVCC_5V_N ground, and the output of operational amplifier U52B is connected to analog output interface ANA_OUT.

[0014] Furthermore, the DSP processing module specifically adopts a TI-C6657 microcontroller.

[0015] Beneficial effects of the present invention: 1. The data acquisition device of the present invention supports a large number of channels, can collect multiple physical quantities at the same time, and can collect and output data from eight channels at the same time, thereby improving the efficiency and speed of data acquisition. In addition, the present invention can realize high-speed data processing and analysis, meet real-time requirements, does not require built-in FPGA, is simple to develop and debug, and reduces development and maintenance costs; 2. The input and output types of the present invention are highly compatible and can be compatible with a variety of analog signals, such as vibration signals, temperature signals, sound signals, etc., and the collection of input signals can be realized by simply configuring the corresponding sensors to access the input channels. The output signals are also similar and can adapt to a variety of different types of signal sources and loads, thus expanding the application scope of the present device; 3. The data acquisition device of the present invention effectively improves the quality and stability of input signals and output signals and reduces noise and interference by setting the first signal conditioning module and the second signal conditioning module; 4. The present invention designs the circuits of the A / D conversion module and the D / A conversion module to ensure the precision and accuracy of data conversion; 5. The present invention designs an EMIF circuit, which mainly realizes data communication from AD7606 to the DSP processing module. Based on the parallel communication protocol, the digital signal output by AD7606 can be quickly transmitted to the DSP processing module to process the digital signal. The SPI circuit is designed to realize the transmission of the data processed by the DSP processing module to AD5676 through the SPI interface, thereby converting the data from digital signal to analog signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a circuit diagram of a first signal conditioning module of the present invention; Figure 2 A / D conversion module circuit diagram of the present invention; Figure 3 An EMIF circuit diagram for connecting the present invention and a DSP processing module; Figure 4 SPI output circuit diagram for connecting the present invention to a DSP processing module; Figure 5 The D / A conversion module circuit diagram of the present invention; Figure 6 is a circuit diagram of a second signal conditioning module of the present invention; Figure 7 It is the overall architecture diagram of the data acquisition device of the present invention; Figure 8 It is a working flow chart of the data acquisition device of the present invention. DETAILED DESCRIPTION

[0017] In order to make the purpose, technical solution and advantages of the present invention more clear, the technical solution of the present invention will be clearly and completely described below in conjunction with the accompanying drawings and a preferred implementation manner.

[0018] refer to Figure 8 , an embodiment of the present invention provides an eight-channel input and output data acquisition device, comprising an analog signal input interface, a first signal conditioning module, an A / D conversion module, an EMIF circuit, a DSP processing module, an SPI output circuit, a D / A conversion module, a second signal conditioning module and an analog output interface connected in sequence; The analog signal input interface receives eight channels of analog signals, which can be analog values ​​of physical quantities such as voltage, current, and temperature. The analog signals are filtered by the first signal conditioning module and transmitted to the A / D conversion module through the EMIF circuit. The A / D conversion module converts the eight-channel analog signals into eight-channel digital signals. The digital signals are transmitted to the DSP processing module through the EMIF circuit. The DSP processing module collects, processes and analyzes the digital signals. The processed eight-channel digital signals are transmitted to the D / A conversion module through the SPI output circuit. The D / A conversion module converts the eight-channel digital signals into eight-channel analog signals. The analog signals are amplified and low-pass filtered by the second signal conditioning module and then output to the analog output interface to realize the output of eight-channel signals.

[0019] The first signal conditioning module of the present invention includes eight ESD protection and signal filtering circuits, and the analog signals of the eight channels flow into the corresponding ESD protection and signal filtering circuits respectively. Figure 1 , one of the ESD protection and signal filtering circuits includes a diode D14, a filter U25, resistors R81, R63, R79, R80, operational amplifiers U26A, U26B, and capacitors C44, C50, C126, C129, C127, and C128, the filter U25 is composed of capacitors and inductors, and the structure and composition of each ESD protection and signal filtering circuit are the same; The cathode of diode D14 is connected to the analog input port ANA_IN_P1 and the filter U25, and the anode is analog grounded. Pin 1 of filter U25 is connected to the cathode of diode D14, pin 2 is analog grounded, pin 3 is connected to one end of resistor R81, and the other end of R81 is connected to the non-inverting input terminal (pin 3) of operational amplifier U26A. The inverting input terminal (pin 2) of operational amplifier U26A is connected to one end of resistor R63, and the other end of resistor R63 is connected to the output terminal (pin 1) of operational amplifier U26A. The positive power supply pin (pin 8) of operational amplifier U26A is connected to a 5V analog voltage source, and the negative power supply pin (pin 4) is grounded. The output end (pin 1) of U26A is connected to one end of resistor R79, the other end of resistor R79 is connected to one end of capacitor C44 and one end of resistor R80, the other end of capacitor C44 is connected to the inverting input end (pin 6) and output end (pin 7) of operational amplifier U26B, the other end of resistor R80 is connected to one end of capacitor C50 and the non-inverting input end (pin 5) of operational amplifier U26B, the other end of capacitor C50 is analog grounded, the positive power supply pin (pin 8) of operational amplifier U26B is connected to a 5V analog voltage source, the negative power supply pin (pin 4) is grounded, and the output end (pin 7) of operational amplifier U26B is connected to the AD module input interface ADC_IN1. The filter U25 of the first signal conditioning module filters the input analog signal, the operational amplifiers U26A and U26B amplify the analog signal, and the diode D14 is responsible for electrostatic protection (ESD protection) to improve the quality and stability of the signal.

[0020] refer to Figure 2The A / D conversion module of the present invention adopts the AD7606 chip. The input pins V1-V8 of the AD7606 chip are respectively connected to eight ESD protection and signal filtering circuits. The ADC signals of the eight channels flow into the input pins V1-V8 respectively. The V1GND-V8 GND pins of the AD7606 chip are all analog grounded. The CONVST_A and CONVST_B of the AD7606 chip are connected. The CONVST_A and CONVST_B pins are simultaneously connected to a trigger signal pin to synchronously sample all channels. The PAR / SER / BYTE_SEL, RANGE, CS, RD / SCLK, PEF_SELECT, The STBY and RESET pins are connected to one end of R208, R845, R857, R856, R852 and R854 respectively, and the other ends of R208, R845, R857, R856, R852, R854 and R855 are connected to the AVDD_3V3 analog power supply. One end of R208, R845 and R852 is also connected to the resistors R215, R846 and R853 respectively and then analog grounded. The AVCC0, AVCC1, AVCC2 and AVCC3 pins of the AD7606 chip are connected to each other and then to the AVCC_5V_P power supply. One end of the capacitors C162, C163, C160, C161, C158 and C159 are connected to the AVCC_5V_P power supply and the other end is analog grounded. The DB0-DB15 pins of the AD7606 chip are connected to the resistor array. The REFCAPA and REFCAPB pins of the AD7606 chip are connected to one end of capacitor C48, and the other end of capacitor C48 is analog grounded. The REFGND0 and REFGND1 pins of the AD7606 chip are analog grounded. The REFIN / REFOUT pin of the AD7606 chip is connected to one end of capacitor C52 and ADC_VERF, and the other end of capacitor C52 is analog grounded. The REGND0 and REGND1 pins of the AD7606 chip are connected to one end of capacitors C657 and C51 respectively, and the other end of capacitors C657 and C51 are analog grounded. The VDRIVE pin of the AD7606 chip is connected to one end of capacitors C53 and C656 and AVDD_3V3, and the other end of capacitors C53 and C656 are analog grounded. The AGND0-AGND5 of the AD7606 chip are analog grounded.

[0021] The eight-channel analog signals enter from the ADC input pins V1-V8 of the A / D conversion module, and the A / D conversion module converts the eight analog signals into digital signals.

[0022] refer to Figure 3The EMIF circuit of the present invention adopts the SOM TL665x chip U16D. U16D has a total of 50 pins C1-C50, wherein C1 is used as the DSP_NMIZ pin for the non-masked interrupt of the controller, C3 is used as the DSP_HOUT pin and connected to the test point TP4 for outputting signals, C5 and C7 pins are used as the DSP_CORESEL0 and DSP_CORESEL1 pins for selecting a specific core or working mode, C11 pin is used as the DSP_LRESETZ pin for the reset function of the DSP, C12 pin is grounded, C13 pin is used as the DSP_RESETSTAT pin for indicating the reset state, and C15 is used as the D The SP_LRESETNMIENZ pin is used to control the reset and non-maskable interrupt (NMI) functions of the DSP. C17 is used as the DSP_RESETZ pin for reset. The C19 pin is used as the DSP_BOOTCOMPLETE pin and connected to the test point TP11 to indicate the startup status of the DSP. The C21 pin is grounded. The C14, C16, C18, C20, C22, C24, C26, C28, C30, C32, C34, C36, C38, C40, C42 and C44 pins are used as the DSP_EMIFSD00-D15 pin to receive data transmitted by AD7606. C23, C25, C27, C29, C31, C33, C35, C37, C39, C41, C43, C45, C47, C46, ​​C48 and C50 are used as DSP_EMIFSA00-A15 pins. DSP_EMIFSA00-A15 represents 16 pins of the EMIF address bus, which are used to read data from external devices through the EMIF bus and then put the data into the memory for subsequent processing or use. The DSP processing module receives the eight-channel digital signal output from the AD7606 through the EMIF circuit, and realizes the transmission of the eight-channel signal from the AD7606 analog-to-digital converter to the DSP processing module. This application configures the EMIF circuit as a high-speed parallel interface, so that the eight channels can collect data in parallel through the EMIF circuit, realize high-speed data collection efficiency, and achieve the parallel collection effect of large-capacity data.

[0023] refer to Figure 4The SPI output circuit of the present invention adopts the SOM TL665x chip U16E. U16E has D1-D50 pins. D3 and D5 are used as DSP_TIMI0 and DSP_TIMI1 pins for the timer and timing functions of the DSP. D7 and D9 are used as DSP_TIMO0 and DSP_TIMO1 pins for the DSP timer output function. D13 and D15 are used as DSP_SDA and DSP_SCL pins respectively for external communication. Specifically, SDA is a data line for transmitting data, and SCL is a clock line for providing a clock signal for data transmission and synchronizing the data transmission process. D19, D21, D29 and D31 pins are used as DSP_UART1_RST, DSP_UART1_TXD, DSP_UART_RST and DSP_UART_TXD pins respectively. UART is the debugging serial port. It is connected to the computer through the serial port. In the serial port printing interface, verify whether the data collection is correct. UART1 is a 485 communication interface, which is a reserved communication interface for users to increase their needs. D23, D25, D33 and D35 are used as DSP_UART1_CTS and DSP_UART1_RTS, DSP_UART_CTS and DSP_UART_RTS pins respectively, which are used for serial communication control signals. D39 and D41 pins are used as DSP_SSPMOS1 and DSP_SSPMOS0 pins for serial or parallel data transmission of the DSP processing module. Specifically, MOSI is a signal line, representing the output data of the DSP processing module and the input data of the D / A conversion module. The signal is transmitted from the DSP processing module to the D / A conversion module. MISO is a signal line, representing the input data of the DSP processing module and the output data of the D / A conversion module. The signal is transmitted from the D / A conversion module to the DSP processing module; D43, D45 and D47 pins are used as DSP_SSPCK, DSP_SSPCS1 and DSP_ The SSPCS0 pin is used for the clock signal of the serial synchronous interface and to control communication with external devices. DSP_SSPCS1 and DSP_ SSPCS0 are chip select pins. The software driver controls the level of each pin at the corresponding time through timing, thereby controlling the data transmission from the DSP processing module to the D / A conversion module; the D48 and D50 pins are used as SYS_nRESET and SYS_IO interfaces, respectively, for system reset and processing system input and output, respectively. The SYS_IO interface is connected to the TP9 test point, and the other pins of U16E are grounded.

[0024] The relationship between the conversion accuracy and time of DAC data is: the higher the conversion accuracy, i.e., the number of bits, the longer the time consumption. The present invention enables AD5676 to receive the processed eight-channel digital signal output from the DSP processing module through the SPI output circuit, thereby realizing high-speed transmission of the eight-channel signal from the DSP processing module to AD5676, and ensuring the conversion accuracy of DAC data while achieving eight-channel high-speed serial output; the DSP processing module also stores the data processed by the DSP processing module in the flash of the DSP processing module through the SPI output circuit to prevent data loss.

[0025] refer to Figure 5 , the D / A conversion module uses the AD5676BRUZ chip. The SCLK, SDI, SDO, SYNC*, LDAC*, GAIN, RESET* and RSTSEL pins of the AD5676BRUZ chip are connected to resistors R222, R223, R224, R225, R226, R227, R228 and R273 respectively. The SDI, LDAC*, GAIN, RESET* and RSTSEL pins of the AD5676BRUZ chip are connected to one end of resistors R232, R233, R234, R236 and R235 respectively. The other end of resistors R232, R233, R234, R236 and R235 are connected to VDD_1VB_BRD. The AD5676BRUZ chip The VDD pin of the chip is connected to one end of capacitor C167 and one end of C165, and the other ends of C167 and C165 are analog grounded. The VL pin of the AD5676BRUZ chip is connected to one end of capacitor C168 and one end of C169, and the other ends of C168 and C169 are analog grounded. The VOUT0-VOUT7 pins of the AD5676BRUZ chip are used as the DC output interface of eight channels. The VREF interface of the AD5676BRUZ chip is connected to one end of resistor R274, and the other end of resistor R274 is connected to one end of capacitor C166 and VREF_2V5A, and the other end of capacitor C166 is analog grounded. The GND interface of the AD5676BRUZ chip is analog grounded, and the eight-channel signal is converted from a digital signal to an analog signal and output through the D / A conversion module.

[0026] The second signal conditioning module includes eight amplification and filtering circuits, reference Figure 6, one of the amplification and filtering circuits includes resistors R277, R241, R278, R242, R244, R243, capacitors C183, C184, operational amplifiers U52A and U52B, one end of resistor R277 is connected to VREF_2V5A power supply, the other end is connected to one end of resistor R242 and the inverting input end (pin 2) of operational amplifier U52A, the other end of resistor R242 is connected to the output end (pin 1) of operational amplifier U52A and one end of resistor R244, one end of resistor R241 is connected to the digital signal output interface of DA module, the other end of resistor R241 is connected to one end of resistor R278 and the non-inverting input end (pin 3) of operational amplifier, the other end of resistor R278 is analog grounded, the positive power supply pin (pin 8) of operational amplifier U52A is connected to AVCC_5V_P power supply, operational amplifier The negative power supply pin (pin 4) of the amplifier U52A is connected to AVCC_5V_N and grounded, the other end of the resistor R244 is connected to one end of the capacitor C183 and one end of the resistor R243, the other end of the capacitor C183 is connected to the inverting input terminal (pin 6) of the operational amplifier U52B and the output terminal (pin 7) of the operational amplifier U52B, the other end of the resistor R243 is connected to one end of the capacitor C184 and the non-inverting input terminal (pin 5) of the operational amplifier U52B, the other end of the capacitor C184 is analog grounded, the positive power supply pin (pin 8) of the operational amplifier U52B is connected to the AVCC_5V_P power supply, the negative power supply pin (pin 4) of the operational amplifier U52B is connected to the AVCC_5V_N and grounded, and the output terminal of the operational amplifier U52B is connected to the analog output interface ANA_OUT; the structure and composition of each amplification and filtering circuit are the same.

[0027] The signals of the eight channels are converted into analog signals by the D / A conversion module and output to eight amplification and filtering circuits respectively, which are used to reduce or eliminate high-frequency noise and interference at the output end of the DAC components, thereby improving the quality of the output signal. The two operational amplifiers are used to output a wider range of voltages, from the original positive and negative 2.5V to positive and negative 5V, making the present invention suitable for more occasions.

[0028] refer to Figure 7, is the overall architecture diagram of the data acquisition device of the present invention. The present invention mainly consists of an eight-channel 16-bit ADC-AD7606 analog-to-digital converter, a TI-C6657 microcontroller produced by TI and an eight-channel 16-bit DAC-AD5676 digital-to-analog converter. The DSP processing module adopts the TI-C6657 microcontroller. The peripheral circuit of the TI-C6657 microcontroller is connected with 128MByte NandFlash, 1GByte DDR3, JTAG, RESET, LED, network port, debugging serial port and RS485. The 128MByteNandFlash is used to store programs and data, the 1GByte DDR3 is used as the main memory of the system, JTAG is used for debugging and programming, RESET is used for resetting, LED Used to indicate status, network port and RS485 are used for communication, and debug serial port is used for debugging. The TI-C6657 microcontroller is powerful and the algorithm can be custom designed. The TI-C6657 microcontroller is connected with storage module and communication module, which can realize flexible control and data processing to meet the needs of different application scenarios. The TI-C6657 microcontroller has rich communication interfaces, which is convenient for connection and communication with external devices to realize remote transmission and monitoring of data.

[0029] refer to Figure 7 and Figure 8 The working process of the data acquisition device of the present invention is as follows: the analog signals of the eight channels first pass through the first signal conditioning module, and the eight ESD protection and signal filtering circuits of the first signal conditioning module correspond to the analog signals of the eight channels. The analog signals of the eight channels are output to the A / D conversion module for analog-to-digital conversion after low-pass filtering and ESD protection, that is, the eight-channel 16-bit ADC-AD7606 analog-to-digital converter. The digital signals of the eight channels after conversion are then transmitted to the DSP processing module through the EMIF circuit at high speed and in parallel. The DSP processing module is connected with an SPI output circuit. The signals of the eight channels after processing by the DSP processing module TI-C6657 are transmitted to the D / A conversion module through the SPI output circuit at high speed, that is, the eight-channel 16-bit ADC-AD7606 analog-to-digital converter. At the same time, the DSP processing module stores the processed data in the Flash of the DSP processing module through the SPI output circuit to prevent data loss. The analog signals of the eight channels after conversion are finally output to the eight amplification and filtering circuits of the second signal conditioning module respectively, and the analog signals are output after amplification and filtering.

[0030] Among them, in the process of transmitting the signal processed by the DSP processing module TI-C6657 to the D / A conversion module at high speed through the SPI output circuit, it is necessary to initialize the parameters of the analog-to-digital converters AD7606 and AD5676 through the software program, control the timing drive of AD7606 and AD5676, and realize the flow of eight channels of signals from AD7606 to TI-C6657 and from TI-C6657 to AD5676 through the respective timing control signals of AD7606 and AD5676.

[0031] The data acquisition device of the present invention can be applied in industrial automation production. The device can simultaneously collect operating parameters of multiple devices, such as temperature, pressure, rotation speed, etc., to provide accurate data support for monitoring and optimization of the production process; in scientific research experiments, it can quickly and accurately collect experimental data, which helps researchers to analyze data and draw scientific conclusions. The present invention can realize high-speed data processing and analysis, meet real-time requirements, do not require built-in FPGA, and simple development and debugging, thereby reducing development and maintenance costs.

[0032] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications are also within the protection scope of the present invention.

Claims

1. An eight-channel input and output data acquisition device, characterized in that: It includes an analog signal input interface, a first signal conditioning module, an A / D conversion module, an EMIF circuit, a DSP processing module, an SPI output circuit, a D / A conversion module, a second signal conditioning module and an analog output interface which are connected in sequence; The analog signal input interface receives eight-channel analog signals. The analog signals are filtered by the first signal conditioning module and then transmitted to the A / D conversion module through the EMIF circuit. The A / D conversion module converts the eight-channel analog signals into eight-channel digital signals. The digital signals are transmitted to the DSP processing module through the EMIF circuit. The DSP processing module collects, processes and analyzes the digital signals. The processed eight-channel digital signals are transmitted to the D / A conversion module through the SPI output circuit. The D / A conversion module converts the eight-channel digital signals into eight-channel analog signals. The analog signals are amplified and low-pass filtered by the second signal conditioning module and then output to the analog output interface to realize the output of eight-channel signals.

2. The eight-channel input and output data acquisition device according to claim 1, characterized in that: The first signal conditioning module includes eight ESD protection and signal filtering circuits, and the analog signals of the eight channels flow into the corresponding ESD protection and signal filtering circuits respectively. The structure and composition of each ESD protection and signal filtering circuit are the same. One of the ESD protection and signal filtering circuits includes a diode D14, a filter U25, resistors R81, R63, R79, R80, operational amplifiers U26A, U26B, and capacitors C44, C50, C126, C129, C127, and C128. The filter U25 is composed of capacitors and inductors. The structure and composition of each ESD protection and signal filtering circuit are the same. The cathode of diode D14 is connected to the analog input port ANA_IN_P1 and the filter U25, and the anode is analog grounded. Pin 1 of filter U25 is connected to the cathode of diode D14, pin 2 is analog grounded, pin 3 is connected to one end of resistor R81, and the other end of R81 is connected to the non-inverting input of operational amplifier U26A. The inverting input of operational amplifier U26A is connected to one end of resistor R63, and the other end of resistor R63 is connected to the output of operational amplifier U26A. The positive power supply pin of operational amplifier U26A is connected to a 5V analog voltage source, and the negative power supply pin is grounded. The output end of amplifier U26A is connected to one end of resistor R79, the other end of resistor R79 is connected to one end of capacitor C44 and one end of resistor R80, the other end of capacitor C44 is connected to the inverting input and output ends of operational amplifier U26B, the other end of resistor R80 is connected to one end of capacitor C50 and the non-inverting input end of operational amplifier U26B, the other end of capacitor C50 is analog grounded, the positive power supply pin (pin 8) of operational amplifier U26B is connected to a 5V analog voltage source, the negative power supply pin is grounded, and the output end of operational amplifier U26B is connected to AD module input interface ADC_IN1.

3. The eight-channel input and output data acquisition device according to claim 1, characterized in that: The A / D conversion module uses the AD7606 chip. The input pins V1-V8 of the AD7606 chip are connected to eight ESD protection and signal filtering circuits respectively. The V1GND-V8 GND pins of the AD7606 chip are analog grounded. The CONVST_A and CONVST_B of the AD7606 chip are connected. The PAR / SER / BYTE_SEL, RANGE, CS, RD / SCLK, PEF_SELECT, The STBY and RESET pins are connected to one end of R208, R845, R857, R856, R852 and R854 respectively, and the other ends of R208, R845, R857, R856, R852, R854 and R855 are connected to the AVDD_3V3 analog power supply. One end of R208, R845 and R852 is also connected to the resistors R215, R846 and R853 respectively and then analog grounded. The AVCC0, AVCC1, AVCC2 and AVCC3 pins of the AD7606 chip are connected to each other and then to the AVCC_5V_P power supply. One end of the capacitors C162, C163, C160, C161, C158 and C159 are connected to the AVCC_5V_P power supply and the other end is analog grounded. The DB0-DB15 pins of the AD7606 chip are connected to the resistor array. The REFCAPA and REFCAPB pins of the AD7606 chip are connected to one end of capacitor C48, and the other end of capacitor C48 is analog grounded. The REFGND0 and REFGND1 pins of the AD7606 chip are analog grounded. The REFIN / REFOUT pin of the AD7606 chip is connected to one end of capacitor C52 and ADC_VERF, and the other end of capacitor C52 is analog grounded. The REGND0 and REGND1 pins of the AD7606 chip are connected to one end of capacitors C657 and C51 respectively, and the other end of capacitors C657 and C51 are analog grounded. The VDRIVE pin of the AD7606 chip is connected to one end of capacitors C53 and C656 and AVDD_3V3, and the other end of capacitors C53 and C656 are analog grounded. The AGND0-AGND5 of the AD7606 chip are analog grounded.

4. The eight-channel input and output data acquisition device according to claim 1, characterized in that: The EMIF circuit uses the SOM TL665x chip U16D. U16D has a total of 50 pins from C1 to C50, of which C1 is used as the DSP_NMIZ pin for the non-masked interrupt of the controller, C3 is used as the DSP_HOUT pin and connected to the test point TP4 for outputting signals, C5 and C7 pins are used as the DSP_CORESEL0 and DSP_CORESEL1 pins for selecting a specific core or working mode, C11 pin is used as the DSP_LRESETZ pin for the reset function of the DSP, C12 pin is grounded, C13 pin is used as the DSP_RESETSTAT pin for indicating the reset status, and C15 is used as the DSP_RESETSTAT pin for indicating the reset status. As DSP_LRESETNMIENZ pin, it is used to control the reset and non-maskable interrupt function of DSP. C17 is used as DSP_RESETZ pin for reset. C19 pin is used as DSP_BOOTCOMPLETE pin and connected to test point TP11 to indicate the startup status of DSP. C21 pin is grounded. C14, C16, C18, C20, C22, C24, C26, C28, C30, C32, C34, C36, C38, C40, C42 and C44 pins are used as DSP_EMIFSD00-D15 pins to receive data transmitted by AD7606. C23, C25, C27, C29, C31, C33, C35, C37, C39, C41, C43, C45, C47, C46, ​​C48 and C50 are used as DSP_EMIFSA00-A15 pins. DSP_EMIFSA00-A15 represents the 16 pins of the EMIF address bus, which are used to read data from external devices through the EMIF bus and then put the data into memory for subsequent processing or use.

5. The eight-channel input and output data acquisition device according to claim 1, characterized in that: The SPI output circuit uses the SOM TL665x chip U16E. U16E has D1-D50 pins. D3 and D5 are used as DSP_TIMI0 and DSP_TIMI1 pins for DSP timer and timing functions. D7 and D9 are used as DSP_TIMO0 and DSP_TIMO1 pins for DSP timer output functions. D13 and D15 are used as DSP_SDA and DSP_SCL pins respectively for external communication. D19, D21, D29 and D31 pins are used as DSP_UART1_RST, DSP_UART1_TXD, DSP_UART_RST and DSP_UART_TXD pins respectively. UART is a debugging serial port, and UART1 is a 485 communication interface. D23, D25, D33 and D35 are used as DSP_UART1_CTS and DSP_UART1_RTS, DSP_UART_CTS and DSP_UART_RTS pins respectively, which are used for serial communication control signals. D39 and D41 pins are used as DSP_SSPMOS1 and DSP_SSPMOS0 pins, which are used for serial or parallel data transmission of DSP processing module; D43, D45 and D47 pins are used as DSP_SSPCK, DSP_SSPCS1 and DSP_ SSPCS0 pins respectively, which are used for clock signals of serial synchronous interface and control communication with external devices. DSP_SSPCS1 and DSP_ SSPCS0 are chip select pins, and the software driver controls the level of each pin at the corresponding time through timing; D48 and D50 pins are used as SYS_nRESET and SYS_IO interfaces respectively, which are used for system reset and processing system input and output respectively. The other pins of U16E are all grounded.

6. The eight-channel input and output data acquisition device according to claim 1, characterized in that: The D / A conversion module uses the AD5676BRUZ chip. The SCLK, SDI, SDO, SYNC*, LDAC*, GAIN, RESET* and RSTSEL pins of the AD5676BRUZ chip are connected to resistors R222, R223, R224, R225, R226, R227, R228 and R273 respectively. The SDI, LDAC*, GAIN, RESET* and RSTSEL pins of the AD5676BRUZ chip are connected to one end of resistors R232, R233, R234, R236 and R235 respectively. The other ends of resistors R232, R233, R234, R236 and R235 are connected to VDD_1VB_ BRD, the VDD pin of the AD5676BRUZ chip is connected to one end of the capacitor C167 and one end of C165, and the other end of C167 and C165 is analog grounded. The VL pin of the AD5676BRUZ chip is connected to one end of the capacitor C168 and one end of C169, and the other end of C168 and C169 is analog grounded. The VOUT0-VOUT7 pins of the AD5676BRUZ chip are used as the DC output interface of eight channels. The VREF interface of the AD5676BRUZ chip is connected to one end of the resistor R274, and the other end of the resistor R274 is connected to one end of the capacitor C166 and VREF_2V5A. The other end of the capacitor C166 is analog grounded, and the GND interface of the AD5676BRUZ chip is analog grounded.

7. The eight-channel input and output data acquisition device according to claim 1, characterized in that: The second signal conditioning module includes eight amplifying and filtering circuits, each of which has the same structure and composition, wherein one of the amplifying and filtering circuits includes resistors R277, R241, R278, R242, R244, R243, capacitors C183, C184, operational amplifiers U52A and U52B; One end of resistor R277 is connected to VREF_2V5A power supply, and the other end is connected to one end of resistor R242 and the inverting input end of operational amplifier U52A, the other end of resistor R242 is connected to the output end of operational amplifier U52A and one end of resistor R244, one end of resistor R241 is connected to the digital signal output interface of D / A conversion module, the other end of resistor R241 is connected to one end of resistor R278 and the non-inverting input end of operational amplifier, the other end of resistor R278 is analog grounded, the positive power supply pin of operational amplifier U52A is connected to AVCC_5V_P power supply, and the negative power supply pin of operational amplifier U52A is connected to AVCC_5V _N is grounded, the other end of resistor R244 is connected to one end of capacitor C183 and one end of resistor R243, the other end of capacitor C183 is connected to the inverting input of operational amplifier U52B and the output of operational amplifier U52B, the other end of resistor R243 is connected to one end of capacitor C184 and the non-inverting input of operational amplifier U52B, the other end of capacitor C184 is analog grounded, the positive power supply pin of operational amplifier U52B is connected to AVCC_5V_P power supply, the negative power supply pin of operational amplifier U52B is connected to AVCC_5V_N ground, and the output of operational amplifier U52B is connected to analog output interface ANA_OUT.

8. The eight-channel input and output data acquisition device according to claim 1, characterized in that: The DSP processing module specifically adopts the TI-C6657 microcontroller.

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