Terminal signal, signal processing method and device, passive tag and product

Abstract

The invention relates to the technical field of communication, and particularly provides a terminal signal, a signal processing method and device, a passive tag and a product. The terminal signal provided by the invention is obtained by encoding a first code element and a second code element; wherein the length of the first code element is the same as that of the second code element; the code pattern of the first code element is a full high level; the code pattern of the second code element comprises at least one low level and a plurality of high levels. The two code elements provided by the invention at least only comprise one low level, the proportion of the high level is higher, and the terminal signal provided by the invention can provide longer charging duration for the terminal under the condition of ensuring that the terminal receives the same signal, thereby effectively ensuring that the terminal can obtain enough working electric quantity.

Description

Technical Field

[0001] The present disclosure relates to the field of communication technology, and in particular to a terminal signal, a signal processing method and device, a passive tag and a product. Background Art

[0002] At present, in cellular passive IoT technology, terminals often use signals modulated by radio frequency signals (such as pulse interval coding) for charging. However, the proportion of high-level code elements used for charging in the current signal code type is relatively low. For example, in pulse interval coding, logic1 is encoded as '1110' or '110', and logic0 is encoded as '10' or '01', which results in a shorter charging time and lower charging efficiency of the terminal. Summary of the invention

[0003] In view of the above problems, the present disclosure is proposed. The present disclosure provides a terminal signal, a signal processing method and device, a passive tag and a product.

[0004] According to one aspect of the present disclosure, a terminal signal is provided, which is obtained by encoding a first code element and a second code element; wherein the first code element and the second code element have the same length; the code type of the first code element is all high levels; and the code type of the second code element includes at least one low level and multiple high levels.

[0005] According to another aspect of the present disclosure, a signal processing method is also provided, including: encoding and generating a terminal signal based on a first code element and a second code element; and / or decoding the terminal signal; wherein the first code element and the second code element have the same length; the code type of the first code element is all high levels; and the code type of the second code element includes at least one low level and multiple high levels.

[0006] According to another aspect of the present disclosure, a signal processing device is also provided, including: a signal generating module, used to encode and generate a terminal signal based on a first code element and a second code element; and / or, a signal processing module, used to decode the terminal signal; wherein, the first code element and the second code element have the same length; the code type of the first code element is all high levels; the code type of the second code element includes at least one low level and multiple high levels.

[0007] According to another aspect of the present disclosure, a passive tag is provided for implementing the method described in any one of the above embodiments.

[0008] According to another aspect of the present disclosure, an electronic device is provided, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the method described in any one of the above embodiments.

[0009] According to another aspect of the present disclosure, a computer-readable storage medium is provided, on which a computer program / instruction is stored. When the computer program / instruction is executed by a processor, the method described in any of the above embodiments is implemented.

[0010] According to another aspect of the present disclosure, a computer program product is provided, including a computer program / instruction, which implements the method described in any of the above embodiments when the computer program / instruction is executed by a processor.

[0011] As described in detail below, according to an embodiment of the present disclosure, a terminal signal, a signal processing method and device, a passive tag and a product. The terminal signal provided by the present disclosure is obtained by encoding a first code element and a second code element, wherein the first code element and the second code element provided by the present disclosure are of the same length, and the code type of the first code element is a full high level, and the second code element includes at least one low level and multiple high levels. That is to say, compared with the signal modulated by the radio frequency signal in the prior art (such as logic1 and logic0 encoding in pulse interval encoding), the two code elements provided by the present disclosure include at least one low level, and the proportion of high levels is higher. Under the condition of ensuring that the terminal receives the same signal, the terminal signal provided by the present disclosure can provide the terminal with a longer charging time, thereby effectively ensuring that the terminal can obtain sufficient working power. In addition, the two code elements of the terminal signal provided by the present disclosure are of the same length. Compared with the code elements of unequal lengths in the prior art, the terminal signal provided by the present disclosure can reduce the probability of errors in the decoding process to a certain extent, and improve the efficiency of decoding.

[0012] It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the technology as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and other purposes, features and advantages of the present disclosure will become more apparent by describing the embodiments of the present disclosure in more detail in conjunction with the accompanying drawings. The accompanying drawings are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. In the accompanying drawings, the same reference numerals generally represent the same components or steps.

[0014] Figure 1 It is a schematic diagram illustrating a signal structure of an embodiment of the present disclosure.

[0015] Figure 2 is a schematic diagram illustrating a low duty cycle signal output according to an embodiment of the present disclosure.

[0016] Figure 3 is a schematic diagram illustrating a high duty cycle signal output according to an embodiment of the present disclosure.

[0017] Figure 4 It is a schematic diagram comparing the charging efficiency of the embodiments of the present disclosure.

[0018] Figure 5 It is a schematic diagram comparing the charging efficiency of the embodiments of the present disclosure.

[0019] Figure 6 It is a schematic diagram illustrating a flow chart of signal encoding according to an embodiment of the present disclosure.

[0020] Figure 7 It is a schematic diagram illustrating a flow chart of signal decoding according to an embodiment of the present disclosure.

[0021] Figure 8 It is a flowchart illustrating a signal processing method according to an embodiment of the present disclosure.

[0022] Fig. 9 It is a schematic diagram illustrating a signal structure comparison according to an embodiment of the present disclosure.

[0023] Fig.10 It is a schematic diagram illustrating a bit error rate comparison of different signal structures according to an embodiment of the present disclosure.

[0024] Fig.11 is a block diagram illustrating a signal processing apparatus according to an embodiment of the present disclosure.

[0025] Fig.12 is a hardware block diagram illustrating an electronic device according to an embodiment of the present disclosure.

[0026] Fig.13 is a schematic diagram illustrating a computer program product according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solution and advantages of the present disclosure more obvious, the exemplary embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure, and it should be understood that the present disclosure is not limited to the exemplary embodiments described here.

[0028] At present, in 3GPP, the expected communication distance of cellular passive IoT technology is set at 30-50m indoors and about 200m outdoors, which is at least three times higher than the communication distance of radio frequency identification technology (RFID). Therefore, it is necessary to optimize the method of improving the communication distance of cellular passive IoT. In conventional wireless communication systems with unlimited energy, the optimization of physical layer coding technology can significantly improve the communication distance. For example, cellular networks use advanced channel coding such as LDPC and Polar to improve signal anti-interference.

[0029] However, the cellular passive IoT is an energy-constrained system, that is, the terminal needs to obtain energy from environmental energy such as RF energy and solar energy, because solar energy is unreliable energy. Therefore, RF energy is not only a means of transmitting information, but also can provide energy for the terminal. Limited by the energy acquisition method, the downlink coding of the cellular passive IoT should not only consider higher noise resistance performance, but also comprehensively consider the impact of coding on RF energy conversion efficiency, terminal circuit stability and other factors, and design a high-performance coding solution for "simultaneous transmission of data and energy".

[0030] Among them, the pulse interval encoding (PIE) encoding used in RFID can effectively improve the proportion of high-level in the encoded code block and charge the terminal. Therefore, it is adopted by the IEC / ISO 18000-6C standard. PIE encoding stipulates that logic 1 (also known as logic 1, log1, original bit 1) is encoded as "1110" or "110", and logic 0 (also known as logic 0, log0, original bit 0) is encoded as "10" or "01". However, since the encoding of logic 0 and logic 1 is not equal in length in this method, it is difficult to estimate their frame length during the communication process, which will increase the decoding complexity of the communication system. Therefore, the receiving end cannot divide the code block, and it may be possible to translate 2 original bits (logic 0, logic 0) into 1 logic1, or 1 logic 1 into 2 original bits (logic 0, logic0). In the existing RFID system, once the above decoding error occurs, a retransmission mechanism is used, that is, the current decoding result is discarded, the signal is received again and the decoding is performed.

[0031] Considering that in most scenarios, the terminal still needs to rely on RF energy charging to complete energy acquisition, the downlink communication link of the cellular passive system still needs to use PIE coding. However, due to the expansion of communication distance, the disadvantages of the above PIE decoding algorithm will be more obvious in the cellular system. At the same time, in order to achieve longer-distance RF energy collection, the charging gain brought by PIE coding needs to be further increased. Therefore, it is necessary to comprehensively consider the system's anti-noise performance and terminal charging efficiency, and optimize the PIE encoding and decoding method to enhance the downlink coverage distance of the cellular passive IoT system.

[0032] In view of the problem that the terminal signal structure in the prior art leads to low charging efficiency and easy decoding errors, the present disclosure provides a terminal signal, which is composed of the first code element and the second code element reconstructed by the present disclosure, wherein the first code element and the second code element at least include only one low level, thereby increasing the proportion of the high level in the code element used to charge the terminal, thereby improving the charging efficiency of the terminal. And through the code elements of the same length, the possibility of decoding errors is reduced.

[0033] The terminal signal specifically includes:

[0034] The terminal signal is obtained by encoding a first code element and a second code element; wherein, the first code element and the second code element have the same length; the code type of the first code element is all high levels; the code type of the second code element includes at least one low level and multiple high levels.

[0035] Specifically, the terminal signal can be understood as a signal encoded by a radio frequency signal used to charge the terminal and / or transmit information, and is a transceiver signal of the terminal. Among them, the terminal described above is an extremely low power consumption terminal, and the extremely low power consumption terminal here refers to a new type of Internet of Things terminal that does not rely on traditional battery power supply, and can use backscatter communication technology for communication. Among them, the terminal includes but is not limited to at least one of the following: a new type of passive Internet of Things tag (also called a passive tag), an environmental Internet of Things terminal. Furthermore, passive tags can be deployed in cellular passive Internet of Things. The information expressed by the terminal signal can be represented by a first code element and a second code element. The first code element and the second code element can be understood as different logical states, similar to the encoding of logic1 and logic0 in binary code PIE, and the logical state can be represented by multiple levels. For example, please refer to Figure 1 , Figure 1 Schematic diagram of a signal structure of an embodiment of the present disclosure. Figure 1 As shown, the original bit 0 (i.e., the first code element) can be represented by '111', and the original bit 1 (i.e., the second code element) can be represented by '110', where '1' represents a high level and '0' represents a low level. In this way, whether it is a character or a number, the first code element and the second code element can be combined to transmit information. Since there are only two logical states, even if the signal is interfered to a certain extent during transmission, as long as the interference does not exceed a certain threshold, the receiving end can still accurately identify the original signal. It should be noted that Figure 1 This is only an embodiment for easy understanding. In practical applications, the present disclosure does not specifically limit the lengths of the first code element and the second code element, and the structure of the second code element.

[0036] The present disclosure has no specific restrictions on the signal types represented by the first code element and the second code element. The first code element may be the code of logic1, and the second code element may be the code of logic0. Conversely, the first code element may be the code of logic0, and the second code element may be the code of logic1. The two may be selected according to the actual situation, and the present disclosure does not impose any specific restrictions on this.

[0037] Among them, the code type of the first code element is all high levels, that is, any byte in the first code element can be used to charge the terminal. The structure of the second code element needs to be distinguished from the first code element. The code type of the second code element includes at least one low level and multiple high levels, wherein the number of low levels included in the second code element does not exceed the preset threshold, for example, it may not exceed 1 / 4, 1 / 5, etc. of the code element length, and can be specifically customized. The fewer the number of low levels, the more conducive to charging. In other words, the present disclosure mainly uses the change of level to transmit information. When transmitting the same information, compared with the prior art, the terminal signal provided by the present disclosure can include at least one low level. Therefore, the terminal signal provided by the present disclosure has a higher duty cycle, and the terminal signal changes less times, which reduces the charging circuit capacitance required by the terminal to a certain extent, thereby shortening the pre-charging time and maintaining the circuit stability during the communication process, thereby providing higher charging efficiency. For ease of understanding, please refer to Figure 2 and Figure 3 ,like Figure 2 As shown, 201 is the signal amplitude of the terminal signal with a low duty cycle, and 202 is the average circuit output under the terminal signal with a low duty cycle, such as Figure 3 As shown, 301 is the signal amplitude of the terminal signal with a high duty cycle, and 302 is the output of the average circuit under the terminal signal with a high duty cycle. Obviously, the signal amplitudes of 201 and 301 are the same, both 3-18V, but the number of signals at a high level in 301 is more, and the duty cycle of 301 is greater than that of 201. Compared with 202 and 302, the output variation of the average circuit is smaller, making the circuit more stable, helping to protect the battery or capacitor from damage and ensuring that they can safely and effectively receive charging energy, thereby improving the charging efficiency to a certain extent.

[0038] The lengths of the first code element and the second code element are the same. That is, the terminal does not need an additional synchronization and timing mechanism to distinguish the two during the demodulation process, and the signal processing and identification methods can also be consistent, thereby simplifying the subsequent signal decoding process. The specific decoding process will be described in detail later and will not be repeated here.

[0039] Furthermore, the present disclosure does not specifically limit the length of the first code element and the second code element. When the length of the first code element and the second code element is longer, the number of high levels in the first code element and the second code element is more, and the duty cycle is higher, then the two code types can provide a longer charging time, which means that the terminal pre-charge capacitor will not need to be very large, which is beneficial to the timeliness of terminal communication and the reduction of device costs. In addition, this solution makes the charging and discharging process of the capacitor more stable, and the capacitor charge is always maintained above a certain level, which is beneficial to ensure the quality of terminal communication and is beneficial to the design of subsequent signal demodulation solutions. For example, please refer to Figure 4 ,like Figure 4 As shown, 401 is the charging efficiency of the terminal using the prior art PIE encoding for charging. That is, when the original bit 1 is encoded as "110" (i.e., the second codeword), when the original bit 0 is encoded as "111" (i.e., the first codeword), that is, Figure 1 As shown, the duty cycle of the code is 83.3%, and 402 is the charging efficiency of the code. Obviously, the charging efficiency of the code represented by 402 is higher than the charging efficiency of the PIE code. Figure 1 The encoding length is up to 6 bits, such as Figure 5 As shown, that is, when the original bit 1 is encoded as "111110" (i.e. the second code element) and the original bit 0 is "111111" (i.e. the first code element), the duty cycle of the code type is 91%, and 403 is the charging efficiency of the code. Obviously, the charging efficiency of the code represented by 403 is higher than the charging efficiency of the code represented by 402.

[0040] In an illustrative embodiment, still taking the encoding of logic1 and logic0 in the prior art PIE as an example, the encoding code type of logic1 can be "1110" or "110". At this time, the encoding duty cycle of logic1 is 75% or 66.7%, and the duty cycle of the first code element provided by the present disclosure is 100%. Obviously, when the lengths of the two code elements are the same, the first code element provided by the present disclosure can provide a longer charging time for the terminal. The encoding code type of logic 0 is "10" or "01". When the lengths of logic0 and the second code element provided by the present disclosure are the same, the duty cycle is the same. In general, the duty cycle of the terminal signal provided by the present disclosure is higher than that of the prior art.

[0041] In summary, the terminal signal provided by the present disclosure is obtained by encoding the first code element and the second code element, wherein the first code element and the second code element provided by the present disclosure have the same length, and the code type of the first code element is a full high level, and the second code element includes at least one low level and multiple high levels. In other words, compared with the signal modulated by the radio frequency signal in the prior art (such as logic1 and logic0 encoding in pulse interval coding), the two code elements provided by the present disclosure include at least one low level, and the proportion of high levels is higher. Under the condition of ensuring that the terminal receives the same signal, the terminal signal provided by the present disclosure can provide the terminal with a longer charging time, thereby effectively ensuring that the terminal can obtain sufficient working power. In addition, the two code elements of the terminal signal provided by the present disclosure have the same length. Compared with the code elements of unequal lengths in the prior art, the terminal signal provided by the present disclosure can reduce the probability of errors in the decoding process to a certain extent, and improve the efficiency of decoding.

[0042] For the specific structure of the second code element, the present disclosure does not specifically limit the specific position of the low level. The low level of the second code element is at a fixed position of the code type; wherein the fixed position includes but is not limited to: at least one of the first position, the last position, and the middle position. For example, when the fixed position is the last position, the second code element may be "110", and when the fixed position is the middle position, the second code element may be "101".

[0043] If there are multiple continuous high levels in the original bit, such as 5 first code elements, and the first code element is "111", there will be 15 continuous high levels. Such continuous high levels will cause the terminal to lose the clock synchronization information during the decoding process because the level does not jump for a long time, and the coding scheme that does not jump for a long time has weak anti-noise performance. Therefore, in addition to the above two types of code elements (i.e., the above-mentioned first code element and second code element), the terminal signal provided by the present disclosure may also include a third code element. Among them, the third code element has the same length as the above two code elements and a different code type. Exemplarily, when the second code element code type is "110", the third code element code type can be "101". The third code element is obtained by level inversion based on M specified positions of the full high level; wherein M is an integer greater than 0. Among them, the specified position includes but is not limited to at least one of the following: the first position, the last position, and the middle position. That is to say, the third code element can be used to prompt the clock synchronization information, and in the subsequent decoding process, the third code element will be reversed and restored to obtain the first code element, which will be described in detail later.

[0044] The present disclosure also provides a signal encoding method (i.e., subsequent step S601) and a signal decoding method (i.e., subsequent step S701) of the above-mentioned terminal signal, wherein the terminal may only apply the above-mentioned signal encoding method (e.g., photoelectric encoder, magnetic encoder, capacitive encoder, inductive encoder, and mechanical encoder), or only apply the above-mentioned signal decoding method (e.g., digital decoder, frequency decoder), or, may apply both the above-mentioned signal encoding method and the above-mentioned signal decoding method (e.g., passive tag). In other words, the terminals for signal encoding and signal decoding of the terminal signals provided by the present disclosure may be the same or different, and may be determined according to actual conditions, and the present disclosure does not impose any restrictions.

[0045] For the signal encoding method, please refer to Figure 6 , including:

[0046] Step S601: Encode and generate a terminal signal based on the first codeword and the second codeword.

[0047] Specifically, the present disclosure does not specifically limit the use of the terminal. That is, the terminal can be used only for encoding and generating terminal signals, or can be used only for decoding terminal signals, or can be used for both encoding and decoding, which can be determined according to actual conditions.

[0048] Among them, the terminal signals that can be processed by the terminal, and / or the terminal signals obtained by processing at least include the terminal signals provided by the present disclosure.

[0049] Optionally, when there are multiple consecutive high levels in the original bit, in order to ensure clock synchronization, the terminal can perform level inversion on a specified position in the high level. For example, if there are three consecutive first code elements in the original bit, the last N bits after encoding are inverted by 01, that is, Figure 5 As shown, if the encoded bits are "111 111 111", N = 2, then the last two bits 1 after encoding should be inverted to bit 0, and the encoded bits are 111 111 100. In practical applications, if logic 1 is encoded as a full high level code pattern, then logic 1 can use the above level inversion method to obtain the third code element. Conversely, if logic 0 is encoded as a full high level code pattern, then logic 0 can use the above level inversion method to obtain the third code element. Among them, the level inversion method includes but is not limited to at least one of the following: mapping conversion, algorithm conversion, and software conversion.

[0050] For details on signal decoding methods, please refer to Figure 7 ,like Figure 7 As shown:

[0051] Step S701, decoding the terminal signal; wherein the first code element and the second code element have the same length; the code type of the first code element is all high levels; the code type of the second code element includes at least one low level and multiple high levels.

[0052] Specifically, the terminal can directly decode after receiving the terminal signal, or can perform identification processing after receiving the terminal signal. The steps performed here are related to the type of code elements included in the terminal signal. When the terminal signal includes the third code element, the terminal needs to identify the terminal signal to obtain the inverted third code element. The terminal can invert the third code element before decoding to obtain the high-level code element before inversion (i.e., the first code element). Next, the terminal signal can be decoded.

[0053] Specifically, the present disclosure mainly uses a difference decoding method based on length rounding to decode the terminal signal. Since the terminal signal provided by the present disclosure contains less level change information, it only has a unique falling edge when the high level changes to the low level. Therefore, in the decoding process, the present disclosure uses the low level edge as a high level indication in the data frame, and then fills the decoding result by calculating the number of low level code elements in the adjacent high level code elements, thereby obtaining a complete decoding result.

[0054] The decoding process of the terminal signal specifically includes the following steps S701b to S701d:

[0055] S701b: Determine a second codeword in the terminal signal based on the falling edge position of each sampling point.

[0056] Specifically, since there is only one falling edge when the high level changes to the low level, and the first code element is all high level, that is to say, there is a falling edge only when the second code element exists. Therefore, when there is a falling edge in the sampling point, it can be considered that there is a second code element in the signal.

[0057] S701c, determining a first symbol in the terminal signal based on each falling edge position and a sampling sequence length;

[0058] That is to say, the first difference can be obtained by subtracting the starting sampling sequence position of the valid data frame from the sampling sequence position of any falling edge, or the sampling sequence position of the previous falling edge, and the ratio between the first difference and the sampling sequence length is obtained and rounded to obtain the number of the first code elements. Because the result also includes the high-level part of the high-level code element, the result is then rounded up and subtracted by 1. Specifically, the first difference includes at least one of the following: the position difference between the first falling edge position and the starting position of the data frame, the position difference between any two adjacent falling edge positions, and the position difference between the last falling edge position and the last position of the data frame.

[0059] For ease of understanding, the following will be explained in conjunction with specific embodiments. Assume that the first code element is "111111", the second code element is "111110", and the number of sampling times of a code element is 60. When there are multiple '0' code elements in the signal (that is, there are multiple falling edge positions), it means that there are multiple second code elements in the signal. When the first difference between any two consecutive '0' code elements is greater than 60, it means that there is at least one first code element between the two second code elements. After obtaining the ratio of the first difference to the length of the sampling sequence, it can be obtained how many first code elements there are between two consecutive '0' code elements. Similarly, for the first '0' code element, it is only necessary to obtain the number of first code elements based on the first difference between the first 0' code element and the starting sampling sequence position, and based on the ratio of the first difference to the length of the sampling sequence.

[0060] It should be noted that the present disclosure does not specifically limit the number of sampling points of each codeword (i.e., the sampling sequence length). In order to prevent errors caused by noise elimination or sampling errors, the divisor size in the decoding can be appropriately adjusted according to the number of sampling points of a single codeword.

[0061] S701d, sequentially concatenate the second codeword and the first codeword to obtain a decoding result.

[0062] Thus, in the above steps S701b and S701c, the position of each second symbol and the number of first symbols around the second symbol can be obtained. Thus, the final decoding result can be obtained by splicing according to the position of each symbol.

[0063] Optionally, before step S701b, step S701a may also be included, i.e., pre-processing the terminal signal, the pre-processing includes but is not limited to at least one of the following: denoising, pre-charging, and clock synchronization. In this way, the duration of the low level in the code element can be used to set the decision threshold for noise. For the case where the edge difference of adjacent level changes is less than the decision threshold, the level in the adjacent edge is changed to the level of a sampling point before the leading edge of the two edges to eliminate noise interference. Afterwards, the terminal capacitor can be pre-charged and clock synchronized through the preamble. The clock synchronization method is to use sliding correlation positioning to determine the starting position of the valid data frame. Since the encoding proposed in this scheme is a low-rate encoding scheme, the terminal clock accuracy only needs to be around 1% to 10% to meet the clock synchronization needs.

[0064] The signal processing method provided in the present disclosure can freely combine the above embodiments according to actual conditions, and the present disclosure does not impose any specific limitation on this.

[0065] In an exemplary embodiment, the present disclosure provides a signal processing method, which can be specifically referred to as Figure 8 ,like Figure 8 As shown, the method specifically includes:

[0066] S1, receiving end data frame input.

[0067] In this step, the receiving end can be understood as a terminal, and the data frame input is an input terminal signal.

[0068] S2, remove noise according to the number of sampling points per unit bit.

[0069] In this step, the number of sampling points per bit, i.e. the aforementioned sampling sequence length, is subjected to noise removal, i.e. the denoising process in the aforementioned preprocessing.

[0070] S3, determine the start bit of the valid data frame by sliding correlation based on the preamble code.

[0071] This step is the clock synchronization process in the aforementioned preprocessing.

[0072] S4, finding the falling edge position to determine the number of '1' code elements.

[0073] This step is the aforementioned S701c.

[0074] S51, the '0' codeword before the first '1' codeword is determined.

[0075] S52, '0' between two adjacent code elements is determined.

[0076] S53, the '0' codeword after the last '1' codeword is determined.

[0077] Steps S51-S53 are used to determine the first difference, S51 corresponds to the position difference between the first falling edge position and the starting position of the data frame, S52 corresponds to the position difference between any two adjacent falling edge positions, and S53 corresponds to the position difference between the last falling edge position and the last position of the data frame.

[0078] S6, sequentially concatenate the arrays according to the decoding results.

[0079] S7, decoding result output.

[0080] According to the above decoding process, the decoding error of the present disclosure will only exist in the low-level area, that is, any erroneous level jump in the low-level area will lead to decoding errors. For example, when the noise elimination process is performed in the first step of the decoding link, in the low-level area, the decoding principle will mistakenly regard the error as being eliminated by noise interference. According to the noise interference elimination method, the low-level part at this time will become a high level. This change also causes the falling edge used for code type judgment to disappear, so the judgment of a "1" code element will be missed, resulting in the "1" code element being incorrectly decoded as a "0" code element. Please refer to Fig. 9,like Fig. 9 As shown, 901 is used to represent a high level (i.e., 1), and 902 is used to represent a low level (i.e., 0), then logic1 can be represented as 10, and logic0 can be represented as 1110. Compared with PIE encoding, in PIE decoding, because the falling edge needs to be used as the decision position, therefore, changing the falling edge situation will also change the decision result accordingly. When an error occurs in a low-level area, according to the same noise elimination method as the new encoding, the low-level area will all become a high level at this time, causing the falling edge to disappear. At this time, the current decision moment will be ignored in the judgment, resulting in erroneous decoding. Compared with the terminal signal provided by the present disclosure, the code pattern of the PIE code contains more low-level components, and this feature causes the probability of the error area to appear to be greater, thus resulting in a higher bit error rate. Similarly, by lengthening the new code pattern to further reduce the proportion of low levels in the new code pattern, the optimization result can be further strengthened.

[0081] For a comparison of the error rates between the two, please refer to Fig.10 ,Depend on Fig.10 It can be observed that due to the appearance of continuous high-level code elements, the new short code type can avoid misjudgment when continuous high-level code elements appear. Compared with the accuracy of PIE encoding and decoding 1003, the decoding accuracy 1002 and 1001 provided by the present disclosure will be increased by about 50% (assuming that 1, 0 code elements, etc. may appear). Without considering the code element transmission efficiency, as shown in 1002 and 1001. Further extending the code type can further reduce the low-level transmission time under the same code element transmission time, thereby reducing the decoding errors caused by the channel environment. The specific degree of impact on the decoding error performance will be affected by the code length, Fig.10 The results shown are consistent with the theoretical analysis results. Compared with PIE coding, the new equal-length coding has better charging performance and better communication quality. When the bit error rate is ≤10%, the signal-to-noise ratio is improved. At the same time, the longer code type brings better charging performance and lower decoding errors. In scenarios where there are no strict requirements on the transmission time, it can be used as an optimization solution for the new equal-length coding to further improve the success rate of terminal reading.

[0082] In summary, the terminal signal provided by the present disclosure combines all high-level code elements with at least one bit of low-level code elements, which can optimize the communication bit error rate under a certain signal-to-noise ratio while ensuring the maximum charging efficiency. In addition, the present disclosure also provides a signal processing method, in the decoding process, the falling edge is used as an indication of the high-level code element in the data frame, and then the low-level code elements between the first and last two code elements and the subsequent two adjacent high-level code elements are rounded up according to the sampling sequence difference between the high-level code elements divided by the length of a single code element and the influence of the "1" code element is subtracted to obtain the original code element number, thereby effectively improving the communication quality, and in the same usage scenario, more information distortion problems can be avoided, and information retransmission problems can be reduced, which effectively improves the communication efficiency and saves cost.

[0083] The present disclosure also provides a signal processing device. Fig.11 A structural block diagram of a signal processing device provided in an embodiment of the present disclosure, such as Fig.11 As shown, the signal processing device 1100 includes:

[0084] The signal generating module 1101 is used for encoding and generating a terminal signal based on the first code element and the second code element;

[0085] and / or,

[0086] The signal processing module 1102 is used to decode the terminal signal;

[0087] The first code element has the same length as the second code element;

[0088] The code pattern of the first code element is all high level;

[0089] The code pattern of the second code element includes at least one low level and a plurality of high levels.

[0090] In an exemplary embodiment, the signal processing device 1100 is further configured so that the low level of the second code element is at a fixed position in the corresponding code type; wherein the fixed position includes: any one of the first position, the last position, and the middle position.

[0091] In an exemplary embodiment, the signal processing device 1100 is further configured such that the first code element is used to represent a logic 1, and the second code element is used to represent a logic 0; or, the first code element is used to represent a logic 0, and the second code element is used to represent a logic 1.

[0092] In an exemplary embodiment, the signal processing device 1100 is further configured such that the terminal signal is a receiving and transmitting signal of a passive tag, and the terminal signal is used to charge the passive tag during the signal receiving and transmitting process; wherein the passive tag is deployed in a cellular passive Internet of Things.

[0093] In an exemplary embodiment, the signal processing device 1100 is also configured to perform decoding processing on the terminal signal, including: determining the second codeword in the terminal signal based on the falling edge position of each sampling point; determining the first codeword in the terminal signal based on each falling edge position and the sampling sequence length; sequentially splicing the second codeword with the first codeword to obtain a decoding result.

[0094] In an exemplary embodiment, the signal processing device 1100 is further configured to determine the first symbol in the terminal signal based on each falling edge position and the sampling sequence length, including:

[0095] Obtain a first difference, wherein the first difference includes at least one of the following: a position difference between a first falling edge position and a starting position of a data frame, a position difference between any two adjacent falling edge positions, and a position difference between a last falling edge position and a last position of a data frame; obtain a ratio between the first difference and the length of the sampling sequence and round it to obtain the number of the first code elements.

[0096] In an exemplary embodiment, the signal processing device 1100 is also configured to, before decoding the terminal signal, the method also includes: preprocessing the terminal signal, and the preprocessing includes at least one of the following: denoising processing, precharging processing, and clock synchronization processing.

[0097] Fig.12 The electronic device 1200 according to the embodiment of the present disclosure includes at least a memory, a processor and a computer program stored in the memory, and the processor executes the computer program to implement the signal transmission method described in any of the above embodiments.

[0098] Fig.12 The electronic device 1200 shown specifically includes: a central processing unit (CPU) 1201, a graphics processing unit (GPU) 1202 and a memory 1203. These units are connected to each other via a bus 1204. The central processing unit (CPU) 1201 and / or the graphics processing unit (GPU) 1202 can be used as the above-mentioned processor, and the memory 1203 can be used as the above-mentioned memory storing computer-readable instructions. In addition, the electronic device 1200 may also include a communication unit 1205, a storage unit 1206, an output unit 1207, an input unit 1208 and an external device 1209, which are also connected to the bus 1204.

[0099] Fig.13 is a schematic diagram illustrating a computer program product according to an embodiment of the present disclosure. Fig.13As shown, a computer-readable storage medium 1300 according to an embodiment of the present disclosure has computer-readable instructions 1301 stored thereon. When the computer-readable instructions 1301 are executed by a processor, the signal transmission method described in any of the foregoing embodiments of the present disclosure is implemented. The computer-readable storage medium includes, but is not limited to, for example, volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, optical disk, magnetic disk, etc.

[0100] The present disclosure further provides a computer program product, including a computer program / instruction, which implements the signal processing method described in any of the foregoing embodiments of the present disclosure when executed by a processor.

[0101] The basic principles of the present disclosure are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present disclosure are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present disclosure. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, and are not limitations. The above details do not limit the present disclosure to the necessity of adopting the above specific details to be implemented.

[0102] The block diagrams of the devices, apparatuses, equipment, and systems involved in this disclosure are only illustrative examples and are not intended to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagrams. As will be appreciated by those skilled in the art, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner. Words such as "including," "comprising," "having," and the like are open words, referring to "including but not limited to," and can be used interchangeably therewith. The words "or" and "and" used herein refer to the words "and / or," and can be used interchangeably therewith, unless the context clearly indicates otherwise. The word "such as" used herein refers to the phrase "such as but not limited to," and can be used interchangeably therewith.

[0103] Additionally, as used herein, "or" used in a list of items beginning with "at least one" indicates a separate list, so that, for example, a list of "at least one of A, B, or C" means A or B or C, or AB or AC or BC, or ABC (i.e., A and B and C). Furthermore, the word "exemplary" does not mean that the example described is preferred or better than other examples.

[0104] It should also be noted that in the system and method of the present disclosure, each component or each step can be decomposed and / or recombined. Such decomposition and / or recombination should be regarded as equivalent solutions of the present disclosure.

[0105] Various changes, substitutions, and modifications of the techniques described herein may be made without departing from the teachings defined by the appended claims. Furthermore, the scope of the claims of the present disclosure is not limited to the specific aspects of the processes, machines, manufactures, compositions of events, means, methods, and actions described above. Currently existing or later to be developed processes, machines, manufactures, compositions of events, means, methods, or actions that perform substantially the same functions or achieve substantially the same results as the corresponding aspects described herein may be utilized. Thus, the appended claims include such processes, machines, manufactures, compositions of events, means, methods, or actions within their scope.

[0106] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the aspects shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

[0107] The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present disclosure to the forms disclosed herein. Although multiple example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.

Claims

1. A terminal signal, characterized in that: The terminal signal is obtained by encoding the first code element and the second code element; The first code element has the same length as the second code element; The code pattern of the first code element is all high level; The code pattern of the second code element includes at least one low level and a plurality of high levels.

2. The terminal signal according to claim 1, characterized in that: The low level of the second code element is at a fixed position of the code type to which it belongs; wherein the fixed position includes: any one of the first position, the last position, and the middle position.

3. The terminal signal according to claim 1, characterized in that: The first code element is used to represent a logic 1, and the second code element is used to represent a logic 0; or, The first code element is used to represent a logic 0, and the second code element is used to represent a logic 1.

4. The terminal signal according to claim 1, characterized in that: The terminal signal is a transceiver signal of a passive tag, and the terminal signal is used to charge the passive tag during the signal transceiver process; Wherein, the passive tag is deployed in a cellular passive Internet of Things.

5. The terminal signal according to claim 1, characterized in that: The terminal signal further includes a third symbol, and the third symbol is obtained by level inversion based on M designated positions of all high levels; Wherein, M is an integer greater than 0.

6. A signal processing method, characterized in that: include: Encoding and generating a terminal signal based on the first codeword and the second codeword; and / or, Decoding the terminal signal; The first code element has the same length as the second code element; The code pattern of the first code element is all high level; The code pattern of the second code element includes at least one low level and a plurality of high levels.

7. The method according to claim 6, characterized in that The low level of the second code element is at a fixed position of the code type to which it belongs; wherein the fixed position includes: any one of the first position, the last position, and the middle position.

8. The method according to claim 6, characterized in that The first code element is used to represent a logic 1, and the second code element is used to represent a logic 0; or, The first code element is used to represent a logic 0, and the second code element is used to represent a logic 1.

9. The method according to claim 6, characterized in that The terminal signal is a transceiver signal of a passive tag, and the terminal signal is used to charge the passive tag during the signal transceiver process; Wherein, the passive tag is deployed in a cellular passive Internet of Things.

10. The method according to any one of claims 6 to 9, characterized in that: The decoding process of the terminal signal includes: Determine a second symbol in the terminal signal based on the falling edge position of each sampling point; Determining a first symbol in the terminal signal based on each falling edge position and a sampling sequence length; The second codeword is sequentially concatenated with the first codeword to obtain a decoding result.

11. The method according to claim 10, characterized in that The determining the first symbol in the terminal signal based on each falling edge position and the sampling sequence length includes: Obtain a first difference, wherein the first difference includes at least one of the following: a position difference between a first falling edge position and a starting position of a data frame, a position difference between any two adjacent falling edge positions, and a position difference between a last falling edge position and a last position of a data frame; The ratio between the first difference and the sampling sequence length is obtained and rounded to an integer to obtain the number of the first code elements.

12. The method according to claim 10 or 11, characterized in that: Before decoding the terminal signal, the method further includes: The terminal signal is preprocessed, and the preprocessing includes at least one of the following: denoising processing, precharging processing, and clock synchronization processing.

13. A signal processing device, characterized in that: include: A signal generating module, used for encoding and generating a terminal signal based on the first code element and the second code element; and / or, A signal processing module, used for decoding the terminal signal; The first code element has the same length as the second code element; The code pattern of the first code element is all high level; The code pattern of the second code element includes at least one low level and a plurality of high levels.

14. A passive tag, characterized in that: The passive tag is used to implement the method according to any one of claims 6 to 12.

15. An electronic device comprising a memory, a processor and a computer program stored in the memory, characterized in that: The processor executes the computer program to implement the method according to any one of claims 6 to 12.

16. A computer-readable storage medium having a computer program / instruction stored thereon, characterized in that: When the computer program / instructions are executed by a processor, the method according to any one of claims 6 to 12 is implemented.

17. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instructions are executed by a processor, the method according to any one of claims 6 to 12 is implemented.

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