Manufacturing method and photoetching machine equipment
By dividing different exposure areas on the semiconductor substrate and forming front layer alignment marks, the problem that the alignment marks are difficult to detect by detecting light is solved, and the quality and accuracy of the lithography process are improved.
Patent Information
- Application Number
- CN202411835792.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-12
- Publication Date
- 2025-02-11
AI Technical Summary
During semiconductor manufacturing, it is difficult to detect alignment marks or poor detection effects of detecting light, resulting in a decrease in lithography quality.
By dividing the first region and the second region on the semiconductor substrate, the first region includes a complete exposure region, the second region includes an incomplete exposure region, and a front layer alignment mark is formed on both regions. Then, the photoresist in the second area is subjected to the first exposure process, the exposed photoresist is removed, the front layer alignment mark is exposed, and the second exposure process is performed based on it.
The accuracy of the second exposure process is improved, the quality of the lithography process is improved, the probability of wafer rework is reduced, and the chipping cost and actual manufacturing cost are reduced.
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Figure CN119414672A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing technology, and in particular to a manufacturing method and a photolithography device. Background Art
[0002] In the field of semiconductor manufacturing, alignment marks are usually formed in advance in order to improve the overlay accuracy between process layers.
[0003] In the manufacturing process of some semiconductor devices, due to process requirements, a thicker photoresist is spin-coated to perform a photolithography process. During the photolithography process, an alignment operation needs to be performed according to an alignment mark.
[0004] However, when the alignment mark is detected by the detection light, the alignment mark cannot be detected or the detection effect is poor, and the intensity of the obtained alignment signal is weak, which will reduce the lithography quality. Summary of the invention
[0005] The problem solved by the embodiments of the present invention is to provide a manufacturing method and a photolithography device, which can improve the quality of the photolithography process.
[0006] An embodiment of the present invention provides a manufacturing method, including:
[0007] Providing a semiconductor substrate, wherein the semiconductor substrate is divided into a first area and a second area, wherein the first area includes a plurality of complete exposure areas, and the second area includes a plurality of incomplete exposure areas;
[0008] forming a front layer alignment mark on the semiconductor substrate in the first region and the second region;
[0009] forming a photoresist, wherein the photoresist covers the front layer alignment mark;
[0010] Performing a first exposure process on the photoresist in a portion of the second area, and then removing the exposed photoresist to expose the front layer alignment mark located in the portion of the second area;
[0011] The semiconductor substrate is subjected to a second exposure process based on the exposed front layer alignment mark as a reference.
[0012] Optionally, the plurality of incomplete exposure regions include a first incomplete exposure region and a second incomplete exposure region, and the first incomplete exposure region and the second incomplete exposure region are arranged at relative positions of the semiconductor substrate.
[0013] Optionally, before performing the first exposure process on the photoresist of a portion of the second region, the forming method further comprises:
[0014] A process list for the semiconductor substrate is configured, the process list including the number of exposure processes and exposure conditions, wherein the number of exposure processes is two, and the exposure condition for the first exposure process is to select at least one incomplete exposure area in the second area and to remove the first area, and the exposure condition for the second exposure process is to select each complete exposure area in the first area and to remove part or all of the incomplete exposure areas in the second area.
[0015] Optionally, the method of forming the front layer alignment mark on the semiconductor substrate in the first region and the second region includes at least one of the following:
[0016] Forming a layer to be processed on the semiconductor substrate; forming a groove in the layer to be processed, wherein the groove exposes the surface of the semiconductor substrate and serves as an alignment mark of the front layer;
[0017] Forming a dielectric layer on the semiconductor substrate; forming an opening in the dielectric layer, wherein the opening exposes the surface of the semiconductor substrate; forming a layer to be processed in the opening; after forming the layer to be processed, removing the dielectric layer, and using the side wall adjacent to the layer to be processed and the area between the surface of the semiconductor substrate as the front layer alignment mark;
[0018] In the step of forming the photoresist, the photoresist covers the surface of the layer to be processed and fills the groove.
[0019] Optionally, the layer to be processed is a metal contact layer.
[0020] Optionally, along the normal direction of the surface of the semiconductor substrate, the thickness of the layer to be processed is 3 μm to 5 μm.
[0021] Optionally, before forming the layer to be processed on the semiconductor substrate, the forming method further comprises:
[0022] forming a dielectric layer on the semiconductor substrate;
[0023] The front layer alignment mark exposes the surface of the dielectric layer.
[0024] Optionally, along a normal direction of the surface of the semiconductor substrate, a thickness of the dielectric layer is 0.5 μm to 0.7 μm.
[0025] Optionally, before forming the photoresist, the forming method further comprises:
[0026] forming a protective layer on the layer to be processed, wherein the protective layer is also located in the groove;
[0027] In the step of forming the photoresist, the photoresist also covers the surface of the protective layer.
[0028] Optionally, along the normal direction of the surface of the semiconductor substrate, the thickness of the photoresist is 4 μm to 6 μm.
[0029] Accordingly, an embodiment of the present invention further provides a lithography device, including:
[0030] A providing unit, configured to provide a semiconductor substrate, wherein the semiconductor substrate is divided into a first region and a second region, wherein the first region includes a plurality of complete exposure regions, and the second region includes a plurality of incomplete exposure regions;
[0031] A forming unit, configured to form a front layer alignment mark on the semiconductor substrate in the first region and the second region;
[0032] An exposure unit is used to form a photoresist and perform a first exposure process on the photoresist in a portion of the second area, then remove the exposed photoresist to expose a front layer alignment mark located in the portion of the second area, and perform a second exposure process on the semiconductor substrate based on the exposed front layer alignment mark, wherein the photoresist covers the front layer alignment mark.
[0033] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:
[0034] In the manufacturing method provided by an embodiment of the present invention, a semiconductor substrate is divided into a first area and a second area, wherein the first area includes a plurality of complete exposure areas, and the second area includes a plurality of incomplete exposure areas, and front-layer alignment marks are formed on the semiconductor substrate of the first area and the second area. In this way, when performing a photolithography process, since no device is formed in the incomplete exposure area, the front-layer alignment marks of the portion of the second area can be exposed in advance by performing a first exposure process, and then the exposed front-layer alignment marks can be used as a reference to perform an alignment operation on the second exposure process, thereby improving the accuracy of the second exposure process, enabling the target area to be exposed for the second time, and improving the quality of the photolithography process. BRIEF DESCRIPTION OF THE DRAWINGS
[0035] Figure 1 is a flow chart of a manufacturing method in an embodiment of the present invention;
[0036] Figure 2 It is a schematic diagram of dividing the exposure area of a semiconductor substrate in an embodiment of the present invention;
[0037] Figures 3 to 8 It is a schematic structural diagram corresponding to each step of a power device in an embodiment of the present invention;
[0038] Fig. 9 It is a schematic structural diagram of a lithography device in an embodiment of the present invention. DETAILED DESCRIPTION
[0039] As described in the background art, in the manufacturing process of some semiconductor devices (e.g., power devices), when detecting alignment marks by using detection light, the alignment marks cannot be detected or the detection effect is poor. This is because:
[0040] During the formation of power devices, a thicker metal layer needs to be grown; and in subsequent processing, a thicker photoresist needs to be spin-coated on the metal layer to ensure that the surface of the metal layer will not be etched and to improve the integrity of the metal layer surface.
[0041] In this way, under the double blocking of thicker metal and thicker photoresist, only a small part of the detection light can be transmitted to the alignment mark (or called alignment structure), which has an adverse effect on the alignment process and may even make it impossible to effectively perform the alignment operation. In this way, when performing the photolithography process, the alignment operation cannot be achieved and may even cause photolithography to be performed on other areas, reducing the quality of the photolithography process.
[0042] In order to solve the above technical problems, the present invention provides a manufacturing method, comprising: providing a semiconductor substrate, wherein the semiconductor substrate is divided into a first area and a second area, the first area includes a plurality of complete exposure areas, and the second area includes a plurality of incomplete exposure areas; forming a front layer alignment mark on the semiconductor substrate in the first area and the second area; forming a photoresist, wherein the photoresist covers the front layer alignment mark; performing a first exposure process on the photoresist in a portion of the second area, and then removing the exposed photoresist to expose the front layer alignment mark located in the portion of the second area; and performing a second exposure process on the semiconductor substrate based on the exposed front layer alignment mark.
[0043] In the manufacturing method provided by the present invention, when performing the photolithography process, since the incomplete exposure area does not form a device, the front layer alignment mark of the part of the second area can be exposed in advance by performing the first exposure process, and then the alignment operation can be performed based on the exposed front layer alignment mark, thereby improving the accuracy of the second exposure process, making it possible to perform the second exposure process on the target area and improving the quality of the photolithography process.
[0044] Furthermore, the above solution reduces the probability of wafer rework, reduces wafer tape-out costs and actual manufacturing costs, and has higher economic practicality.
[0045] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are exemplarily described below in conjunction with the accompanying drawings.
[0046] See also Figures 1 to 8 ,in, Figure 1is a flow chart of a manufacturing method in an embodiment of the present invention, Figure 2 FIG. 1 is a schematic diagram of dividing the exposure area of a semiconductor substrate in an embodiment of the present invention. Figures 3 to 8 It is a schematic structural diagram corresponding to each step of a power device in an embodiment of the present invention.
[0047] See also Figure 1 and Figure 2 , can be manufactured in the following ways:
[0048] S100, providing a semiconductor substrate, wherein the semiconductor substrate is divided into a first region and a second region, wherein the first region includes a plurality of complete exposure regions, and the second region includes a plurality of incomplete exposure regions.
[0049] Specifically, the semiconductor substrate 100 may provide a process operation basis for a formation process of a power device, wherein the power device may include a longitudinal double diffused metal oxide semiconductor structure LDMOS and / or a vertical double diffused metal oxide semiconductor structure VDMOS.
[0050] In the actual manufacturing process, there is a part of the semiconductor substrate that does not form any device or this part of the semiconductor substrate will not appear in the finally formed semiconductor device. Based on this, the semiconductor substrate can be divided into a first region and a second region.
[0051] The first area may include a plurality of complete exposure areas St0, where the complete exposure area St0 refers to an area where the exposure area of the semiconductor substrate is divided into a plurality of grids of rectangular areas of the same size when performing a photolithography process, and the pattern within the grid is complete.
[0052] The second area may include a plurality of incomplete exposure areas (as a non-limiting example, Figure 2 As shown in the schematic diagrams St1 and St2), the incomplete exposure area refers to the area where the exposure area of the semiconductor substrate is divided into a grid of multiple rectangular areas of the same size when performing the photolithography process, and the pattern within the grid is incomplete.
[0053] It is understandable that, since the pattern in the incomplete exposure area is incomplete, in a specific implementation, each incomplete exposure area is often not exposed, but each complete exposure area is exposed to reduce the exposure cost and improve the exposure efficiency.
[0054] By dividing the semiconductor substrate into the first area and the second area, when performing the subsequent photolithography process, the first exposure process can be performed on the second area (i.e., the incomplete exposure area) to expose the front layer alignment mark in advance; then, the second exposure process is performed with the exposed front layer alignment mark as a reference. Since the second area is an incomplete exposure area, the exposure accuracy requirement can be reduced, as long as the front layer alignment mark can be exposed, thereby reducing the difficulty of the photolithography process.
[0055] In this embodiment, Figure 2 As shown, the plurality of incomplete exposure regions include a first incomplete exposure region St1 and a second incomplete exposure region St2 , and the first incomplete exposure region St1 and the second incomplete exposure region St2 are disposed at relative positions on the semiconductor substrate 100 .
[0056] By arranging the first incomplete exposure area St1 and the second incomplete exposure area St2 at relative positions on the semiconductor substrate 100, after performing the first exposure process, the front layer alignment marks located on both sides of the first area can be exposed, so that the second exposure process can be aligned based on at least two front layer alignment marks, and the area to be exposed in the second exposure process can be accurately determined.
[0057] And when the second exposure process is performed for alignment operation, the photoresist on the front layer alignment mark is removed, and most of the detection light can be transmitted to the front layer alignment mark. In this way, when most of the detection light is irradiated to the front layer alignment mark, the intensity of the alignment signal can be improved, thereby improving the accuracy of the alignment operation.
[0058] It should be noted that, first, Figure 2 The schematic diagram of the exposure area division of the semiconductor substrate shown is only an example for illustrating the difference between different areas of the semiconductor substrate to highlight the basis for dividing the first area and the second area. In some other embodiments, the semiconductor substrate can be further divided into more areas; second, Figure 2 Two incomplete exposure areas are illustrated. In a specific implementation, there may be more incomplete exposure areas or one incomplete exposure area, and this solution does not impose any limitation on this.
[0059] S110, forming a front layer alignment mark on the semiconductor substrate in the first area and the second area.
[0060] The front layer alignment mark is used as an alignment mark between different layers to achieve alignment between layers.
[0061] By forming the front-layer alignment marks on both the first region and the second region of the semiconductor substrate, the front-layer alignment marks on the semiconductor substrate in the second region can be exposed in advance to perform the alignment operation of the second exposure process.
[0062] In this embodiment, the method of forming the front layer alignment mark on the semiconductor substrate in the first region and the second region may include at least one of the following:
[0063] Method 1: forming a layer to be processed on the semiconductor substrate; forming a groove in the layer to be processed, wherein the groove exposes the surface of the semiconductor substrate and the groove serves as an alignment mark of the front layer, wherein in the step of forming a photoresist, the photoresist covers the surface of the layer to be processed and fills the groove.
[0064] In this way, the photoresist can play a protective role, preventing the to-be-processed layer located on the first region from being etched during the photolithography process, thereby improving the electrical properties of the finally formed semiconductor device, such as the withstand voltage performance.
[0065] Method 2: forming a dielectric layer on the semiconductor substrate; forming an opening in the dielectric layer, wherein the opening exposes the surface of the semiconductor substrate; forming a layer to be processed in the opening; after forming the layer to be processed, removing the dielectric layer, and using the side wall of the layer to be processed adjacent to the surface of the semiconductor substrate as the front layer alignment mark, wherein in the step of forming the photoresist, the photoresist covers the surface of the layer to be processed and fills the groove.
[0066] It is to be understood that the above two methods of forming the front layer alignment mark are only illustrative and should not be construed as limiting the present invention. For example, in some embodiments, after forming a to-be-processed layer with a front layer alignment mark on another semiconductor substrate, the to-be-processed layer can be transferred to the semiconductor substrate.
[0067] S120, forming a photoresist, wherein the photoresist covers the front layer alignment mark.
[0068] The main function of photoresist is to transfer the pattern on the mask to the surface of the semiconductor substrate. Through the exposure and development process, the chemical properties of the photoresist will change, thus forming a tiny structure corresponding to the mask pattern.
[0069] In this embodiment, a photoresist is formed on a semiconductor substrate by spin coating.
[0070] S130, performing a first exposure process on the photoresist in a portion of the second area, and then removing the exposed photoresist to expose the front layer alignment mark located in the portion of the second area.
[0071] Specifically, in step S120, a photoresist is formed on the entire semiconductor substrate, and the thickness of the formed photoresist is relatively thick, making it impossible or difficult to detect the position of the front layer alignment mark, thereby making it difficult to perform a photolithography process on the target area (eg, the first area).
[0072] Taking into account that the semiconductor substrate on the second area is inactive, or no device is formed on the semiconductor substrate on the second area, the photoresist in a portion of the second area can be exposed for the first time to expose the front layer alignment mark located in the portion of the second area; and when performing the first exposure process, the conditions required can be lowered, as long as the front layer alignment mark is exposed, which reduces the difficulty of implementation and can improve the alignment efficiency of the second exposure process.
[0073] S140, performing a second exposure process on the semiconductor substrate based on the exposed front layer alignment mark.
[0074] Specifically, after exposing the front-layer alignment mark located in the second area, an alignment operation can be performed with the front-layer alignment mark as a reference. By performing a detection operation, the position of the alignment mark can be determined. Combined with the previously known relative position relationship between the first area and the second area, the boundary range of the first area can be determined. Thus, the exposure range of the semiconductor substrate during the second exposure process can be determined to achieve precise processing.
[0075] In short, by pre-exposing the front-layer alignment mark of the second area, when performing the second exposure process, the problem of being unable to perform subsequent processes due to failure to detect the front-layer alignment mark will not occur.
[0076] In this embodiment, when forming the photoresist, the photoresist is coated on the entire surface of the semiconductor substrate. When performing the photolithography process, there are different execution timings. Therefore, before performing the first exposure process on the photoresist of a portion of the second area, the forming method further includes:
[0077] A process bill for the semiconductor substrate is configured.
[0078] Specifically, the process list defines all the process steps performed on the semiconductor substrate, as well as the specific implementation methods and parameters of each process step, so that the process list must include the parameters of the lithography process of the semiconductor substrate, so that the process list can be modified or set during the manufacturing process.
[0079] In a specific embodiment, the process list includes the number of exposure processes and exposure conditions, wherein one exposure process corresponds to one exposure condition.
[0080] Specifically in this embodiment, the exposure processing is performed twice, and the exposure condition of the first exposure processing is to select at least one incomplete exposure area in the second area and to remove the first area, and the exposure condition of the second exposure processing is to select each complete exposure area in the first area and to remove part or all of the incomplete exposure areas in the second area.
[0081] In other words, through the control interface of the manufacturing system, the area where photolithography is to be performed can be selected, so that the front layer alignment mark of the second area can be exposed in advance, so that the subsequent process can complete the alignment operation to accurately find other locations on the semiconductor substrate that need to be exposed.
[0082] In order to better understand and illustrate the manufacturing process in this scheme, Figures 3 to 8 , an exemplary description is given.
[0083] See also Figure 3 , a semiconductor substrate 100 is provided, wherein the semiconductor substrate 100 is divided into a first region I and a second region II, wherein the first region I includes a plurality of complete exposure regions, and the second region II includes a plurality of incomplete exposure regions.
[0084] The semiconductor substrate 100 may provide a process operation basis for a formation process of a power device, wherein the power device may include a longitudinal double diffused metal oxide semiconductor structure LDMOS and / or a vertical double diffused metal oxide semiconductor structure VDMOS.
[0085] In this embodiment, the material of the semiconductor substrate 100 is silicon. In other embodiments, the material of the semiconductor substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the semiconductor substrate may also be other types of substrates such as a silicon substrate on an insulator or a germanium substrate on an insulator. The material of the semiconductor substrate may be a material suitable for process requirements or easy to integrate.
[0086] The first region I may refer to a region where a device structure is formed on the semiconductor substrate 100 , and the first region defines a location of a semiconductor device that is finally formed.
[0087] The second region II may refer to a region on the semiconductor substrate 100 where no device structure is formed, or a region that does not play a role in a finally formed semiconductor device.
[0088] Specifically for this solution, the main function of the second area II is to be used for alignment.
[0089] See also Figure 4 , a front layer alignment mark is formed on the semiconductor substrate 100 in the first region I and the second region II.
[0090] The alignment mark plays an alignment role. By performing a detection operation on the alignment mark of the previous layer, the relative position between the current layer and the previous layer can be determined, thereby achieving alignment.
[0091] In this embodiment, for ease of understanding, the front layer alignment mark on the first region I is recorded as the front layer alignment mark M0, and the front layer alignment marks on the second region II are recorded as the front layer alignment marks M1 and M2 respectively.
[0092] In this embodiment, one of the ways to form the front layer alignment mark may be:
[0093] A layer to be processed 104 is formed on the semiconductor substrate 100 ; a groove (not shown) is formed in the layer to be processed 104 , wherein the groove exposes the surface of the semiconductor substrate 100 and serves as an alignment mark for the front layer.
[0094] In other words, the space formed by the sidewalls of the adjacent to-be-processed layer 104 and the surface of the semiconductor substrate 100 is used as a front-layer alignment mark.
[0095] The layer to be processed 104 provides a process basis for forming a front-layer alignment mark, and when the layer to be processed 104 is a metal contact layer, the layer to be processed 104 also determines the withstand voltage value of the power device.
[0096] In this embodiment, a physical vapor deposition process may be used to form the to-be-processed layer 104. In some other embodiments, chemical vapor deposition, atomic vapor deposition, etc. may also be used to form the to-be-processed layer.
[0097] In this embodiment, the layer to be processed 104 may be a metal contact layer, which determines the withstand voltage of the power device. The thicker the metal contact layer is, the greater the withstand voltage of the power device is.
[0098] The material of the metal contact layer may include one or more of Ni, W, Ti, TiN, Ta, Pt, Al, Cu, Ag, Au and Co.
[0099] In a specific embodiment, the material of the metal contact layer is an alloy of Al and Cu.
[0100] It should be noted that when the layer to be treated is a metal contact layer, Figure 4 When the front layer alignment mark is formed in the manner shown, the hardness of the metal contact layer should be low and easy to handle. For example, the material of the metal contact layer can be aluminum. When the metal contact layer is other types of metal materials, the metal contact layer and the front layer alignment mark located in the adjacent metal contact layer can be formed based on the Damascus process.
[0101] In this embodiment, along the normal direction of the surface of the semiconductor substrate 100, the thickness D1 of the layer to be processed 104 is 3 μm to 5 μm.
[0102] By making the thickness D1 of the layer to be processed 104 greater than or equal to 3μm, the withstand voltage value of the power device can be increased, so that the power device has a higher withstand voltage level; by making the thickness D1 of the layer to be processed 104 less than or equal to 5μm, the optical path of the detection light can be shortened accordingly, so that when the detection light is used to detect the first alignment structure, the intensity of the detection signal is increased, thereby improving the alignment accuracy, so as to better perform the second exposure process.
[0103] In a specific embodiment, the thickness of the to-be-processed layer 104 is 4 μm. In other words, when the to-be-processed layer 104 is a metal contact layer, the thickness of the metal contact layer is 4 μm.
[0104] See next Figure 3 and Figure 4 Before forming the to-be-processed layer 104 on the semiconductor substrate 100 , the forming method further includes: forming a dielectric layer 102 on the semiconductor substrate 100 .
[0105] The dielectric layer 102 protects the semiconductor substrate 100 and can be used as a through hole of the CT (contact) layer to connect the semiconductor substrate 100 with the peripheral metal wire, thereby protecting the semiconductor substrate 100 from the external environment and preventing the diffusion of the interconnect structure.
[0106] In this embodiment, an atomic layer deposition (ALD) process may be used to form the dielectric layer 102 on the semiconductor substrate 100. The thickness uniformity of the dielectric layer 102 may be improved through multiple atomic layer deposition cycles.
[0107] In some other embodiments, other deposition processes (such as chemical vapor deposition processes) may be used to form a dielectric layer on the semiconductor substrate.
[0108] In this embodiment, the material of the dielectric layer 102 may include a dielectric material, wherein the dielectric material may be BPSG or USG.
[0109] In some other embodiments, the material of the dielectric layer may also be silicon oxide, silicon nitride, etc.
[0110] In this embodiment, along the normal direction of the surface of the semiconductor substrate 100 , the thickness D2 of the dielectric layer 102 is 0.5 μm to 0.7 μm.
[0111] By making the thickness D2 of the dielectric layer 102 greater than or equal to 0.5 μm, the dielectric layer 102 can cover the surface of the semiconductor substrate 100 and improve the surface flatness of the semiconductor substrate 100; by making the thickness D2 of the dielectric layer 102 less than or equal to 0.7 μm, the area of the entire semiconductor device can be reduced accordingly and the power consumption can be reduced.
[0112] In a specific embodiment, the thickness D2 of the dielectric layer 102 is 0.6 μm.
[0113] See next Figure 4 On the basis of forming the dielectric layer 102, the front layer alignment mark also exposes a portion of the surface of the dielectric layer 102 to provide a processing space for forming a through hole of the CT layer.
[0114] In this embodiment, the semiconductor substrate 100 formed with the to-be-processed layer 104 usually needs to be rotated between multiple machines, and there is a risk that the to-be-processed layer 104 is exposed to the air. When the to-be-processed layer 104 is in a humid environment or an environment full of corrosive gases, the flatness of the surface of the to-be-processed layer 104 is easily damaged, thereby reducing the performance of the power device, such as reducing the withstand voltage value of the power device, or increasing the contact resistance value due to poor interface quality, thereby reducing the electrical performance of the power device.
[0115] See also Figure 5 , forming a photoresist 108 (see Figure 6 ), a protection layer 106 is formed on the layer to be processed 104, and the protection layer 106 is also located in the groove (or called the front layer alignment mark).
[0116] The protection layer 106 is used to protect the layer to be processed 104 to improve the surface morphology of the layer to be processed 104 .
[0117] In this embodiment, a physical vapor deposition process is used to form the protective layer 106. The physical vapor deposition process can reduce the implementation cost, is compatible with existing processes, and is relatively easy to implement.
[0118] In the present embodiment, the material of the protection layer 106 includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon carbonitride oxycarbon, boron nitride and boron carbonitride.
[0119] In a specific embodiment, the material of the protection layer 106 is silicon nitride.
[0120] In this embodiment, along the normal direction of the surface of the semiconductor substrate 100 , the thickness of the protection layer 106 is 0.8 μm to 1 μm.
[0121] By making the thickness of the protective layer 106 greater than or equal to 0.8 μm, the risk of the surface of the layer to be processed 104 being exposed to the air again due to the consumption of the protective layer 112 in the subsequent process can be avoided, thereby improving the morphology of the layer to be processed 104; by making the thickness of the protective layer 106 less than or equal to 0.8 μm, the area of the power device can be reduced, thereby reducing power consumption.
[0122] In a specific embodiment, the thickness of the protection layer 106 is 0.9 μm.
[0123] See also Figure 6 , forming a photoresist 108, wherein the photoresist 108 covers the front layer alignment marks M0, M1 and M2.
[0124] The photoresist 108 can transfer the pattern on the mask to the surface of the semiconductor substrate 100 and plays a role in protecting the layer to be processed 104 .
[0125] Specifically, in this solution, the layer to be processed 104 located in the first area I will be used as a device layer and needs to be protected. By making the photoresist 108 cover the surface of the layer to be processed 104 and fill the grooves, the processing layer 104 can be protected when performing the first exposure process.
[0126] In this embodiment, the photoresist 108 is formed by a spin coating process.
[0127] In this embodiment, along the normal direction of the surface of the semiconductor substrate, the thickness D3 of the photoresist 108 is 4 μm to 6 μm.
[0128] By making the thickness D3 of the photoresist 108 less than or equal to 6μm, the time required for opening the photoresist 108 during the exposure process can be reduced, thereby improving manufacturing efficiency; by making the thickness D3 of the photoresist 108 greater than or equal to 4μm, during the first exposure process, even if a portion of the photoresist 108 located in the first area I is consumed, a portion of the photoresist 108 can still be retained, thereby still being able to protect the layer to be processed 104 located in the first area I, thereby being able to improve the withstand voltage value of the power device.
[0129] In a specific embodiment, the thickness D3 of the photoresist 108 is 5 μm.
[0130] It should be noted that when forming the protection layer 106 , in the step of forming the photoresist 108 , the photoresist 108 also covers the surface of the protection layer 106 .
[0131] See also Figure 7, a first exposure process is performed on a portion of the photoresist 108 in the second region II, and then the exposed photoresist 108 is removed to expose the front layer alignment marks M1 and M2 located in the portion of the second region.
[0132] The specific implementation method of the first exposure process can refer to the description in the existing solution.
[0133] See also Figure 8 , taking the exposed front layer alignment marks M1 and M2 as reference, performing a second exposure process on the semiconductor substrate 100 .
[0134] Specifically, an alignment operation can be performed based on the exposed front layer alignment marks M1 and M2 to determine the range of the second exposure process, so that at least the first area I can be exposed for the second time, which facilitates the continuation of the processing process of the layer 104 to be processed.
[0135] It is understandable that the above-mentioned embodiments provide a variety of implementation schemes, and the various implementation schemes can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible implementation schemes, which can all be considered as embodiment schemes disclosed and open in the embodiments of this application.
[0136] An embodiment of the present invention further provides a lithography device corresponding to the above-mentioned manufacturing method, which is described in detail below through specific embodiments with reference to the accompanying drawings.
[0137] See also Fig. 9 A structural schematic diagram of a manufacturing device in an embodiment of the present invention is shown in FIG. Fig. 9 As shown, the lithography machine device M may include:
[0138] A providing unit M1 is used to provide a semiconductor substrate, wherein the semiconductor substrate is divided into a first area and a second area, wherein the first area includes a plurality of complete exposure areas, and the second area includes a plurality of incomplete exposure areas;
[0139] A forming unit M2 is used to form a front layer alignment mark on the semiconductor substrate in the first area and the second area;
[0140] The exposure unit M3 is used to form a photoresist and perform a first exposure process on the photoresist in a portion of the second area, then remove the exposed photoresist to expose the front layer alignment mark located in the portion of the second area, and perform a second exposure process on the semiconductor substrate based on the exposed front layer alignment mark, wherein the photoresist covers the front layer alignment mark.
[0141] The specific implementation of the providing unit M1 , the forming unit M2 and the exposing unit M3 may refer to the above examples.
[0142] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A manufacturing method, characterized in that: include: Providing a semiconductor substrate, wherein the semiconductor substrate is divided into a first area and a second area, wherein the first area includes a plurality of complete exposure areas, and the second area includes a plurality of incomplete exposure areas; forming a front layer alignment mark on the semiconductor substrate in the first region and the second region; forming a photoresist, wherein the photoresist covers the front layer alignment mark; Performing a first exposure process on the photoresist in a portion of the second area, and then removing the exposed photoresist to expose the front layer alignment mark located in the portion of the second area; The semiconductor substrate is subjected to a second exposure process based on the exposed front layer alignment mark as a reference.
2. The manufacturing method according to claim 1, characterized in that: The plurality of incomplete exposure regions include a first incomplete exposure region and a second incomplete exposure region, and the first incomplete exposure region and the second incomplete exposure region are disposed at opposite positions of the semiconductor substrate.
3. The manufacturing method according to claim 1, characterized in that: Before performing the first exposure process on the photoresist of a portion of the second area, the forming method further comprises: A process list for the semiconductor substrate is configured, the process list including the number of exposure processes and exposure conditions, wherein the number of exposure processes is two, and the exposure condition for the first exposure process is to select at least one incomplete exposure area in the second area and to remove the first area, and the exposure condition for the second exposure process is to select each complete exposure area in the first area and to remove some or all of the incomplete exposure areas in the second area.
4. The manufacturing method according to claim 1, characterized in that: The method of forming the front layer alignment mark on the semiconductor substrate in the first region and the second region comprises at least one of the following: forming a layer to be processed on the semiconductor substrate; forming a groove in the layer to be processed, wherein the groove exposes the surface of the semiconductor substrate and serves as an alignment mark of the front layer; forming a dielectric layer on the semiconductor substrate; forming an opening in the dielectric layer, wherein the opening exposes a surface of the semiconductor substrate; forming a layer to be processed in the opening; After forming the layer to be processed, removing the dielectric layer, and using the area between the sidewall of the layer to be processed and the surface of the semiconductor substrate as the front layer alignment mark; In the step of forming the photoresist, the photoresist covers the surface of the layer to be processed and fills the groove.
5. The manufacturing method according to claim 4, characterized in that: The layer to be processed is a metal contact layer.
6. The manufacturing method according to claim 4, characterized in that: Along the normal direction of the surface of the semiconductor substrate, the thickness of the layer to be processed is 3 μm to 5 μm.
7. The manufacturing method according to claim 4, characterized in that: Before forming the layer to be processed on the semiconductor substrate, the forming method further comprises: forming a dielectric layer on the semiconductor substrate; The front layer alignment mark exposes the surface of the dielectric layer.
8. The manufacturing method according to claim 7, characterized in that: Along the normal direction of the surface of the semiconductor substrate, the thickness of the dielectric layer is 0.5 μm to 0.7 μm.
9. The manufacturing method according to claim 4, characterized in that: Before forming the photoresist, the forming method further comprises: forming a protective layer on the layer to be processed, wherein the protective layer is also located in the groove; In the step of forming the photoresist, the photoresist also covers the surface of the protective layer.
10. The manufacturing method according to claim 1, characterized in that: Along the normal direction of the surface of the semiconductor substrate, the thickness of the photoresist is 4 μm to 6 μm.
11. A photolithography device, characterized in that: include: A providing unit, configured to provide a semiconductor substrate, wherein the semiconductor substrate is divided into a first region and a second region, wherein the first region includes a plurality of complete exposure regions, and the second region includes a plurality of incomplete exposure regions; A forming unit, configured to form a front layer alignment mark on the semiconductor substrate in the first region and the second region; An exposure unit is used to form a photoresist and perform a first exposure process on the photoresist in a portion of the second area, then remove the exposed photoresist to expose a front layer alignment mark located in the portion of the second area, and perform a second exposure process on the semiconductor substrate based on the exposed front layer alignment mark, wherein the photoresist covers the front layer alignment mark.