Storage array and storage device

Abstract

A storage array and a storage device, the storage array comprising: a plurality of storage modules arranged along a first direction; the storage module comprises a first data block and a second data block, the second data block and the first data block are arranged along a second direction, and the second direction intersects with the first direction; the data induction amplification unit is located between the first data block and the second data block in the second direction; the first data line is suitable for realizing connection between the data induction amplification unit and the first data block; and the second data line is suitable for realizing connection between the data induction amplification unit and the second data block. The data induction amplification unit is located between the first data block and the second data block, the length of the first data line and the length of the second data line are reduced, then the loads of the first data line and the second data line are reduced, the access delay of the first data line and the second data line is reduced, energy consumption is reduced, and the reading speed is increased.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a storage array and a storage device. Background Art

[0002] A semiconductor memory device is a semiconductor device capable of storing a plurality of data in a plurality of unit cells. A random access memory device is a memory device capable of storing data by accumulating charges in a capacitor.

[0003] With the advancement of semiconductor technology, highly integrated memory devices are developed. In particular, in order to highly integrate random access memory devices, it is necessary to reduce the area of ​​a cell block formed by a plurality of unit cells that occupies most of the area. Therefore, when a signal holding data stored in a unit cell is output to the outside, the signal must be amplified in a data sense amplifier before the signal is output.

[0004] However, current data sense amplifiers still have some deficiencies. Summary of the invention

[0005] The problem solved by the present invention is how to arrange a data sensing amplifier to reduce the length of a data line connected to the data sensing amplifier in a storage array, so as to reduce the load on the data line and reduce the area of ​​a random access storage device.

[0006] To solve the above problems, the present invention provides a storage array, comprising: a plurality of storage modules, the plurality of storage modules are arranged along a first direction; the storage modules comprise: a first data block and a second data block, the second data block and the first data block are arranged along a second direction, wherein the second direction intersects with the first direction; a data sensing amplification unit, the data sensing amplification unit is located between the first data block and the second data block along the second direction; a first data line, the first data line extends along the second direction, the first data line is suitable for realizing the connection between the data sensing amplification unit and the first data block; a second data line, the second data line extends along the second direction, the second data line is suitable for realizing the connection between the data sensing amplification unit and the second data block.

[0007] Optionally, the storage module has a plurality of the first data blocks, and along the second direction, the plurality of the first data blocks are arranged in sequence in a direction away from the second data block; the storage module has a plurality of the second data blocks, and along the second direction, the plurality of the second data blocks are arranged in sequence in a direction away from the first data block.

[0008] Optionally, a difference between the number of first data blocks arranged along the second direction and the number of second data blocks arranged along the second direction is smaller than a threshold.

[0009] Optionally, a difference between the length of the first data line and the length of the second data line is smaller than a threshold.

[0010] Optionally, the storage module also includes: a word line driver, the word line driver is located on one side of the corresponding data block along the first direction, the data block is one of the first data block and the second data block; the data sensing amplification unit is located in the word line driver of the first data block and the word line driver of the second data block.

[0011] Optionally, the data line is located between the word line driver and the corresponding data block, wherein the data line is one of the first data line and the second data line.

[0012] Optionally, the storage module also includes: a third data block and a fourth data block, the third data block is located along the second direction of the fourth data block, the third data block and the first data block are arranged along the first direction, and the fourth data block and the second data block are arranged along the first direction; along the first direction, the data sensing amplification unit is located between the third data block and the first data block; the storage array also includes: a third data line, the third data line extends along the second direction, the third data line is suitable for realizing the connection between the data sensing amplification unit and the third data block; the fourth data line, the fourth data line extends along the second direction, and the fourth data line is suitable for realizing the connection between the data sensing amplification unit and the fourth data block.

[0013] Optionally, the third data line is located at a side of the third data block away from a word line driver of the third data block; and the fourth data line is located at a side of the fourth data block away from a word line driver of the fourth data block.

[0014] Optionally, it further includes: a direction decoder, wherein the direction decoder is located on one side of the storage module along the second direction.

[0015] Optionally, the data sensing amplification unit includes: a selector and a data sensing amplifier, the output end of the selector is connected to an input end of the data sensing amplifier, the input end of the selector is connected to a data line one-to-one, and the data line is one of the first data line and the second data line.

[0016] Optionally, it further includes: a control unit, which is suitable for sending a control signal to control the connection between the input end of the selector and the data line.

[0017] Optionally, the data sensing amplification unit includes: a selector and a data sensing amplifier, the output end of the selector is connected to an input end of the data sensing amplifier, the input end of the selector is connected to a data line one-to-one, wherein the data line is one of the first data line, the second data line, the third data line and the fourth data line.

[0018] Optionally, it further includes: a control unit, which is suitable for sending a control signal to control the connection between the input end of the selector and the data line.

[0019] Optionally, an output line of the data sensing and amplifying unit is connected to an auxiliary circuit along a first direction.

[0020] Correspondingly, the present invention further provides a storage device, which includes the storage array as described in any one of the above items.

[0021] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0022] In the storage array of the technical solution of the present invention, the data sensing amplification unit is located between the first data block and the second data block, which reduces the distance between the data sensing amplification unit and the first data block, and reduces the distance between the data sensing amplification unit and the second data block, thereby reducing the length of the first data line connecting the first data block and the data sensing amplification unit, and reducing the length of the second data line connecting the second data block and the data sensing amplification unit, thereby reducing the load of the first data line and the second data line, and reducing the access delay of the first data line and the second data line, which is beneficial to reducing energy consumption and improving reading speed.

[0023] In an optional solution of the present invention, the data sensing amplification unit includes: a selector and a data sensing amplifier, the output end of the selector is connected to an input end of the data sensing amplifier, and the input end of the selector is connected to a data line in a one-to-one correspondence, wherein the data line is one of the first data line, the second data line, the third data line, and the fourth data line. Compared with setting a plurality of data sensing amplifiers, setting the selector to achieve multiplexing of one data sensing amplifier reduces the number of data sensing amplifiers, thereby reducing the area of ​​the storage array. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a structural schematic diagram of a storage array of the prior art;

[0025] Figure 2 It is a schematic diagram of the structure of a data sensing amplifier in a storage array of the prior art;

[0026] Figure 3 is a schematic diagram of the structure of a storage array according to an embodiment of the present invention;

[0027] Figure 4 is a structural schematic diagram of a data sensing and amplifying unit in a storage array according to an embodiment of the present invention;

[0028] Figure 5 is a timing diagram of a selector in a memory array according to an embodiment of the present invention;

[0029] Figure 6 is a schematic structural diagram of a storage array according to another embodiment of the present invention;

[0030] Figure 7 is a structural schematic diagram of a data sensing and amplifying unit in a storage array according to another embodiment of the present invention;

[0031] Figure 8 is a timing diagram of a selector in a storage array according to another embodiment of the present invention;

[0032] Fig. 9 FIG. 4 is a timing diagram of a data sensing amplifier in a memory array according to another embodiment of the present invention. DETAILED DESCRIPTION

[0033] As can be seen from the background technology, the prior art still has the problem of too long data lines and heavy loads. The reasons for the problems are now analyzed in conjunction with an embodiment:

[0034] Please refer to Figure 1 The storage array includes: a plurality of storage modules 100, each having a plurality of data blocks (not shown in the figure), and the plurality of storage modules 100 are arranged along a first direction X; a data sensing amplifier 101, the data sensing amplifier 101 is located at one side of the storage module 100 along a second direction Y, wherein the second direction Y intersects with the first direction X; and a data line 102, the data line 102 extends along the second direction Y, and the data line 102 is suitable for realizing the connection between the data sensing amplifier 101 and the storage module 100.

[0035] Please refer to Figure 2 One input terminal of the data sensing amplifier 101 is suitable for being connected to the data line 102, and the signal transmitted by the data line 102 is the signal DL. Another input terminal (not shown in the figure) of the data sensing amplifier 101 is suitable for inputting a reference voltage VREF. The output terminal OUT of the data sensing amplifier 101 is suitable for being connected to an auxiliary circuit.

[0036] Through research, it is found that the data sensing amplifier 101 is located at one end of the storage module 100. In order to achieve connection with the farthest data block, the data line 102 extends from one end of the storage module 100 to the other end along the second direction Y, and the data line 102 is relatively long. The larger line length causes a larger load on the data line 102, resulting in a lower reading speed of the storage array.

[0037] To solve the technical problem, the present invention provides a storage array, comprising: a plurality of storage modules, the plurality of storage modules are arranged along a first direction; the storage modules comprise: a first data block and a second data block, the second data block and the first data block are arranged along a second direction, wherein the second direction intersects with the first direction; a data sensing amplification unit, the data sensing amplification unit is located between the first data block and the second data block along the second direction; a first data line, the first data line extends along the second direction, the first data line is suitable for realizing the connection between the data sensing amplification unit and the first data block; a second data line, the second data line extends along the second direction, the second data line is suitable for realizing the connection between the data sensing amplification unit and the second data block.

[0038] In the storage array of the technical solution of the present invention, the data sensing amplification unit is located between the first data block and the second data block, which reduces the distance between the data sensing amplification unit and the first data block, and reduces the distance between the data sensing amplification unit and the second data block, thereby reducing the length of the first data line connecting the first data block and the data sensing amplification unit, and reducing the length of the second data line connecting the second data block and the data sensing amplification unit, thereby reducing the load of the first data line and the second data line, and reducing the access delay of the first data line and the second data line, which is beneficial to reducing energy consumption and improving reading speed.

[0039] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0040] Figure 3 is a schematic diagram of the structure of a storage array according to an embodiment of the present invention, Figure 4 yes Figure 3 A schematic diagram of the structure of the data sensing and amplifying unit of the storage array in FIG. Figure 5 yes Figure 4 Timing diagram of the selector of the data sense amplifier unit.

[0041] Please refer to Figure 3The storage array includes: a plurality of storage modules 200, and the plurality of storage modules 200 are arranged along a first direction X. The storage module 200 includes a plurality of data blocks (MAT), and the plurality of data blocks are arranged in sequence along a second direction Y, wherein the second direction Y intersects with the first direction X.

[0042] The data block is suitable for storing a storage unit.

[0043] The data block has a plurality of bit lines (BitLine, referred to as BL) and a plurality of local word lines (Local WordLine, referred to as LWL), the extension direction of the bit lines (not marked in the figure) intersects with the extension direction of the local word lines (not marked in the figure), and the local word lines are connected to at least part of the bit lines. Specifically, in some embodiments of the present invention, the first direction X is the extension direction of the local word lines, and the second direction Y is the extension direction of the bit lines.

[0044] Please continue to refer to Figure 3 The multiple data blocks in the storage module 200 are divided into first data blocks 201 and second data blocks 202, that is, a part of the data blocks are first data blocks 201, and a part of the data blocks are second data blocks 202.

[0045] It should be noted that Figure 3 In some of the embodiments shown, the multiple data blocks in the storage module 200 are only divided into first data blocks 201 and second data blocks 202, that is, a part of the data blocks are first data blocks 201, and the remaining part of the data blocks are second data blocks 202.

[0046] The second data block 202 and the first data block 201 are arranged along a second direction Y.

[0047] For details, please refer to Figure 3 In some embodiments of the present invention, the storage module 200 has a plurality of the first data blocks 201 , and along the second direction Y, the plurality of the first data blocks 201 are arranged in sequence in a direction away from the second data block 202 .

[0048] For details, please refer to Figure 3 In some embodiments of the present invention, the storage module 200 has a plurality of second data blocks 202 , and along the second direction Y, the plurality of second data blocks 202 are arranged in sequence in a direction away from the first data block 201 .

[0049] The difference between the number of first data blocks 201 arranged along the second direction Y and the number of second data blocks 202 arranged along the second direction Y is less than a threshold value. The threshold value is determined according to actual process requirements. The difference between the number of first data blocks 201 arranged along the second direction Y and the number of second data blocks 202 arranged along the second direction Y is less than a threshold value, so that the difference between the number of first data blocks 201 arranged along the second direction Y and the number of second data blocks 202 arranged along the second direction Y is small. Specifically, in some embodiments of the present invention, the number of first data blocks 201 arranged along the second direction Y and the number of second data blocks 202 arranged along the second direction Y are equal, that is, in the storage module 200, half of the data blocks are first data blocks 201, and the remaining number of data blocks are second data blocks 202. For examples, please refer to Figure 3 In some embodiments of the present invention, the number of the first data blocks 201 arranged along the second direction Y and the number of the second data blocks 202 arranged along the second direction Y are both 2.

[0050] Please continue to refer to Figure 3 The storage module 200 further includes: a word line driver 203, wherein the word line driver 203 is located on one side of the corresponding data block along the first direction X, and the data block is one of the first data block 201 and the second data block 202.

[0051] The word line driver 203 is connected to the corresponding data block. Specifically, the word line driver 203 is connected to the local word line of the corresponding data block. For example: there are M local word lines in one data block, and the word line driver 203 is suitable for connecting to one local word line among the M local word lines, so as to read the information of the bit line connected to the local word line.

[0052] The first direction X is the extension direction of the local word line, so the word line driver 203 and the corresponding data block are adjacently arranged along the first direction X. Figure 3 As shown, all word line drivers 203 in the storage module 200 are located on the same side of the corresponding data block along the first direction X.

[0053] Specifically, in some embodiments of the present invention, the word line drivers 203 correspond to the data blocks one by one, that is, in the first direction X, each word line driver 203 corresponds to one data block, and one side of each word line driver 203 has one first data block 201 or one data block 202. For example, Figure 3 As shown, the first data block 201 is located on the right side of the word line driver 203 or the second data block 202 is located on the right side of the word line driver 203 .

[0054] Please continue to refer to Figure 3The storage module 200 includes: a read amplifier 211, and the read amplifier 211 is located between two adjacent data blocks along the second direction Y.

[0055] The read amplifier 211 is connected to the corresponding data block. Specifically, the read amplifier 211 is connected to the bit line of the corresponding data block. For example, one data block has N bit lines, and the read amplifier 211 is suitable for connecting to the N bit lines to read the information of the N bit lines.

[0056] Please continue to refer to Figure 3 The storage module 200 includes: a data sensing and amplifying unit 204. Along the second direction Y, the data sensing and amplifying unit 204 is located between the first data block 201 and the second data block 202.

[0057] Specifically, Figure 3 As shown, the data sensing amplification unit 204 is located between two adjacent data blocks along the second direction Y in the storage module 200; along the second direction Y, multiple data blocks in the storage module 200 are arranged on both sides of the data sensing amplification unit 204, wherein the data block located on one side of the data sensing amplification unit 204 along the second direction Y is the first data block 201, and the data block located on the other side of the data sensing amplification unit 204 along the second direction is the second data block 202.

[0058] For details, please continue to refer to Figure 3 , the data sensing amplifying unit 204 is located between the word line driver 203 of the first data block 201 and the word line driver 203 of the second data block 202, that is, the data sensing amplifying unit 204 is located between the word line driver 203 of the first data block 201 and the word line driver 203 of the adjacent second data block 202.

[0059] Specifically, in some embodiments of the present invention, the number of first data blocks 201 arranged along the second direction Y and the number of second data blocks 202 arranged along the second direction Y are equal. Therefore, along the second direction Y, the data sensing amplification unit 204 is located in the middle position of the storage array, that is, along the second direction Y, the distance from the data sensing amplification unit 204 to one side of the storage module 200 is approximately equal to the distance from the data sensing amplification unit 204 to the other side of the storage module 200.

[0060] In some embodiments of the present invention, the output line of the data sensing and amplifying unit 204 is connected to the auxiliary circuit along the first direction X. Specifically, Figure 3In some embodiments shown, the auxiliary circuit 210 is located at one side of the storage module 200 along the first direction X, and the connection line between the data sensing and amplifying unit 204 and the auxiliary circuit 210 extends along the first direction X.

[0061] Combined with reference Figure 3 The storage module 200 includes: a first data line 207, the first data line 207 extends along the second direction Y, and the first data line 207 is suitable for realizing the connection between the data sensing and amplifying unit 204 and the first data block 201; a second data line 208, the second data line 208 extends along the second direction Y, and the second data line 208 is suitable for realizing the connection between the data sensing and amplifying unit 204 and the second data block 202.

[0062] Specifically, one end of the first data line 207 is connected to the data sensing amplifying unit 204, and the other end of the first data line 207 extends along the second direction Y away from the data sensing amplifying unit 204; one end of the second data line 208 is connected to the data sensing amplifying unit 204, and the other end of the second data line 208 extends along the second direction Y away from the data sensing amplifying unit 204.

[0063] Since the first data block 201 and the second data block 202 are arranged on both sides of the data sensing and amplifying unit 204 along the second direction Y, the extension direction of the other end of the second data line 208 is different from the extension direction of the other end of the first data line 207 .

[0064] The data sensing and amplifying unit 204 is located between the first data block 201 and the second data block 202. The length of the first data line 207 connecting the first data block 201 and the data sensing and amplifying unit 204 is short, and the load of the first data line 207 is small. The length of the second data line 208 connecting the second data block 202 and the data sensing and amplifying unit 204 is short, and the load of the second data line 208 is small. The reduction of the load of the first data line 207 and the second data line 208 is conducive to improving the reading speed of the storage array.

[0065] Moreover, the difference between the number of the first data blocks 201 and the number of the second data blocks 202 is less than a threshold value, the data sensing amplification unit 204 is located in the middle of the storage array along the second direction Y, the difference between the length of the first data line 207 and the length of the second data line 208 is less than a threshold value, and the load of the first data line 207 and the load of the second data line 208 are approximately equal, which can effectively ensure the stability and reliability of the storage array performance.

[0066] Specifically, in some embodiments of the present invention, please continue to refer to Figure 3 The data line is located between the word line driver 203 and the corresponding data block, wherein the data line is one of the first data line 207 and the second data line 208 .

[0067] The data line is located between the word line driver 203 and the corresponding data block, that is, in a projection plane parallel to the horizontal plane, the data line is located between the word line driver 203 and the corresponding data block.

[0068] Specifically, in the projection plane parallel to the horizontal plane, in the first direction X, the first data line 207 is located between the word line driver 203 and the first data block 201 corresponding to the word line driver 203; in the first direction X, the second data line 208 is located between the word line driver 203 and the second data block 202 corresponding to the word line driver 203.

[0069] For details, please refer to Figure 4 The output end of the selector 205 is connected to an input end of the data sensing amplifier 206, and the input end of the selector 205 is connected to a data line one by one, wherein the data line is one of the first data line 207 and the second data line 208.

[0070] Combined with reference Figure 4 In some embodiments, the data sensing amplification unit 204 includes: a selector 205 and a data sensing amplifier 206, the output end of the selector 205 is connected to one input end of the data sensing amplifier 206, the other input end of the data sensing amplifier 206 is suitable for inputting a reference voltage VREF, and the output end OUT of the data sensing amplifier 206 is connected to an auxiliary circuit.

[0071] Specifically, in some embodiments of the present invention, the input terminals of the selector 205 are connected to the data lines in a one-to-one correspondence. For example, the selector 205 is a multiplexer 2 (MUX2 for short), and the selector 205 has two input terminals, one of which is connected to the first data line 207, and the other of which is connected to the second data line 208.

[0072] For example, in some embodiments of the present invention, please refer to Figure 4 and Figure 5The first data line 207 transmits a signal IN0, and the first data line 207 is connected to an input terminal of the selector 205. The second data line 208 transmits a signal IN1, and the second data line 208 is connected to another input terminal of the selector 205. The selector 205 selects one of the signal IN0 and the signal IN1 and outputs it from the output terminal OUT; the output terminal OUT of the selector 205 is connected to an input terminal of the data sensing amplifier 206, and the other input terminal of the data sensing amplifier 206 is suitable for inputting a reference voltage VREF.

[0073] The memory array further comprises: a control unit adapted to send a control signal to control the connection between the input end of the selector 205 and the data line.

[0074] The control unit is adapted to send a control signal so that the selector 205 is connected to the first data line 207 or the second data line 208 .

[0075] Please continue to refer to Figure 3 The storage array further includes: a direction decoder 209, and the direction decoder 209 is located on one side of the storage module 200 along the second direction Y.

[0076] In some embodiments of the present invention, the direction decoder 209 is adapted to extract bit line information from the first data block 201 and the second data block 202. For example, when there are N bit lines in one data block, the direction decoder 209 selects 8 Y-direction selection signals, thereby extracting information of the bit lines corresponding to the 8 Y-direction selection signals.

[0077] Figure 6 is a schematic diagram of the structure of a storage array according to another embodiment of the present invention, Figure 7 yes Figure 6 A schematic diagram of the structure of the data sensing and amplifying unit of the storage array in FIG. Figure 8 yes Figure 7 The timing diagram of the selector of the data sensing amplifier unit in Fig. 9 yes Figure 7 A timing diagram of a data sense amplifier in a data sense amplifier unit.

[0078] The present invention will not repeat the same points as the above embodiments. The difference from the above embodiments is that in some embodiments of the present invention, the storage module further includes: a third data block 303 and a fourth data block 304, the third data block 303 is located in the fourth data block 304 and arranged along the second direction Y, the third data block 303 and the first data block 301 are arranged along the first direction X, and the fourth data block 304 and the second data block 302 are arranged along the first direction X.

[0079] like Figure 6 As shown, along the first direction X, the data sensing and amplifying unit 306 is located between the third data block 303 and the first data block 301 , that is, the third data block 303 is located on a side of the data sensing and amplifying unit 306 away from the first data block 301 along the first direction X.

[0080] like Figure 6 As shown, along the first direction X, the data sensing and amplifying unit 306 is located between the fourth data block 304 and the second data block 302 , that is, the fourth data block 304 is located on a side of the data sensing and amplifying unit 306 away from the second data block 302 along the first direction X.

[0081] Please continue to refer to Figure 6 , the multiple data blocks in the storage module 300 are divided into four categories, namely: the first data block 301, the second data block 302, the third data block 303 and the fourth data block 304, that is, a part of the data blocks are the first data block 201, a part of the data blocks are the second data block 202, a part of the data blocks are the third data block 303, and the remaining number of data blocks are the fourth data block 304. For details, please refer to Figure 6 In some embodiments of the present invention, the storage module 300 has a plurality of the third data blocks 303 , and along the second direction Y, the plurality of the third data blocks 303 are arranged in sequence in a direction away from the fourth data block 304 .

[0082] For details, please refer to Figure 6 In some embodiments of the present invention, the storage module 300 has a plurality of the fourth data blocks 304 , and along the second direction Y, the plurality of the fourth data blocks 304 are arranged in sequence in a direction away from the third data block 303 .

[0083] The difference between the number of the third data blocks 303 arranged along the second direction Y and the number of the fourth data blocks 304 arranged along the second direction Y is less than the threshold. Specifically, in some embodiments of the present invention, the number of the third data blocks 303 arranged along the second direction Y and the number of the fourth data blocks 304 arranged along the second direction Y are equal. For example, please refer to Figure 6 In some embodiments of the present invention, the number of the third data blocks 303 arranged along the second direction Y and the number of the fourth data blocks 304 arranged along the second direction Y are both 2.

[0084] Please continue to refer to Figure 6The storage module 300 also includes: a word line driver 305, the word line driver 305 is located on one side of the corresponding data block along the first direction X, and the data block is one of the first data block 301, the second data block 302, the third data block 303 and the fourth data block 304.

[0085] The word line driver 305 is connected to the corresponding data block. Specifically, the word line driver 305 is connected to the local word line of the corresponding data block. For example: there are M local word lines in one data block, and the word line driver 305 is suitable for connecting to one local word line among the M local word lines, so as to read the information of the bit line connected to the local word line.

[0086] The first direction X is the extension direction of the local word line, so the word line driver 305 and the corresponding data block are adjacently arranged along the first direction X. Figure 6 As shown, all word line drivers 305 in the storage module 300 are located on the same side of the corresponding data block along the first direction X.

[0087] Specifically, in some embodiments of the present invention, the word line driver 305 corresponds to the data block one by one, that is, in the first direction X, each of the word line drivers 305 corresponds to one data block, and each of the word line drivers 305 has one first data block 301 on one side, or one second data block 302 on one side of the word line driver 305, or one third data block 303 on one side of the word line driver 305, or one fourth data block 304 on one side of the word line driver 305.

[0088] Please continue to refer to Figure 6 , the first data block 301, the second data block 302, the third data block 303 and the fourth data block 304 in the storage module 300 share the same data sensing and amplifying unit 306. Specifically, in the storage module 300, along the first direction X, the data sensing and amplifying unit 306 is located between the third data block 303 and the first data block 301.

[0089] For details, please continue to refer to Figure 6 In some embodiments of the present invention, along the second direction Y, the data sensing and amplifying unit 306 is located between the word line driver 305 of the third data block 303 and the word line driver 305 of the fourth data block 304 .

[0090] The first data block 301, the second data block 302, the third data block 303 and the fourth data block 304 share the same data sensing amplification unit 306, which reduces the number of data sensing amplification units 306 and saves the area occupied by setting up the data sensing amplification units 306, which is beneficial to reducing the area of ​​the storage array.

[0091] Furthermore, along the second direction Y, the data sensing and amplifying unit 306 is located in the middle of the memory array, that is, along the second direction Y, the distance from the data sensing and amplifying unit 306 to one side of the memory module 300 is substantially equal to the distance from the data sensing and amplifying unit 306 to the other side of the memory module 300. Therefore, in some embodiments of the present invention, the lengths of the first data line 309, the second data line 310, the third data line 311, and the fourth data line 312 are substantially equal.

[0092] Please continue to refer to Figure 6 The storage module 300 also includes: a third data line 311, the third data line 311 extends along the second direction Y, and the third data line 311 is suitable for realizing the connection between the data sensing amplification unit 306 and the third data block 303; a fourth data line 312, the fourth data line 312 extends along the second direction Y, and the fourth data line 312 is suitable for realizing the connection between the data sensing amplification unit 306 and the fourth data block 304.

[0093] Specifically, one end of the third data line 311 is connected to the data sensing amplifying unit 306, and the other end of the third data line 311 extends along the second direction Y away from the data sensing amplifying unit 306; one end of the fourth data line 312 is connected to the data sensing amplifying unit 306, and the other end of the fourth data line 312 extends along the second direction Y away from the data sensing amplifying unit 306; and the extension direction of the other end of the fourth data line 312 is different from the extension direction of the other end of the third data line 311.

[0094] In addition, if Figure 6 As shown, the first data block 301, the second data block 302, the third data block 303 and the fourth data block 304 share the same data sensing and amplifying unit 306; the data sensing and amplifying unit 306 is located between the word line driver 305 corresponding to the first data block 301 and the word line driver 305 corresponding to the second data block 302, the third data line 311 is located on the side of the third data block 303 away from the word line driver 305 of the third data block 303; the fourth data line 312 is located on the side of the fourth data block 304 away from the word line driver 305 of the fourth data block 304.

[0095] The third data line 311 is located on a side of the third data block 303 away from the word line driver 305 of the third data block 303. That is, in a projection plane parallel to the horizontal plane, the third data line 311 is located on a side of the third data block 303 away from the word line driver 305 of the third data block 303.

[0096] The fourth data line 312 is located on a side of the fourth data block 304 away from the word line driver 305 of the fourth data block 304. That is, in a projection plane parallel to the horizontal plane, the fourth data line 312 is located on a side of the fourth data block 304 away from the word line driver 305 of the fourth data block 304.

[0097] Specifically, the third data block 303 and the first data block 301 are arranged along the first direction X, and the fourth data block 304 and the second data block 302 are arranged along the first direction X; in the projection plane parallel to the horizontal plane, the third data line 311 is located between the third data block 303 and the word line driver 305 of the first data block 301 arranged along the first direction X; in the projection plane parallel to the horizontal plane, the fourth data line 312 is located between the fourth data block 304 and the word line driver 305 of the second data block 302 arranged along the first direction X.

[0098] Please refer to Figure 7 The data sensing amplification unit 306 includes: a selector 307 and a data sensing amplifier 308, wherein the output end of the selector 307 is connected to one input end of the data sensing amplifier 308, the other input end of the data sensing amplifier 308 is suitable for inputting a reference voltage VREF, and the output end OUT of the data sensing amplifier 308 is connected to an auxiliary circuit.

[0099] For details, please refer to Figure 7 The output end of the selector 307 is connected to an input end of the data sensing amplifier 308, and the input end of the selector 307 is connected to a data line one by one, wherein the data line is one of the first data line 309, the second data line 310, the third data line 311 and the fourth data line 312.

[0100] Specifically, in some embodiments of the present invention, the input terminals of the selector 307 are connected to the data lines in a one-to-one correspondence. Figure 7In some of the embodiments shown, the selector 307 is a multiplexer Multiplexer 4 (MUX4 for short), and the selector 307 has four input ends, one input end of the selector 307 is connected to the first data line 309, one input end of the selector 307 is connected to the second data line 310, one input end of the selector 307 is connected to the third data line 311, and one input end of the selector 307 is connected to the fourth data line 312.

[0101] The selector 307 and one data sensing amplifier 308 are provided, so that the number of data sensing amplifiers 308 is reduced, thereby reducing the area of ​​the storage array.

[0102] For example, in some embodiments of the present invention, please refer to Figure 7 and Figure 8 The first data line 309 transmits a signal IN0, the second data line 310 transmits a signal IN1, the third data line 311 transmits a signal IN2, and the fourth data line 312 transmits a signal IN3; the first data line 309, the second data line 310, the third data line 311, and the fourth data line 312 are connected to the four input terminals of the selector 307 in a one-to-one correspondence, and the selector 205 selects one from the signal IN0, the signal IN1, the signal IN2, and the signal IN3 to output from the output terminal OUT; the output terminal OUT of the selector 307 is connected to an input terminal of the data sensing amplifier 308, and the other input terminal of the data sensing amplifier 308 is suitable for inputting a reference voltage VREF.

[0103] The memory array further comprises: a control unit adapted to send a control signal to control the connection between the input end of the selector 307 and the data line.

[0104] The control unit is adapted to send a control signal so that the selector 307 is connected to the first data line 309 , the second data line 310 , the third data line 311 or the fourth data line 312 .

[0105] Please refer to Fig. 9 , Fig. 93 is a structural diagram of the data sensing amplifier 308. IN indicates a signal input to one input terminal of the data sensing amplifier 308, and the IN terminal is suitable for connecting to the output terminal of the selector 307; VREF indicates a reference voltage input to another input terminal of the data sensing amplifier 308; EN indicates a signal input to the enable terminal of the data sensing amplifier 308; BIAS indicates a signal input to the bias terminal of the data sensing amplifier 308; and OUT indicates a signal output from the output terminal of the data sensing amplifier 308.

[0106] Correspondingly, an embodiment of the present invention further provides a storage device, which includes the storage array as described above.

[0107] The storage device includes the storage array as described above, thereby reducing the load of the data line of the storage device, thereby reducing the access delay of the storage device, which is beneficial to reducing the energy consumption of the storage device and improving the reading speed of the storage device; and the storage device includes the storage array as described above, so that the area of ​​the storage device is reduced.

[0108] In summary, in the storage array of the technical solution of the present invention, the data sensing amplification unit is located between the first data block and the second data block, which reduces the distance between the data sensing amplification unit and the first data block, and the distance between the data sensing amplification unit and the second data block, thereby reducing the length of the first data line connecting the first data block and the data sensing amplification unit, and the length of the second data line connecting the second data block and the data sensing amplification unit, thereby reducing the load of the first data line and the second data line, and reducing the access delay of the first data line and the second data line, which is beneficial to reducing energy consumption and improving the reading speed; and the selector is set to realize the multiplexing of one data sensing amplifier, reducing the number of data sensing amplifiers, thereby reducing the area of ​​the storage array; in addition, the storage device includes the storage array as described above, reducing the load of the data line of the storage device, thereby reducing the access delay of the storage device, which is beneficial to reducing the energy consumption of the storage device, improving the reading speed of the storage device, and reducing the area of ​​the storage device.

[0109] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A storage array, characterized in that: include: A plurality of storage modules, wherein the plurality of storage modules are arranged along a first direction; The storage module comprises: A first data block and a second data block, wherein the second data block and the first data block are arranged along a second direction, wherein the second direction intersects with the first direction; a data sensing and amplifying unit, wherein the data sensing and amplifying unit is located between the first data block and the second data block along the second direction; A first data line, the first data line extending along a second direction, the first data line being suitable for realizing a connection between the data sensing and amplifying unit and the first data block; A second data line, the second data line extends along a second direction, and the second data line is suitable for realizing the connection between the data sensing and amplifying unit and the second data block.

2. The storage array according to claim 1, wherein: The storage module has a plurality of the first data blocks, and along the second direction, the plurality of the first data blocks are arranged in sequence in a direction away from the second data block; The storage module has a plurality of the second data blocks, and along the second direction, the plurality of the second data blocks are arranged in sequence in a direction away from the first data block.

3. The storage array according to claim 2, wherein: A difference between the number of the first data blocks arranged along the second direction and the number of the second data blocks arranged along the second direction is smaller than a threshold.

4. The storage array according to any one of claims 1 to 3, characterized in that: A difference between the length of the first data line and the length of the second data line is smaller than a threshold.

5. The storage array according to claim 1, wherein: The storage module also includes: A word line driver, the word line driver being located at one side of a corresponding data block along a first direction, the data block being one of the first data block and the second data block; The data sensing and amplifying unit is located between the word line driver of the first data block and the word line driver of the second data block.

6. The storage array according to claim 5, characterized in that: The data line is located between the word line driver and the corresponding data block, wherein the data line is one of the first data line and the second data line.

7. The storage array according to claim 6, wherein: The storage module further includes: a third data block and a fourth data block, the third data block is located at the fourth data block and arranged along the second direction, the third data block and the first data block are arranged along the first direction, and the fourth data block and the second data block are arranged along the first direction; Along the first direction, the data sensing and amplifying unit is located between the third data block and the first data block; The storage array further comprises: A third data line, the third data line extending along the second direction, the third data line being suitable for realizing the connection between the data sensing and amplifying unit and the third data block; A fourth data line, the fourth data line extends along the second direction, and the fourth data line is suitable for realizing the connection between the data sensing and amplifying unit and the fourth data block.

8. The storage array according to claim 7, wherein: The third data line is located at a side of the third data block away from a word line driver of the third data block; The fourth data line is located at a side of the fourth data block away from a word line driver of the fourth data block.

9. The storage array according to claim 1, wherein: Also includes: A direction decoder is located at one side of the storage module along the second direction.

10. The storage array according to claim 1, wherein: The data sensing and amplifying unit includes: a selector and a data sensing amplifier, wherein the output end of the selector is connected to an input end of the data sensing amplifier, and the input end of the selector is connected to a data line in a one-to-one correspondence, wherein the data line is one of the first data line and the second data line.

11. The storage array according to claim 10, wherein: Also includes: A control unit is adapted to send a control signal to control the connection between the input terminal of the selector and the data line.

12. The storage array according to claim 7, wherein: The data sensing amplification unit includes: a selector and a data sensing amplifier, the output end of the selector is connected to an input end of the data sensing amplifier, the input end of the selector is connected to a data line one-to-one, wherein the data line is one of the first data line, the second data line, the third data line and the fourth data line.

13. The storage array according to claim 12, wherein: Also includes: A control unit is adapted to send a control signal to control the connection between the input terminal of the selector and the data line.

14. The storage array according to claim 1, wherein: The output line of the data sensing and amplifying unit is connected to the auxiliary circuit along a first direction.

15. A storage device, characterized in that: include: A storage array as claimed in any one of claims 1 to 14.

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