Memory read sequence control circuit without address decoding

Abstract

A memory read-out sequence control circuit without address decoding comprises m circuit units, each circuit unit generates two adjacent sequence control signals which are effective in sequence, and 2m column-level sequence control signals which are effective in sequence are generated in total so as to realize sequential read-out of 2m column-level memory units in each row. According to the invention, through the sequence generation circuit formed by the latch and the logic gate circuit, all control signals required by the read sequence of the memory can be output only by reading the clock signal and the reset signal, no address line signal input and decoding circuit is needed, and the control signals are triggered at the rising edge and the falling edge of the input read clock, so that the read sequence of the memory is more stable. The reading speed is doubled, an input interface is greatly simplified, and the area and power consumption of a chip are correspondingly reduced.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuits, in particular to a memory readout sequence control circuit suitable for selecting column-level and row-level sequences of a memory array without requiring address decoding. Background Art

[0002] At present, memory is increasingly used in various chips, and the data capacity required to be stored is getting larger and larger, and the speed of reading data is getting faster and faster. As the storage capacity increases, the size of the memory array increases accordingly, thus limiting the improvement of the memory data reading speed.

[0003] The writing and reading of the memory array requires separate operations on each memory cell. The current common technology is to use an address decoding circuit to generate a sequence control signal to achieve sequential access to each memory cell. As the size of the memory array increases, the row / column address input signal and the size of the decoding circuit also increase proportionally, which not only increases the number of interfaces, but also puts higher requirements on the external address generation circuit, which will undoubtedly increase the area and power consumption of the entire chip. In addition, due to the increase in the number and length of internal address lines and the greater load on the lines, the input delay of the address signal increases, making the decoder output control sequence pulse signal narrower, resulting in a shortened actual read time of a single memory cell, and even bit errors, which becomes a bottleneck that limits the read accuracy and read speed of the memory array. Summary of the invention

[0004] In view of the area, speed and power consumption problems existing in the above-mentioned large-scale memory read sequence control method, the present invention proposes a memory read sequence control circuit that does not require address decoding. It only needs to read the clock signal and the reset signal to generate all the control signals required for the memory read sequence, and does not require any address line signal input and decoding circuit. The control signal is triggered at both the rising edge and the falling edge of the input read clock, which doubles the read speed, greatly simplifies the input interface and correspondingly reduces the chip area and power consumption.

[0005] The present invention is achieved through the following technical solutions:

[0006] The present invention relates to a memory readout sequence control circuit without address decoding, comprising m identical circuit units, each circuit unit generating two adjacent sequentially valid sequence control signals, i.e., the valid pulse widths of the signals are sequentially arranged in an adjacent and non-overlapping order, and a total of 2m sequentially valid sequence control signals are generated, i.e., the signal pulse widths when valid do not overlap each other and are sequentially arranged in a corresponding physical address order, so as to realize sequential access to a storage array of 2m column units.

[0007] The circuit unit comprises: a pair of identical clock-triggered latches and a pair of identical logic gate circuits respectively connected thereto for generating sequence control signals, wherein: the input terminal D of the first latch is connected to the output terminal Q of the second latch of the circuit unit at the previous level, the output terminal Q of the first latch of the circuit unit at this level is connected to the D terminal of the second latch of the circuit unit at this level; the Q terminal of the second latch of the circuit unit at this level is connected to the D terminal of the first latch of the circuit unit at the next level; the pair of latches are connected to the same reset signal (rst), and the positive and negative clock control terminals of the pair of latches are respectively connected in opposite directions and connected to a pair of clock signals with opposite phases.

[0008] The pair of logic gate circuits of the circuit unit respectively generate a first sequence control signal through an AND gate according to the output signal of the second latch Q end of the circuit unit at the previous level and the output signal of the second latch Q end of the circuit unit at this level after being inverted; ② A second sequence control signal is generated after the Q-end output signal of the first latch of the circuit unit at this level and the Q-end output signal of the second latch are inverted and passed through an AND gate.

[0009] The present invention relates to another memory read sequence control circuit that does not require address decoding, comprising m identical circuit units, wherein the input and output ends of every two adjacent circuit units are cross-connected to each other, generating four adjacent sequentially valid sequence control signals, and generating a total of 2m sequentially valid column sequence control signals, for realizing sequential access to a storage array of 2m column units.

[0010] The adjacent first and second circuit units each include: a pair of identical clock-triggered latches and a pair of identical logic gate circuits connected thereto for generating a sequence control signal, wherein: the input terminal D of the first latch is connected to the output terminal Q of the second latch of the previous level circuit unit, the output terminal Q of the first latch of the current level circuit unit is connected to the D terminal of the second latch of the current level circuit unit; the Q terminal of the second latch of the current level circuit unit is connected to the D terminal of the first latch of the next level circuit unit; a pair of latches are connected to the same reset signal, and the clock input terminals of the pair of latches are respectively connected to the output terminals of a pair of logic gate circuits.

[0011] The pair of logic gate circuits of the first circuit unit respectively: ① generate a first sequence control signal and its inverted signal through an AND gate based on the Q-end output signal of the second latch of the previous circuit unit, the input clock signal, and the output signal of the Q-end of the second latch of the first circuit unit, which are inverted; ② generate a second control signal and its inverted signal through an AND gate based on the Q-end output signal of the first latch of the first circuit unit, the inverted signal of the input clock, and the output signal of the Q-end of the first latch of the second circuit unit, which are inverted.

[0012] The pair of logic gate circuits of the second circuit unit generates a third control signal and its inverted signal and a fourth control signal and its inverted signal according to the Q-end output signal of the second latch of the first circuit unit, the input clock signal, the inverted clock signal, the Q-end output signals of the first and second latches of the second circuit unit, and the Q-end output signal of the first latch of the next-level circuit unit.

[0013] All circuit units of the memory readout sequence control circuit are respectively connected to the same clock signal, the inverted clock signal and the reset signal.

[0014] The first trigger input terminal D of the first circuit unit in the memory read sequence control circuit can directly input '1'. Technical Effects

[0015] The present invention adopts a readout clock signal and a reset / enable signal, and realizes sequential and effective sequence control signal output through a logic gate circuit of latch units connected front and back and the input and output of adjacent circuit units. The prior art usually adopts a decoding circuit to realize the readout sequence control of the storage array, which requires a number of address line signals and their reverse signal inputs to realize the sequential readout of the storage units, and the number of address lines and the scale of the decoding circuit increase with the increase of the memory array. The present invention can realize the same function as mentioned above without any address line signal input, greatly simplifies the number of interfaces and circuit scale of the memory readout sequence control circuit, not only saves the external high-precision address generation circuit required for large-scale memory, but also greatly reduces the number of transistors of the circuit unit, avoiding the delay bottleneck problem caused by the increase of address lines and their loads.

[0016] In addition, the prior art is usually single-edge triggered, that is, only one valid sequence control signal is generated in one read clock cycle, while the present invention is double-edge triggered, that is, two valid sequence control signals are generated at the rising edge and falling edge of the clock in one read clock cycle respectively. Therefore, at the same input clock rate, the read speed is doubled, effectively ensuring the reliability of high-speed access to the memory, which is beneficial to reducing chip area and power consumption, and is more suitable for high-speed read requirements of large-scale memory arrays. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a schematic diagram of the memory circuit structure;

[0018] Figure 2 It is the timing diagram of the sequence control signal of the address decoding circuit;

[0019] Figure 3 This is a schematic diagram of the circuit structure of Example 1;

[0020] Figure 4 This is a simulation timing diagram corresponding to Example 1;

[0021] Figure 5 This is a schematic diagram of the circuit structure of Example 2;

[0022] Figure 6 This is a simulation timing diagram corresponding to Example 2. DETAILED DESCRIPTION

[0023] The present invention is a readout sequence control circuit that can provide row / column unit selection signals for a memory without address line input and only requires clock and reset signals. Figure 1 The memory circuit structure shown in the figure has n×2m memory cells 101 for the memory array 100, wherein: the read sequence control circuit 102 generates all column sequence control signals WL required for reading the memory array through the clock signal and the reset signal. <0> ~WL<2m-1>103 and output to the memory array 100; in the read phase, when the column control signal WL <0> When WL<2m-1>103 is effective in sequence, each data bus Data of the n-row storage line column <0> ~Data <n-1>104 will output WL in parallel <0> ~WL<2m-1> corresponds to the read data of the control storage unit.

[0024] like Figure 2 As shown, the column control signal WL is generated by the existing address decoding circuit. <0> ~WL<2m-1>103 and the timing diagram of the read clock cycle 200. One read clock cycle corresponds to one address code, and each sequence control signal is only valid when triggered by the rising edge of the read clock ck, that is, one sequence control signal is generated in one read clock cycle. Under the sequential triggering of the rising edge of the clock ck, the column control signal WL <0> ~WL<2m-1> 103 are validated sequentially to implement sequential reading of each column of storage cells.

[0025] The present invention relates to a readout sequence control circuit 102 for generating 2m sequence control signals 103, comprising m identical circuit units, using edge triggering, latching and logic operations of the clock, triggering the generation of effective sequence control signals at both the rising and falling edges of the input readout clock, and also generating sequentially effective column control signals WL that are the same as the timing diagram 200. <0> ~WL<2m-1>103, omitting a large number of address line inputs, doubling the readout sequence signal rate under the same input clock, with a simple circuit structure that is easy to implement, reducing the area and power consumption of the memory and increasing the readout rate. Example 1

[0026] This embodiment relates to a memory read sequence control circuit that does not require address decoding, including m such as Figure 3 The circuit unit 300 shown in the figure, each circuit unit 300 generates two adjacent and effective control signals in sequence, which includes: a pair of latches 301, 302 and a pair of logic gate circuits 303, 304 for generating control signals, wherein: the input terminal D of the first latch 301 is connected to the output terminal Q of the second latch of the previous level circuit unit to output the signal a, the Q terminal of the first latch 301 is connected to the input terminal D of the second latch 302; the Q terminal of the second latch 302 is connected to the input terminal D of the first latch of the next level circuit unit; the reset terminals of the pair of latches 301, 302 are connected to the same reset signal rst, the positive and negative input terminals of the clock signals of the pair of latches 301, 302 are respectively connected in opposite directions and connected to a pair of clock signals with opposite phases; the output signal a of the second latch of the previous level unit and the output signal b of the first latch 301 are inverted and the signal generates the control signal WL after passing through the AND gate. The output signal b of the first latch 301 and the output signal c of the second latch 302 are inverted and then pass through the AND gate to generate the control signal WL<i+1> .

[0027] When the reset signal rst = 0, all latches are reset to 0, and all output sequence control signals WL , WL<i+1> ...is 0, memory array read is disabled.

[0028] The readout sequence control circuit of the traditional 12-bit decoder structure requires a 12-bit address line signal and its inverted signal input, and can generate up to 2048 sequence control signals to complete the sequence access of 2048 columns of storage units. Using the traditional CMOS gate circuit, a single decoding unit needs 50 transistors to generate a sequence control signal. 12 address lines and their inverted signals, a total of 24 address lines, must run through the entire decoder sequence control circuit, and the delay between address lines must be small enough to ensure decoding accuracy and reading speed. This embodiment requires 1024 of the circuit units 300 to generate the same 2048 sequence control signals. One circuit unit 300 only needs an average of 18 transistors to generate one sequence control signal. Compared with the traditional address decoding circuit structure, the number of transistors is reduced by 64%, and there is no need to consider the limitation of readout speed caused by more delays between address lines.

[0029] like Figure 4 As shown, it is a timing diagram 400 corresponding to the circuit unit 300. If this circuit unit is the first read sequence control unit, the input signal a of the input terminal D of the first latch 301 of the first circuit unit can be directly connected to '1'. After the rst signal is '1', the signal a is sampled by the first latch 301 at the rising edge of the clock signal ck to obtain the output signal b of the first latch 301. The signal b is sampled by the second latch 302 at the falling edge of the clock signal ck to obtain the output signal c of the second latch 302. The signal after the inversion of the signal a and the signal b is passed through the AND gate circuit to obtain the control signal WL ; The signal after signal b and signal c are inverted passes through the AND gate circuit to obtain the control signal WL<i+1> , that is, the rising edge and falling edge of the clock signal ck respectively obtain the adjacent and sequentially effective control signals WL , WL<i+1> Similarly, each circuit unit 300 can generate two control signals, and finally the control signal WL <0> ~WL<2m-1> are valid in sequence. Example 2

[0030] This embodiment relates to a memory read sequence control circuit without address decoding, including m identical circuit units, the input and output ends of every two adjacent circuit units are cross-connected to generate four adjacent sequentially valid sequence control signals, and a total of 2m sequentially valid sequence signals are generated. Each circuit unit also includes a pair of clock-triggered latches and a pair of logic gate circuits, and the output sequence control signal WL of each circuit unit is and its inverted signal WL_b The clock input terminal clk and the inverting terminal clkb of the corresponding latch are respectively connected, so that each circuit unit works only once when the current sequence control signal is valid, which can further reduce power consumption.

[0031] like Figure 5 As shown, it is a connection example 500 of two adjacent circuit units in this embodiment. Two adjacent circuit units 501 and 502 respectively obtain two adjacent and sequentially valid control signals at the rising edge and falling edge of the clock signal ck, wherein the first circuit unit 501 includes: a pair of latches 503 and 504 and a pair of logic gate circuits 505 and 506; the second circuit unit 502 includes: a pair of latches 507 and 508 and a pair of logic gate circuits 509 and 510.

[0032] The D terminal of the first latch 503 of the first circuit unit 501 receives the output signal a of the second latch of the previous circuit unit, the Q terminal of the first latch 503 is connected to the D terminal of the second latch 504, and the Q terminal of the second latch 504 is respectively connected to the input terminal of the first logic gate circuit 505 of the first circuit unit 501 and the D terminal of the first latch 507 of the second circuit unit 502. The clock signal input terminals clk and clkb of the two latches 503 and 504 of the first circuit unit 501 respectively receive the first control signal WL output by the first logic gate circuit 505. and its inverted signal WL_b and the second control signal WL output by the second logic gate circuit 506<i+1> and its inverted signal WL_b<i+1> .

[0033] The first logic gate circuit 505 of the first circuit unit 501 generates a first control signal WL through an AND gate according to the output signal a of the second latch of the previous level unit, the input clock signal ck and the output signal of the second latch 504 of this unit after being inverted. and its inverted signal WL_b The second logic gate circuit 506 generates a second control signal WL through an AND gate according to the inverted signal ckb of the input clock, the output signal b of the first latch 503 of the circuit unit, and the output signal d of the first latch 507 of the second circuit unit after inversion.<i+1> and its inverted signal WL_b<i+1> .

[0034] The second circuit unit 502 generates a third control signal WL through the first logic gate circuit 509 and the second logic gate circuit 510 of the second circuit unit 502 according to the output signal c of the second latch 504 of the first circuit unit 501, the input clock signal ck, the reverse clock signal ckb, the output signal d of the first latch 507 in the second circuit unit 502, the output signal e of the second latch 508, and the output signal g of the first latch of the next level circuit unit.<i+2> and its inverted signal WL_b<i+2> and the fourth control signal WL<i+3> and its inverted signal WL_b<i+3> .

[0035] The reset terminals of the latches 503, 504, 507, 508 and the clock positive and negative input terminals of the logic gate circuits 505, 506, 509, 510 of all the above circuit units are respectively connected to the same reset signal rst and the positive and negative clock signals, and when the reset signal rst = 0, all latches are reset to 0, and all output sequence control signals WL , WL<i+1> , WL<i+2> , WL<i+3> ...is 0, memory array read is disabled.

[0036] In this embodiment, one circuit unit 501 or 502 only needs 20 devices on average to generate one control signal, which reduces the number of transistors by 60% compared with the traditional structure.

[0037] like Figure 5 As shown, Figure 4 The timing diagram corresponding to two adjacent circuit units 500. The clock signal ck and its inverted clock signal ckb are respectively connected to the input terminals ck and ckb of a pair of logic gate circuits 505 and 506 of the first circuit unit. The signal a is sampled by the first latch 503 at the rising edge of the clock signal ck to obtain the output signal b. The signal b is sampled by the second latch 504 at the falling edge of ck to obtain the output signal c. The clock signal ck, the signal a and the inverted signal c are passed through the AND gate circuit to obtain the control signal WL. and WL_b The inverted clock signal ckb, the signal b and the output signal d of the first latch 507 of the second circuit unit are inverted and then pass through the AND gate circuit to obtain the control signal WL<i+1> and WL_b<i+1> ,WL and WL_b , WL<i+1> and WL_b<i+1> The clock positive and negative input terminals of the first latch 503 and the second latch 504 of the first circuit unit are connected respectively. Similarly, for the second circuit unit 502, the third control signal WL is generated by the output signal c of the second latch 504 of the first circuit unit, the input clock signal ck, the reverse clock signal ckb, the output signal d of the first latch 507 of the second circuit unit, the output signal e of the second latch 508, and the output signal g of the first latch of the next circuit unit.<i+2> and its inverted signal WL_b<i+2> and the fourth control signal WL<i+3> and its inverted signal WL_b<i+3> .

[0038] When the circuit unit 501 is the first circuit unit of the m circuit units of the read sequence control circuit 103, the input signal a can be directly connected to '1'. After the rst signal is '1', the first circuit unit 501 and the second circuit unit 502 respectively generate the control signal WL <0> , WL <1> , WL <2> , WL <3> and its inverted signal WL_b <0> 、WL_b <1> 、WL_b <2> 、WL_b <3> .

[0039] Similarly, each circuit unit can generate two adjacent and valid control signals in sequence at the rising edge and falling edge of the input clock within one cycle, ultimately making the sequence control signal WL <0> ~WL<2m-1> are valid in sequence.

[0040] Compared with the prior art, the memory read sequence control circuit not only saves a large number of address line input interfaces required for large-scale memory arrays, but also only needs to read out clock signals and reset / enable signals to generate all control signals required for accessing and reading the memory array, greatly simplifies the number of memory control interfaces, reduces the input signal requirements for external circuits, and effectively avoids the problem of read errors caused by the narrowing of the effective pulse width of the control sequence output by the address decoding due to the increase in input address lines and load caused by the increase in the memory array. At the same input clock rate, the speed of the output sequence control signal is doubled, and the circuit scale of the present invention saves more than 60% of the number of transistors compared with the prior art. Therefore, the present invention can significantly reduce the area and power consumption of the memory read sequence control circuit, and effectively ensure and improve the access read accuracy and read speed of the memory.

[0041] The above-mentioned specific implementation can be partially adjusted in different ways by those skilled in the art without departing from the principle and purpose of the present invention. The protection scope of the present invention shall be based on the claims and shall not be limited by the above-mentioned specific implementation. Each implementation scheme within its scope shall be subject to the constraints of the present invention.

Claims

1. A memory read sequence control circuit capable of realizing column unit sequence selection of a memory array without address decoding, characterized in that: include: m identical circuit units, each circuit unit generates two adjacent sequentially valid sequence control signals, and a total of 2m sequentially valid sequence control signals are generated to realize sequential reading of 2m storage units.

2. The memory read sequence control circuit according to claim 1, characterized in that: The circuit unit comprises: a pair of clock-triggered latches and a pair of logic gate circuits respectively connected thereto for generating sequence control signals, wherein: the input terminal D of the first latch is connected to the output terminal Q of the second latch of the previous level circuit unit, the output terminal Q of the first latch is connected to the D of the second latch; the Q of the second latch is connected to the D of the first latch of the next level circuit unit; the pair of latches are connected to the same reset signal, and the positive and negative clock control terminals of the pair of latches are respectively connected in opposite directions and connected to a pair of clock signals with opposite phases.

3. The memory read sequence control circuit according to claim 2, characterized in that: The pair of logic gate circuits of the circuit unit respectively: ① generate a first sequence control signal according to the output signal of the second latch Q end of the circuit unit at the previous level and the output signal of the second latch Q end of the circuit unit at this level after being inverted through the AND gate; ② generate a second sequence control signal according to the output signal of the first latch Q end of the circuit unit at this level and the output signal of the second latch Q end after being inverted through the AND gate.

4. A memory read sequence control circuit capable of realizing column unit sequence selection of a memory array without address decoding, characterized in that it comprises: m identical circuit units, the input and output ends of every two adjacent first and second circuit units are cross-connected to generate four adjacent sequentially valid sequence control signals, and a total of 2m sequentially valid sequence control signals are generated to realize sequential reading of 2m storage units.

5. The memory read sequence control circuit according to claim 4, characterized in that: The first and second circuit units respectively include: a pair of clock-triggered latches and a pair of logic gate circuits respectively connected thereto for generating sequence control signals, wherein: the input terminal D of the first latch is connected to the output terminal Q of the second latch of the previous circuit unit, the output terminal Q of the first latch is connected to the input terminal D of the second latch, the Q terminals of the first and second latches are connected to the input terminals of two groups of logic gate circuits, and the positive and negative clock input terminals of a pair of latches are respectively connected to the two sequence control signals and their inverted signals output by a pair of logic gate circuits.

6. The memory read sequence control circuit according to claim 5, characterized in that: The pair of logic gate circuits of the first circuit unit respectively: ① generate a first sequence control signal and its inverted signal through an AND gate based on the Q-end output signal of the second latch of the previous level unit, the input clock signal and the output end Q-end output signal of the second latch of the first circuit unit; ② generate a second control signal and its inverted signal through an AND gate based on the Q-end output signal of the first latch of the first circuit unit, the inverted signal of the input clock and the output end Q-end output signal of the first latch of the second circuit unit.

7. The memory read sequence control circuit according to claim 6, characterized in that: The pair of logic gate circuits of the second circuit unit respectively generate a third control signal and its inverse signal and a fourth control signal and its inverse signal according to the Q-end output signal of the second latch of the first circuit unit, the input clock signal, the reverse clock signal, the Q-end output signals of the first and second latches of the second circuit unit, and the Q-end output signal of the first latch of the next-level circuit unit.

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