Three-dimensional memory device and manufacturing method of contact hole of three-dimensional memory device

Abstract

The invention is suitable for the technical field of semiconductors, and provides a three-dimensional memory device and a manufacturing method of a contact hole of the three-dimensional memory device. The manufacturing method of the contact hole of the three-dimensional memory device comprises the steps that a stacking structure of the contact hole to be etched is provided, the stacking structure comprises multiple landing layers, and step structures are formed at the ends of the multiple landing layers; according to the preset depth of the contact hole to be etched, the aperture of the contact hole corresponding to the landing layer is determined, and the aperture of the contact hole is linearly and positively correlated with the depth of the contact hole; manufacturing a mask on the stacked structure according to the aperture; and under a preset process condition, the area, exposed from the mask, of the stacking structure is etched, a plurality of contact holes are formed at the same time, and the contact holes are communicated with the landing layer at the step structure. Therefore, a plurality of contact holes with different depths can be manufactured at the same time, and more contact holes can be manufactured by using one mask, so that the number of masks is reduced, the cost is reduced, the efficiency is improved, and the adverse effect on a front layer structure can be reduced.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular, relates to a three-dimensional storage device and a method for manufacturing a contact hole thereof. Background Art

[0002] A three-dimensional memory device increases the storage density per unit area by stacking multiple memory device layers vertically on a substrate. The memory device layers include horizontal signal lines connected to the memory devices. The signal lines of each memory device layer are usually led out using vertical contact holes.

[0003] As the number of stacked memory cell layers increases, the signal line layer in the bottom area requires a greater contact hole depth than the signal line layer in the top area. When the etching conditions of each contact hole are the same, the etching rate is basically the same. When there are many signal line layers, if all contact holes are etched at once, when the contact hole etching reaches the bottom signal line layer, the top signal line layer will inevitably be over-etched or even etched through, or when the contact hole etching reaches the top signal line layer, the contact hole corresponding to the bottom signal line layer has not been etched, which affects the contact between the conductor and the signal line filled in the contact hole, reducing the yield. In the related art, multiple masks are usually used to etch contact holes of different depths in sections. However, this is costly and easily damages the front layer structure of the three-dimensional storage device.

[0004] Based on this, how to make contact holes of three-dimensional memory devices to reduce costs and improve yield has become an urgent problem to be solved. Summary of the invention

[0005] The present application provides a three-dimensional memory device and a method for manufacturing a contact hole thereof, aiming to solve the problem of how to manufacture the contact holes of the three-dimensional memory device to reduce the cost and improve the yield.

[0006] The present application provides a method for manufacturing a contact hole of a three-dimensional memory device, comprising:

[0007] Providing a stacking structure for etching contact holes, the stacking structure comprising a plurality of landing layers, wherein ends of the plurality of landing layers form a step structure;

[0008] According to the preset depth of the contact hole to be etched, determining the aperture of the contact hole corresponding to the landing layer, wherein the aperture of the contact hole is linearly positively correlated with the depth of the contact hole;

[0009] Making a mask on the stacked structure according to the aperture;

[0010] Under preset process conditions, the area of ​​the stacked structure exposed from the mask is etched to form a plurality of contact holes, wherein the contact holes are connected to the landing layer at the step structure.

[0011] Optionally, the manufacturing method comprises:

[0012] In the case where the landing layer is a sacrificial layer, replacing the sacrificial layer with a conductive layer;

[0013] In the case where the landing layer is a non-sacrificial layer, the non-sacrificial layer serves as a conductive layer.

[0014] Optionally, determining the aperture of the contact hole corresponding to the landing layer according to a preset depth of the contact hole to be etched includes:

[0015] Get the first constant and the second constant;

[0016] The aperture is determined according to the first constant, the second constant, the depth and the following first formula:

[0017] CD=d1*h+β1;

[0018] Wherein, CD is the aperture, h is the depth, d1 is the first constant, and β1 is the second constant.

[0019] Optionally, before the step of determining the aperture according to the first constant, the second constant, the depth and the following first formula, the manufacturing method includes:

[0020] Providing a first test structure having a first test mask, wherein the first test mask is formed with a plurality of first test holes having different apertures;

[0021] Under a first test process condition, etching the area of ​​the first test structure exposed from the first test hole to form a plurality of first test contact holes, wherein the first test contact holes include first reference test contact holes, and the first test process condition includes a first etching time;

[0022] When the current depth of the first reference test contact hole corresponding to the first etching duration is equal to the preset depth of the first reference test contact hole, determining a first test value and a second test value according to a plurality of the first test contact holes;

[0023] determining whether the first test value and the second test value meet the contact hole requirement of the stack structure;

[0024] In the case that the first test value and the second test value meet the contact hole requirement, the first test value and the second test value are respectively determined as the first constant and the second constant, and the corresponding first test process condition is used as the preset process condition;

[0025] When the first test value and the second test value do not meet the contact hole requirement, the first test process condition is adjusted, and the step of etching the area of ​​the first test structure exposed from the first test hole under the first test process condition to form a plurality of first test contact holes is performed.

[0026] Optionally, determining a first test value and a second test value according to the plurality of first test contact holes comprises:

[0027] Measuring the apertures of the plurality of first test contact holes to obtain a first test aperture;

[0028] Measuring the depths of the plurality of first test contact holes to obtain a first test hole depth;

[0029] The first test value and the second test value are determined according to a plurality of corresponding groups of the first test hole diameters and the first test hole depths.

[0030] Optionally, the manufacturing method comprises:

[0031] When the depth intervals of the landing surfaces of any two adjacent landing layers are uniform, the apertures of the contact holes corresponding to the landing layers are determined according to the following second formula:

[0032] CD=d2×(Total_WL_No.-current_WL_No.)+β2;

[0033] Among them, CD is the aperture, Total_WL_No. is the total number of layers of the landing layer, current_WL_No. is the number of layers of the landing layer corresponding to the contact hole along the stacking direction of the three-dimensional storage device, d2 is the third constant, and β2 is the fourth constant.

[0034] Optionally, before the step of determining the aperture of the contact hole corresponding to the landing layer according to the following second formula when the depth spacing of the landing surfaces of any two adjacent landing layers is uniform, the manufacturing method includes:

[0035] When the difference rate of the depth spacing between any two adjacent landing surfaces is less than or equal to 10%, it is determined that the depth spacing of the landing surfaces is uniform.

[0036] Optionally, before the step of determining the aperture of the contact hole corresponding to the landing layer according to the following second formula when the depth spacing of the landing surfaces of any two adjacent landing layers is uniform, the manufacturing method includes:

[0037] Providing a second test structure provided with a second test mask, wherein the second test mask is formed with a plurality of second test holes having different apertures;

[0038] Under a second test process condition, etching the area of ​​the second test structure exposed from the second test hole to form a plurality of second test contact holes, wherein the second test contact holes include second reference test contact holes, and the second test process condition includes a second etching time;

[0039] When the current depth of the second benchmark test contact hole corresponding to the second etching time is equal to the preset depth of the second benchmark test contact hole, determining a third test value according to the depth spacing between the plurality of second test contact holes and the landing surface;

[0040] determining whether the third test value meets the contact hole requirement of the stack structure;

[0041] In the case where the third test value meets the contact hole requirement, determining the third test value as the third constant, and using the corresponding second test process condition as the preset process condition;

[0042] When the third test value does not meet the contact hole requirement, the second test process condition is adjusted, and the step of etching the second test structure in the area exposed from the second test hole under the second test process condition to form a plurality of second test contact holes is performed.

[0043] Optionally, determining a third test value according to a depth spacing between a plurality of the second test contact holes and the landing surface comprises:

[0044] Measuring the apertures of the plurality of second test contact holes to obtain second test apertures;

[0045] Measuring the depths of the plurality of second test contact holes to obtain a second test hole depth;

[0046] Determine an intermediate value according to a plurality of corresponding groups of the second test hole diameters and the second test hole depths;

[0047] The third test value is determined according to the intermediate value and the depth interval of the landing surface.

[0048] Optionally, before the step of determining the aperture of the contact hole corresponding to the landing layer according to a preset depth of the contact hole to be etched, the manufacturing method includes:

[0049] Acquiring contact hole requirements of the stacked structure, wherein the contact hole requirements include an aperture value of the contact hole with the smallest aperture;

[0050] The aperture value is determined as the fourth constant.

[0051] Optionally, the contact hole includes a dense contact hole and a non-dense contact hole, and making a mask on the stacked structure according to the hole diameter includes:

[0052] manufacturing a mask material layer on the stacked structure;

[0053] Making a first opening, a second opening and a third opening in the mask material layer according to the aperture, wherein the first opening, the second opening and the third opening correspond to the dense contact hole, the non-dense contact hole and the virtual hole of the three-dimensional memory device respectively;

[0054] Etching the area of ​​the stacked structure exposed from the mask to form the contact hole under preset process conditions includes:

[0055] Under the preset process conditions, the areas of the stacked structure exposed from the first opening, the second opening and the third opening are etched to form the dense contact hole, the non-dense contact hole and the virtual hole, and the virtual hole is located at the periphery of the non-dense contact hole.

[0056] The three-dimensional storage device provided in the present application comprises a plurality of contact holes of different depths, wherein the contact holes are manufactured by any of the above-mentioned contact hole manufacturing methods.

[0057] The three-dimensional storage device provided in the present application includes multiple conductive layers and multiple contact holes with different depths. The ends of the multiple conductive layers form a step structure. The contact holes are connected to the conductive layers at the step structure. The aperture of the contact holes is linearly positively correlated with the depth of the contact holes.

[0058] Optionally, the diameter of the contact hole and the depth of the contact hole satisfy the following formula:

[0059] CD=d1*h+β1;

[0060] Wherein, CD is the aperture, h is the depth, d1 is the first constant, and β1 is the second constant.

[0061] Optionally, the depth spacing between any two adjacent landing surfaces of the conductive layers is uniform, and the aperture of the contact hole satisfies the following formula:

[0062] CD=d2×(Total_WL_No.-current_WL_No.)+β2;

[0063] Among them, CD is the aperture, Total_WL_No. is the total number of layers of the conductive layer, current_WL_No. is the number of layers of the conductive layer corresponding to the contact hole along the stacking direction of the three-dimensional storage device, d2 is the third constant, and β2 is the fourth constant.

[0064] Optionally, for the conductive layer having uniform depth spacing of the landing surface, a difference rate of the depth spacing of the landing surface is less than or equal to 10%.

[0065] Optionally, the contact hole includes a dense contact hole and a non-dense contact hole, and the three-dimensional memory device includes a virtual hole, and the virtual hole is located at the periphery of the non-dense contact hole.

[0066] The three-dimensional memory device and the method for manufacturing the contact hole thereof in the embodiment of the present application, since the aperture of the contact hole is linearly positively correlated with the depth of the contact hole, multiple contact holes with different depths can be made simultaneously during the manufacturing process, and more contact holes with different depths can be made using one mask, thereby reducing the number of masks, which is beneficial to reducing costs and improving efficiency, and can reduce adverse effects on the previous layer structure, thereby improving the yield and reliability of the three-dimensional memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] Figure 1 It is a schematic flow chart of a method for manufacturing a contact hole of a three-dimensional memory device according to an embodiment of the present application;

[0068] Figure 2 It is a schematic diagram of a scene of a method for manufacturing a contact hole of a three-dimensional memory device according to an embodiment of the present application;

[0069] Figure 3 It is a schematic diagram of a scene of a method for manufacturing a contact hole of a three-dimensional memory device according to an embodiment of the present application;

[0070] Figure 4 It is a schematic flow chart of a method for manufacturing a contact hole of a three-dimensional memory device according to an embodiment of the present application;

[0071] Figure 5 It is a schematic flow chart of a method for manufacturing a contact hole of a three-dimensional memory device according to an embodiment of the present application;

[0072] Figure 6 It is a schematic flow chart of a method for manufacturing a contact hole of a three-dimensional memory device according to an embodiment of the present application;

[0073] Figure 7 It is a schematic flow chart of a method for manufacturing a contact hole of a three-dimensional memory device according to an embodiment of the present application;

[0074] Figure 8 It is a schematic flow chart of a method for manufacturing a contact hole of a three-dimensional memory device according to an embodiment of the present application;

[0075] Fig. 9 It is a schematic flow chart of a method for manufacturing a contact hole of a three-dimensional memory device according to an embodiment of the present application;

[0076] Fig.10It is a schematic flow chart of a method for manufacturing a contact hole of a three-dimensional memory device according to an embodiment of the present application;

[0077] Fig.11 It is a schematic flow chart of a method for manufacturing a contact hole of a three-dimensional memory device according to an embodiment of the present application;

[0078] Fig.12 It is a schematic flow chart of a method for manufacturing a contact hole of a three-dimensional memory device according to an embodiment of the present application;

[0079] Fig.13 It is a schematic flow chart of a method for manufacturing a contact hole of a three-dimensional memory device according to an embodiment of the present application;

[0080] Fig.14 It is a schematic diagram of a scene of a method for manufacturing a contact hole of a three-dimensional memory device according to an embodiment of the present application;

[0081] Fig.15 It is a schematic diagram of a scene of a method for manufacturing a contact hole of a three-dimensional memory device according to an embodiment of the present application;

[0082] Description of main component symbols:

[0083] Stacked structure 10 , landing layer 11 , contact hole 12 , dummy hole 13 ; mask 20 , first opening 21 , second opening 22 , third opening 23 . DETAILED DESCRIPTION

[0084] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and should not be construed as limiting the present application. In addition, it should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application.

[0085] In the description of the present application, it should be understood that the terms "length", "width", "up", "down", "left", "right", "horizontal", "top", "bottom", etc., indicating the orientation or position relationship are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0086] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0087] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0088] In the present application, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0089] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, and does not indicate the relationship between the various embodiments and / or settings discussed in itself. In addition, the various specific processes and examples of materials provided by the present application, but those of ordinary skill in the art can be aware of the application of other processes and / or the use scenarios of other materials.

[0090] In the present application, since the aperture of the contact hole is linearly positively correlated with the depth of the contact hole, multiple contact holes of different depths can be made simultaneously during the production, and more contact holes of different depths can be made using one mask, thereby reducing the number of masks, which is beneficial to reducing costs and improving efficiency, and can reduce adverse effects on the previous layer structure, thereby improving the yield and reliability of three-dimensional storage devices.

[0091] Embodiment 1

[0092] See also Figure 1 , Figure 2 and Figure 3 The method for manufacturing the contact hole 12 of the three-dimensional memory device of the embodiment of the present application includes:

[0093] Step S13: providing a stacked structure 10 for etching a contact hole 12, wherein the stacked structure 10 comprises a multi-layer landing layer 11, and ends of the multi-layer landing layer 11 form a step structure;

[0094] Step S14: determining the aperture of the contact hole 12 corresponding to the landing layer 11 according to the preset depth of the contact hole 12 to be etched, and the aperture of the contact hole 12 is linearly positively correlated with the depth of the contact hole 12;

[0095] Step S16: making a mask 20 on the stacked structure 10 according to the aperture;

[0096] Step S17 : under preset process conditions, the area of ​​the stacked structure 10 exposed from the mask 20 is etched to form a plurality of contact holes 12 , wherein the contact holes 12 are connected to the landing layer 11 at the step structure.

[0097] In the method for manufacturing the contact hole 12 of the three-dimensional memory device of the embodiment of the present application, since the aperture of the contact hole 12 is linearly positively correlated with the depth of the contact hole 12, multiple contact holes 12 with different depths can be manufactured simultaneously during manufacturing, and more contact holes 12 with different depths can be manufactured with one mask 20, thereby reducing defects such as over-etching and under-etching while reducing the number of masks 20, which is beneficial to reducing costs and improving efficiency, and can reduce adverse effects on the front layer structure prepared by the previous process, thereby improving the yield and reliability of the three-dimensional memory device.

[0098] The stacking structure 10 may refer to a structure formed by alternately stacking different first material layers and second material layers on a substrate (not shown in the figure), etching to form a step structure, and then covering it with an insulating layer, wherein the patterns of the first and second material layers are the same, forming a step pair, and the first material layer is located above the second material layer.

[0099] Figure 2 In the embodiment shown, the landing layer 11 is the first material layer.

[0100] It can be understood that the first material layer as the landing layer 11 may be a sacrificial layer used in a gate-last process, or include a conductor layer used in a gate-first process, and the second material layer is a dielectric layer; the landing layer may include an etch stop layer, or may not include an etch stop layer; Figure 2In the illustrated embodiment, a step of the stacked structure 10 includes a landing layer 11 and a dielectric layer, that is, a pair of first and second material layers, the landing layer is located above the dielectric layer, and the orthographic projections of the two on the substrate completely overlap, but the orthographic projections of the two may not completely overlap; when the first material layer is a dielectric layer and the second material layer is a sacrificial layer or includes a conductor layer, the first material layer can be the landing layer and also serve as an etching stop layer.

[0101] The end of the landing layer 11 may refer to a position for forming a contact hole in the landing layer 11. The end may be located, for example, at any end of the linearly extended landing layer 11 or in the middle between the two ends. The ends of the steps formed in two adjacent landing layers 11 in the vertical direction may be adjacent or non-adjacent on the horizontal plane, and the present application does not make specific limitations thereon.

[0102] Further, the substrate of the stacked structure 10 may include one or more materials selected from silicon (e.g., single crystal silicon), silicon germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), and silicon carbide (SiC). In this embodiment, the substrate of the stacked structure 10 is a silicon substrate.

[0103] Further, the substrate of the stacked structure 10 may be a single-layer structure. For example, it may be a single-layer structure made of the above-mentioned silicon, germanium, gallium arsenide and other materials. The substrate may also be a multi-layer structure. For example, the substrate may be a stacked layer of silicon and silicon germanium, a stacked layer of silicon and silicon carbide, a stacked substrate including silicon on insulator or silicon germanium on insulator, etc.

[0104] Further, the substrate of the stacked structure 10 is a peripheral substrate, that is, one or more peripheral devices may be formed therein. Further, the peripheral devices may include any suitable digital, analog and / or mixed signal peripheral circuits for the operation of the three-dimensional memory device. For example, the peripheral devices may include one or more of a data buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver, a charge pump, a current or voltage reference or any active or passive component of the circuit (e.g., a transistor, a diode, a resistor or a capacitor).

[0105] In one embodiment, the substrate is a supporting substrate, and after the stacking structure 10 is prepared on the supporting substrate, the top is bonded to the peripheral substrate and the supporting substrate is removed, or the top is bonded to a temporary substrate, the supporting substrate is removed, and the bottom is bonded to the peripheral substrate. The present invention is not limited thereto.

[0106] Specifically, the number of layers of the landing layer 11 is less than or equal to 250. For example, it is 1, 2, 6, 10, 50, 100, 150, 200, 250. In this way, the number of layers of the landing layer 11 is within a suitable range, and the difference in the aperture of the corresponding contact hole 12 is within a suitable range, so as to avoid the contact hole 12 being unable to be etched once due to too many layers of the landing layer 11.

[0107] It can be understood that in other embodiments, the total number of landing layers may be greater than 250. This is not specifically limited here.

[0108] In this embodiment, the landing layer 11 corresponds to the contact hole 12 one by one. In other words, each landing layer 11 corresponds to one contact hole 12, and each contact hole 12 corresponds to one landing layer 11. It can be understood that in other embodiments, one landing layer 11 may correspond to multiple contact holes 12; or one landing layer 11 may not have a corresponding contact hole 12. The corresponding relationship between the landing layer 11 and the contact hole 12 is not limited here.

[0109] Specifically, the landing layer 11 includes a landing surface, which is a connecting surface between the landing layer 11 and the contact hole 12. Figure 2 As shown, the landing surface is the top surface of the landing layer 11.

[0110] It can be understood that in other embodiments, the landing surface can also be the bottom surface of the landing layer 11; the landing surface can also be located between the top surface and the bottom surface of the landing layer 11; the landing surface can also be located on the side of the bottom surface of the landing layer 11 away from the stacking direction, that is, the depth to be etched of the contact hole is specifically set according to actual needs. The specific positional relationship between the landing surface and the landing layer 11 is not limited here.

[0111] The following is a specific description mainly taking the case where the landing surface of the present disclosure is the top surface of the landing layer 11 as an example.

[0112] Specifically, in the finally formed three-dimensional memory device, a conductive layer is formed at the position of the landing layer 11. The landing layer 11 may include the conductive layer or may be replaced by the conductive layer. The specific form of the landing layer 11 and whether the landing layer 11 is replaced later are not limited here.

[0113] Specifically, the two landing layers 11 are located at different depths in the stacked structure 10, and the projections of the landing surfaces of the landing layers 11 at different depths on the substrate are staggered, thereby forming a step. The specific form of the step structure is not limited here.

[0114] Specifically, in step S14, the contact hole 12 is circular, and the aperture of the contact hole 12 refers to the diameter of the contact hole 12. It can be understood that in other embodiments, the contact hole 12 may also be elliptical, and the aperture may be the length of the major axis of the contact hole 12. The specific shape of the contact hole 12 and the specific definition of the aperture are not limited here.

[0115] Specifically, in step S14, "the aperture of the contact hole 12 is linearly positively correlated with the depth of the contact hole 12" means that as the depth increases, the aperture also increases, and the increasing rate is fixed, and as the depth decreases, the aperture also decreases, and the decreasing rate is fixed.

[0116] Specifically, in step S16, a mask material layer may be fabricated on the stacked structure 10; an opening may be fabricated in the mask material layer according to the aperture, and the opening corresponds to the contact hole 12 to be formed. In this way, the mask 20 may be fabricated. In step S17, the area of ​​the stacked structure 10 exposed from the opening may be etched under preset process conditions to form the contact hole 12.

[0117] Further, the material layer of the mask 20 may include a photoresist layer. In this way, the sensitivity of the photoresist to light can be utilized to conveniently make openings on the material layer of the mask 20, which is conducive to improving efficiency. Furthermore, the photoresist may be a negative photoresist or a positive photoresist. The specific type of the photoresist is not limited here.

[0118] It is understood that in other embodiments, the mask material layer may include a hard mask; the mask material layer may also include a stacked layer of a photoresist layer and a hard mask, or may include an anti-reflection layer, etc. The specific form of the material of the mask 20 is not limited here.

[0119] Specifically, in step S16, the opening size of the mask 20 may be determined according to the aperture; and the mask 20 with an opening is manufactured in the stacked structure 10 according to the opening size, so that the size of the opening of the mask 20 is equal to the opening size.

[0120] Further, the opening size of the mask 20 can be determined according to the aperture and the compensation value of the mask 20. The compensation value is used to compensate for the difference between the mask opening size and the aperture of the contact hole etched using the mask. The compensation value is, for example, a constant coefficient. Further, in this embodiment, the opening size may refer to the diameter of the opening. In this way, by adjusting the opening size of the mask 20 by the compensation value of the mask 20, the aperture of the contact hole 12 formed on the stacked structure 10 can be made more accurate, which is conducive to improving the yield of the three-dimensional memory device.

[0121] Specifically, in step S17 , the region of the stacked structure 10 exposed from the mask 20 may be etched.

[0122] Specifically, in step S17, etching can simultaneously form all the contact holes 12 of the three-dimensional memory device. It is understood that in other embodiments, partial contact holes 12 of multiple three-dimensional memory devices can also be formed simultaneously. For example, in the case where the number of landing layers 11 is too many, even if the depth span of the contact holes 12 that can be formed simultaneously is increased by the method of the present invention, multiple contact holes 12 with too large depth spans cannot be etched simultaneously, so it is necessary to etch the contact holes 12 in sections, and each etching simultaneously forms multiple contact holes 12 with a depth span within a certain range.

[0123] Specifically, in step S17, the "connected" in "the contact hole 12 is connected to the landing layer 11 at the step structure" means that there is no barrier between the hole space of the contact hole 12 and the landing layer 11. When a conductive material is provided in the contact hole 12, the conductive material is in contact with the landing layer 11.

[0124] Illustratively, the conductive material within the contact hole 12 includes tungsten (W).

[0125] Please note that the step numbers and the order shown in the drawings herein do not limit the order in which the steps are executed, and the order of the steps can be adjusted within a reasonable range. Figure 1 In the example, step S13 is performed before step S14, but in other embodiments, step S13 may also be performed after step S14.

[0126] Embodiment 2

[0127] See also Figure 4 In some optional embodiments, the manufacturing method includes:

[0128] Step S181: when the landing layer 11 is a sacrificial layer, the sacrificial layer is replaced with a conductive layer;

[0129] Step S182: When the landing layer 11 is a non-sacrificial layer, the non-sacrificial layer serves as a conductive layer.

[0130] In this way, the landing layer 11 can be used as a conductive layer of the three-dimensional storage device, or can be replaced by a conductive layer of the three-dimensional storage device, so that a conductive layer can be formed at the position of the landing layer 11 and electrically connected to the conductive material filled in the contact hole 12.

[0131] Exemplarily, the sacrificial layer includes at least one of a silicon nitride layer (SiN), a silicon carbide layer (SiC), and amorphous silicon; the non-sacrificial layer includes at least one of a tungsten layer (W) and polysilicon; the conductive layer may also include a metal diffusion prevention layer, and the specific form of the conductive layer is not limited here. Exemplarily, the landing layer 11 as a conductive layer of the three-dimensional storage device may be the landing layer 11 directly as a conductive layer, or the landing layer 11 as a part of the conductive layer, which is not specifically limited here.

[0132] Specifically, in step S181, the landing layer 11 as a sacrificial layer may be etched away to form a gap region, and a conductive layer may be filled in the gap region. Furthermore, an etching method having a higher etching rate for the landing layer 11 than for the dielectric layer may be used to etch away the landing layer 11 as a sacrificial layer.

[0133] Specifically, in step S182 , the landing layer 11 may be used as a conductive layer of the three-dimensional memory device.

[0134] Embodiment 3

[0135] See also Figure 5 In some optional embodiments, step S14 includes:

[0136] Step S141: Obtain a first constant and a second constant;

[0137] Step S142: Determine the aperture according to the first constant, the second constant, the depth and the following first formula:

[0138] CD=d1*h+β1;

[0139] Wherein, CD is the aperture, h is the depth, d1 is the first constant, and β1 is the second constant.

[0140] In this way, it is possible to determine the aperture according to the depth of the contact hole 12 and the first formula, that is, the aperture is linearly positively correlated with the depth.

[0141] Specifically, in step S141, the specific method of obtaining the first constant and the second constant is not limited, but it can be understood that the first constant and the second constant are initially obtained by testing.

[0142] Specifically, in step S142, for the same stacked structure 10, when contact holes 12 with different depths are etched in the insulating layer material accommodating the contact holes 12, that is, the stacked structure 10 with the same material to be etched, the first constant and the second constant are fixed values. In this way, when the etching depth of the contact hole 12 to be etched is known, the same set of first constants and second constants can be used, and there is no need to repeatedly test to determine the first constant and the second constant, which is conducive to improving efficiency and reducing costs.

[0143] Please note that the same stacked structure 10 here at least requires the same material to be etched.

[0144] Embodiment 4

[0145] See also Figure 6 In some optional embodiments, before step S142, the manufacturing method includes:

[0146] Step S111: providing a first test structure provided with a first test mask, wherein the first test mask is formed with a plurality of first test holes with different apertures;

[0147] Step S112: under a first test process condition, etching the area of ​​the first test structure exposed from the first test hole to form a plurality of first test contact holes, wherein the first test contact holes include first reference test contact holes, and the first test process condition includes a first etching time;

[0148] Step S113: determining a first test value and a second test value according to a plurality of first test contact holes when the current depth of the first benchmark test contact hole corresponding to the first etching duration is equal to the preset depth of the first benchmark test contact hole;

[0149] Step S1141: determining whether the first test value and the second test value meet the contact hole requirement of the stack structure 10;

[0150] Step S1142: when the first test value and the second test value meet the contact hole requirement, the first test value and the second test value are respectively determined as a first constant and a second constant, and the corresponding first test process condition is used as a preset process condition;

[0151] Step S1143: When the first test value and the second test value do not meet the contact hole requirement, adjust the first test process condition, and enter the step of etching the area of ​​the first test structure exposed from the first test hole under the first test process condition to form a plurality of first test contact holes.

[0152] In this way, by testing the first test structure provided with a first test mask, the first constant and the second constant that meet the contact hole requirements of the stacked structure 10 and the corresponding preset process conditions can be obtained, so that when the contact hole 12 is subsequently etched under the preset process conditions according to the aperture determined based on the depth, the first constant and the second constant, it meets the requirements for the contact hole in the stacked structure 10, which is beneficial to improving the reliability and yield of the three-dimensional storage device.

[0153] Specifically, in step S111, the first test structure and the stacked structure 10 to be etched need to have at least the same material to be etched, so that the first constant, the second constant and the preset process conditions obtained by the test are suitable for etching the contact hole of the stacked structure 10, thereby improving the dimensional accuracy of the etching.

[0154] Specifically, in step S111, the number of the first test holes may be 2, 3, 4 or other numbers. The specific number of the first test holes is not limited here. It can be understood that the more the number of the first test holes, the larger the data sample used to obtain the first test value and the second test value, and the higher the accuracy of the first test value and the second test value obtained. Accordingly, the time when the etching of each contact hole 12 reaches the landing surface 11 is closer.

[0155] Specifically, in step S112, the first test process condition includes at least one of high frequency (HF) RF power, low frequency (LF) RF power, pressure in the etching chamber, flow rate of process gas and ratio of process gas. Thus, the first test process condition can be adjusted by adjusting the aforementioned conditions.

[0156] Further, the high frequency RF power is 2000W-2700W, for example, 2000W, 2010W, 2100W, 2400W, 2500W, 2700W; the low frequency RF power is 7000W-8000W, for example, 7000W, 7010W, 7100W, 7500W, 7800W, 8000W; the pressure in the etching chamber is 20mT-30mT, for example, 20mT, 21mT, 25mT, 28mT, 30mT. In this way, the above conditions can be adjusted within the above range to obtain the first constant and the second constant that meet the contact hole requirements of the stacked structure 10 and the corresponding preset process conditions.

[0157] Specifically, in step S1141, the first test value and the second test value meet the contact hole requirements. For example, based on the first and second test values ​​as the first and second constants, the contact hole diameters of different depths designed using the first formula meet the contact hole size range allowed under process conditions and design rules, or meet the design requirements based on device performance, etc. The specific content of the contact hole requirements may depend on the specific circumstances.

[0158] Specifically, in step S1141, each stacked structure 10 has a numerical range for determining whether the first test value and the second test value meet the contact hole requirement, but there is no numerical range applicable to all stacked structures 10 for determining whether the first test value and the second test value meet the contact hole requirement.

[0159] Specifically, in step S114, the contact hole requirements include but are not limited to: at least one of the aperture range of the contact hole 12 with the smallest aperture, the aperture range of the contact hole 12 with the largest aperture, and the impedance range of the conductor formed after the contact hole 12 is filled with a conductive material.

[0160] It is understood that the aperture of the smallest contact hole 12 cannot be less than the precision that can be achieved by the existing process, otherwise it is objectively impossible to achieve, and it cannot be too small to avoid too large resistance. The aperture of the largest contact hole 12 cannot interfere with other structures to avoid short circuit after filling with conductive material. The conductor formed after the conductive material is filled in the contact hole 12 has an impedance within a certain range to avoid impedance being too large or too small.

[0161] Specifically, in step S1141, the aperture of the contact hole 12 can be calculated based on the first test value and the second test value, and the impedance of the conductor formed after the contact hole 12 is filled with conductive material can also be calculated based on the first test value and the second test value, so as to determine whether a contact hole 12 that meets the contact hole requirements of the stacked structure 10 can be obtained based on the first test value and the second test value.

[0162] Specifically, in step S1142, when the results calculated based on the first test value and the second test value meet the aforementioned corresponding range, it can be determined that the first test value and the second test value meet the contact hole requirements, and the first test process conditions corresponding to the first test value and the second test value are used as preset process conditions.

[0163] Specifically, in step S1143, when the result calculated according to the first test value and the second test value does not satisfy the aforementioned corresponding range, it can be determined that the first test value and the second test value do not satisfy the contact hole requirement.

[0164] Specifically, in step S1143, the first test process condition can be adjusted by adjusting at least one of the low frequency RF power (LF), the pressure in the etching chamber, the flow rate of the process gas and the ratio of the process gas, and the test can be performed again using the adjusted first test process condition.

[0165] In step S112 , the diameter and depth of the first reference test contact hole are known.

[0166] Since the etching rates of contact holes with different apertures are different under the same etching process parameters, and the first constant will also change when the etching time changes, the etching completion time of the first benchmark test contact hole can be used as a reference for determining the first etching duration during the test process. When the current depth of the first benchmark test contact hole corresponding to the first etching duration is equal to the preset depth of the first benchmark test contact hole, it is determined that the first etching duration is appropriate, and the first test value and the second test value can be determined based on multiple first test contact holes. When the current depth of the first benchmark test contact hole corresponding to the first etching duration is not equal to the preset depth of the first benchmark test contact hole, it is determined that the first etching duration is inappropriate, so the first etching duration needs to be adjusted, and step S112 is entered.

[0167] In this embodiment, the first test contact hole with the smallest aperture corresponding to the landing layer 11 at the top along the stacking direction is used as the first reference test contact hole. In other embodiments, the first reference test contact hole may use other test contact holes with known apertures and hole depths. In selecting the size of the first reference test contact hole, the size of the contact hole 12 of a known specific size on the stacked structure 10 to be etched is preferred. At least, under the corresponding etching process conditions, the size of the first reference test contact hole is set so that its etching completion time is the same as that of the contact hole 12 of a known specific size on the stacked structure 10 to be etched.

[0168] When forming multiple first test contact holes, in some embodiments, the etching of the first benchmark test contact hole just reaches a preset depth, that is, the etching depth of the first benchmark test contact hole is equal to the preset depth of the first benchmark test contact hole, thereby the first etching time can be used as the etching time when the stack structure is formally etched, and the corresponding first constant and second constant are obtained.

[0169] In other embodiments, when forming multiple first test contact holes, the etching depth of the first benchmark test contact hole approaches the preset depth of the first benchmark test contact hole and does not exceed the preset depth, thereby forming a pre-benchmark test contact hole, and the completion of etching the pre-benchmark test contact hole is considered to be the completion of etching the first benchmark test contact hole.

[0170] The ratio of the depth of the pre-reference test contact hole to the depth of the first reference test contact hole may be 90%-99.9%, such as 90%, 91%, 92%, 95%, 98%, 99%, 99.9%. Preferably, the ratio approaches 1 infinitely.

[0171] Optionally, in some embodiments, after obtaining the first constant and the second constant, step S17 may include:

[0172] Under preset process conditions, the area of ​​the stacked structure 10 exposed from the mask 20 is etched to form a plurality of pre-contact holes;

[0173] A plurality of pre-contact holes are etched to form the contact holes 12 , thereby forming the contact holes 12 at the same time. The contact holes 12 are connected to the landing layer 11 at the step structure.

[0174] In this way, the landing layer 11 can be protected from being over-etched during the etching process of the pre-contact hole, thereby improving the process stability and the reliability of the three-dimensional memory device. It can be understood that the closer the ratio of the etching depth of the first benchmark test contact hole to the preset depth of the first benchmark test contact hole is to 1, the less the etching amount of the pre-contact hole is, and the less the over-etching degree of the final contact hole 12 is. The etching process for the pre-contact hole is preferably one that has a large etching selectivity ratio for the landing layer 11 and the material to be etched, so as to further reduce the over-etching degree of the final contact hole 12. The present invention does not specifically limit the etching process.

[0175] In other embodiments, the difference between the hole depth of the first reference test contact hole and the hole depth of the pre-reference test contact hole, that is, the retained thickness of the to-be-etched layer at the bottom of the first reference test contact hole, is set depending on the etching selectivity of the pre-contact hole etching process to the landing layer 11 and the to-be-etched material, so as to further reduce over-etching of the landing layer 11. The present invention does not specifically limit the specific thickness range.

[0176] In other embodiments, when forming a plurality of first test contact holes, the etching depth of the first reference test contact hole is close to the preset depth and exceeds the preset depth, which is not limited here and can be set according to actual needs.

[0177] Embodiment 5

[0178] See also Figure 7 In some optional embodiments, step S113 includes:

[0179] Step S1131: measuring the apertures of a plurality of first test contact holes to obtain a first test aperture;

[0180] Step S1132: measuring the depths of a plurality of first test contact holes to obtain a first test hole depth;

[0181] Step S1133: Determine a first test value and a second test value according to a plurality of groups of corresponding first test hole diameters and first test hole depths.

[0182] In this way, by measuring and calculating the plurality of first test contact holes, the first test value and the second test value can be obtained efficiently and accurately, which is beneficial to improving the accuracy of the subsequently determined hole diameter.

[0183] Specifically, the number of the first test contact holes may be 2, 3, 4 or other numbers. The specific number of the first test contact holes is not limited here.

[0184] Specifically, in step S1131, the diameter of the first test contact hole is measured. Figure 2 In the illustrated embodiment, the first test hole diameter refers to the diameter of a circular first test contact hole.

[0185] Specifically, in step S1132 , the depth of the first test contact hole refers to the size of the first test contact hole in the thickness direction of the stack structure 10 .

[0186] Specifically, in step S1133, a curve can be fitted according to multiple groups of corresponding first test hole diameters and first test hole depths, and the first test value and the second test value can be determined according to the curve. Specifically, the slope of the curve is the first test value, and the ordinate value of the curve when the abscissa is 0 is the second test value. In this way, by determining the test value by the method of fitting the curve, the accuracy of the first test value and the second test value can be improved.

[0187] It can be understood that there are at least two groups of corresponding first test apertures and first test hole depths used to fit the curve, that is, the number of test holes used to determine the first test value and the second test value is at least two. The more groups selected, the higher the accuracy of the first test value and the second test value obtained. In other embodiments, calculations can also be performed based on multiple groups of corresponding first test apertures and first test hole depths to determine the first test value and the second test value. For example, using two groups of corresponding first test apertures and first test hole depths, substitute into the first formula to solve the binary linear equation about the first test value and the second test value. The specific method of determining the first test value and the second test value based on multiple groups of corresponding first test apertures and first test hole depths is not limited here.

[0188] Embodiment 6

[0189] See also Figure 8 In some optional embodiments, the manufacturing method includes:

[0190] Step S152: When the depth intervals between the landing surfaces of any two adjacent landing layers 11 are uniform, the aperture of the contact hole 12 corresponding to each landing layer 11 is determined according to the following second formula:

[0191] CD=d2×(Total_WL_No.-current_WL_No.)+β2;

[0192] Among them, CD is the aperture, Total_WL_No. is the total number of layers of the landing layer 11, current_WL_No. is the number of layers of the landing layer 11 corresponding to the contact hole 12 along the stacking direction of the three-dimensional storage device, d2 is the third constant, and β2 is the fourth constant.

[0193] In this way, when the depth spacing between adjacent landing surfaces remains unchanged, even if the total number of landing layers 11 changes, it is possible to determine the aperture of the contact hole 12 corresponding to each conductive layer according to the number of conductive layers, thereby efficiently and accurately determining the aperture of the contact hole 12, thereby improving the manufacturing efficiency and the yield of the three-dimensional storage device.

[0194] Specifically, in step S152, the specific method of obtaining the third constant and the fourth constant is not limited, but it can be understood that the initial acquisition of the third constant is obtained by testing, and the initial acquisition of the fourth constant can be based on design rules, process conditions or device design requirements.

[0195] Specifically, in step S152, in the second formula, the total number of landing layers 11, the third constant, and the fourth constant are known variables, the number of landing layers 11 corresponding to the contact holes 12 along the stacking direction of the three-dimensional memory device is the independent variable, and the aperture is the dependent variable. In this way, the number of landing layers 11 corresponding to each contact hole 12 along the stacking direction of the three-dimensional memory device can be substituted into the first formula to determine the aperture corresponding to each contact hole 12.

[0196] Specifically, in step S152, the third constant is a fixed value for the same stacked structure 10. Thus, when etching the contact hole 12 for the same stacked structure 10, the same third constant can be used, and there is no need to repeatedly test the stacked structure 10 of the same specification, which is conducive to improving efficiency and reducing costs.

[0197] Please note that the same stacked structure 10 here requires the same material to be etched and the same second reference test holes.

[0198] In other embodiments, when the materials to be etched of two stacked structures 10 are the same, the second reference test holes are the same, and the depth spacing between the landing surfaces of any two adjacent landing layers 11 is equal to or a multiple of each other, Total_WL_No. and current_WL_No. can be recounted according to the depth of the landing surface of the specific landing layer 11, and the aperture can be set using the method of this embodiment.

[0199] The second reference test hole will be described in subsequent embodiments.

[0200] Specifically, in step S152, the fourth constant is the aperture value of the contact hole 12 corresponding to the topmost landing layer 11 along the stacking direction of the three-dimensional memory device 10. The fourth constant is also the aperture value of the contact hole 12 with the smallest aperture.

[0201] It can be understood that for the same stacking structure, the first constant, the second constant, the third constant and the fourth constant are related. Specifically, d2 = d1*Δ; β2 = d1*c+β1. Among them, Δ is the depth spacing of the landing surfaces of adjacent landing layers 11, c is the depth of the contact hole 12 with the smallest aperture, d1 is the first constant in the first formula, and β1 is the second constant in the first formula.

[0202] Embodiment 7

[0203] See also Fig. 9 In some optional embodiments, before step S152, the manufacturing method includes:

[0204] Step S151: when the difference rate of the depth spacing between any two adjacent landing surfaces is less than or equal to 10%, it is determined that the depth spacing of the landing surfaces is uniform.

[0205] In this way, whether the depth spacing of the landing surface is uniform can be determined based on whether the difference rate of the depth spacing is within the difference rate range, with high accuracy and efficiency.

[0206] Specifically, the difference rate satisfies the following third formula:

[0207] K = (DM) / M;

[0208] Wherein, K is the difference rate, D is the depth distance between the landing surface corresponding to the contact hole 12 and the next landing surface along the stacking direction of the three-dimensional memory device, M is the reference value of the difference rate, and the landing surface is the connecting surface between the conductive layer and the contact hole 12.

[0209] Specifically, the reference value of the difference rate is the average value of the depth intervals of all adjacent landing surfaces.

[0210] It is understood that in other embodiments, the reference value of the difference rate may also be the median, mode or other value of the depth intervals of all adjacent landing surfaces. The specific form of the reference value of the difference rate is not specifically limited here.

[0211] Embodiment 8

[0212] See also Fig.10 In some optional embodiments, before step S152, the manufacturing method includes:

[0213] Step S121: providing a second test structure provided with a second test mask, wherein the second test mask is formed with a plurality of second test holes having different apertures;

[0214] Step S122: under a second test process condition, etching the area of ​​the second test structure exposed from the second test hole to form a plurality of second test contact holes, wherein the second test contact holes include second reference test contact holes, and the second test process condition includes a second etching time;

[0215] Step S123: when the current depth of the second benchmark test contact hole corresponding to the second etching time is equal to the preset depth of the second benchmark test contact hole, determining a third test value according to the depth spacing between the plurality of second test contact holes and the landing surface;

[0216] Step S124: determining whether the third test value meets the contact hole requirement of the stack structure 10;

[0217] Step S126: when the third test value meets the contact hole requirement, the third test value is determined as a third constant, and the corresponding second test process condition is used as a preset process condition;

[0218] Step S125: when the third test value does not meet the contact hole requirement, adjusting the second test process condition, and entering the step of etching the area of ​​the second test structure exposed from the second test hole under the second test process condition to form a plurality of second test contact holes.

[0219] In this way, by testing the second test structure provided with the second test mask, the third constant that meets the contact hole requirements of the stacked structure 10 and the corresponding preset process conditions can be obtained, which is beneficial to improving the reliability and yield of the three-dimensional memory device.

[0220] Specifically, in step S121 , the second test structure and the stacked structure 10 to be etched need to be at least made of the same material to be etched.

[0221] Please note that the explanations and descriptions of the second test hole, the second reference test contact hole, the pre-reference test contact hole, etc. are similar to the explanations and descriptions of the first test hole, the first reference test contact hole, and the pre-reference test contact hole in Example 4. The explanations and descriptions of the second test process conditions are similar to the explanations and descriptions of the first test process conditions. The explanations and descriptions of the contact hole requirements can be referred to Example 4. To avoid redundancy, they will not be repeated here.

[0222] Specifically, in step S123 , the third test value may be determined based on all the second test contact holes, or may be determined based on part of the second test contact holes, which is not limited here.

[0223] Specifically, in step S124, each stacked structure 10 has a numerical range for determining whether the third test value meets the contact hole requirement, but there is no numerical range applicable to all stacked structures 10 for determining whether the third test value meets the contact hole requirement.

[0224] Please note that the explanation and description of the contact hole requirements can be found in the previous text and will not be repeated here to avoid redundancy.

[0225] Specifically, in step S124, the aperture of the contact hole 12 can be calculated based on the third test value, and the impedance of the conductor formed after the contact hole 12 is filled with conductive material can also be calculated based on the third test value, so as to determine whether a contact hole 12 that meets the contact hole requirements of the stacked structure 10 can be obtained based on the third test value.

[0226] Specifically, in step S125, when the result calculated according to the third test value satisfies the aforementioned corresponding range, it can be determined that the third test value meets the contact hole requirement, and the second test process condition corresponding to the third test value is used as the preset process condition.

[0227] Specifically, in step S126, when the result calculated according to the third test value does not satisfy the aforementioned corresponding range, it can be determined that the third test value does not meet the contact hole requirement.

[0228] Specifically, in step S1243, the second test process conditions can be adjusted by adjusting at least one of the low frequency RF power (LF), the pressure in the etching chamber, the flow rate of the process gas and the ratio of the process gas, and the test can be performed again using the adjusted second test process conditions.

[0229] Embodiment 9

[0230] See also Fig.11 In some optional embodiments, step S123 includes:

[0231] Step S1231: measuring the apertures of a plurality of second test contact holes to obtain second test apertures;

[0232] Step S1232: measuring the depths of the plurality of second test contact holes to obtain the second test hole depths;

[0233] Step S1233: determining an intermediate value according to a plurality of groups of corresponding second test hole diameters and second test hole depths;

[0234] Step S1234: Determine a third test value based on the intermediate value and the depth interval of the landing surface.

[0235] In this way, by measuring and calculating the plurality of second test contact holes, the third test value can be obtained efficiently and accurately, which is beneficial to improving the accuracy of the subsequently determined aperture.

[0236] Specifically, the number of the second test contact holes may be 2, 3, 4 or other numbers. The specific number of the second test contact holes is not limited here.

[0237] Specifically, in step S1231, the diameter of the second test contact hole is measured. Figure 2 In the illustrated embodiment, the second test hole diameter refers to the diameter of the second test contact hole.

[0238] Specifically, in step S1232 , the depth of the second test contact hole refers to the size of the second test contact hole in the thickness direction of the stack structure 10 .

[0239] Specifically, in step S1233, a curve can be fitted according to multiple groups of corresponding first test hole diameters and first test hole depths, and the intermediate value can be determined according to the slope of the curve. Specifically, the slope of the curve is the intermediate value. In this way, the accuracy of the intermediate value can be improved by determining the intermediate value by the method of fitting the curve.

[0240] It can be understood that the corresponding second test hole diameters and second test hole depths used for fitting the curve are at least two groups, and the more groups selected, the higher the accuracy of the intermediate value obtained. The specific method of determining the intermediate value based on multiple groups of corresponding second test hole diameters and second test hole depths is not limited here.

[0241] Specifically, in step S1234, the product of the intermediate value and the depth spacing of the landing surface is used as the third test value.

[0242] Embodiment 10

[0243] See also Fig.12 In some optional embodiments, before step S152, the manufacturing method includes:

[0244] Step S1501: obtaining the contact hole requirements of the stacked structure 10, wherein the contact hole requirements include the aperture value of the contact hole 12 with the smallest aperture;

[0245] Step S1502: Determine the aperture value as a fourth constant.

[0246] In this way, the fourth constant is determined based on the contact hole requirement of the stacked structure 10 so that the fourth constant meets the contact hole requirement of the stacked structure 10 , which is beneficial to ensure the normal operation of the three-dimensional memory device and improve the reliability of the three-dimensional memory device.

[0247] Specifically, the contact hole 12 with the smallest aperture may be the contact hole 12 corresponding to the uppermost landing layer in the stacking direction in the stacking structure. When the contact hole 12 with the smallest aperture corresponding to the uppermost landing layer 11 in the stacking direction is used as the reference test contact hole, the reference test contact hole corresponds to the contact hole 12 with the smallest aperture included in the contact hole requirement.

[0248] Embodiment 11

[0249] See also Fig.13 , Fig.14 and Fig.15 In some optional embodiments, the contact hole 12 includes a dense contact hole 12 (dense) and a non-dense contact hole 12, and step S16 includes:

[0250] Step S161: manufacturing a mask 20 material layer on the stack structure 10;

[0251] Step S162: making a first opening 21, a second opening 22 and a third opening 23 in the material layer of the mask 20 according to the aperture, wherein the first opening 21, the second opening 22 and the third opening 23 correspond to the dense contact hole 12, the non-dense contact hole 12 and the virtual hole 13 of the three-dimensional memory device respectively;

[0252] Step S17 includes:

[0253] Step S173 : under preset process conditions, etching the areas of the stacked structure 10 exposed from the first opening 21 , the second opening 22 and the third opening 23 to form a dense contact hole 11 , a non-dense contact hole 12 and a dummy hole 13 , wherein the dummy hole 13 is located at the periphery of the non-dense contact hole 12 .

[0254] In this way, by making the third opening 23 at a position corresponding to the periphery of the second opening 22, a virtual hole 13 is formed on the periphery of the non-dense contact hole 12 formed by etching based on the mask 20, so that the etching load at the non-dense hole can be close to the etching load at the dense hole, thereby improving the etching uniformity around the non-dense contact hole 12, avoiding etching defects in the non-dense contact hole 12 due to the difference in etching load between the non-dense contact hole 12 and the dense contact hole 11, and reducing the risk of abnormal etching morphology of the non-dense contact hole 12 finally formed, thereby improving the quality of the contact hole 12 and the yield of the three-dimensional storage device.

[0255] Specifically, the non-dense contact holes 12 include isolated contact holes 12 (i so) and semi-isolated contact holes 12 (semi-i so).

[0256] Specifically, in step S162 , the first opening 21 , the second opening 22 and the third opening 23 may be manufactured simultaneously, or the first opening 21 , the second opening 22 and the third opening 23 may be manufactured separately.

[0257] Specifically, in step S162, one or more third openings 23 may be formed at positions corresponding to the periphery of the second opening 22. In step S173, one or more dummy holes 13 are formed at the periphery of the non-dense contact hole 12.

[0258] Specifically, in step S173, the periphery refers to being adjacent to and surrounding. In other words, the third opening 23 is formed in a region adjacent to and surrounding the second opening 22, and the surrounding may be partial or full. The virtual hole 13 is located in a region adjacent to and surrounding the non-dense contact hole 12.

[0259] It can be understood that the virtual hole 13 can be located at a position that completely surrounds the isolated contact hole 12, so that the etching load around the isolated contact hole 12 is equivalent to the etching load of the dense contact hole; or Fig.14As shown, the virtual hole 13 can be located on the side of the semi-isolated contact hole 12 away from the dense contact hole 12 adjacent thereto so that the etching load around the semi-isolated contact hole 12 is equivalent to the etching load of the dense contact hole, thereby improving the uniformity of etching and avoiding abnormal morphology after etching caused by the change of etching load of the non-dense hole. The aperture of the virtual hole 13 is not specifically limited.

[0260] Embodiment 12

[0261] In some optional embodiments, the preset process conditions include: high frequency radio frequency power (HF) is 2000W-2700W; low frequency radio frequency power (LF) is 7000W-8000W;

[0262] The pressure in the etching chamber is 20mT-30mT.

[0263] In this way, under such process conditions of high-frequency RF power, low-frequency RF power and pressure in the etching chamber, the contact hole 12 is etched in coordination with the mask 20 made according to the aperture, so that multiple contact holes 12 with different depths can be made simultaneously.

[0264] Specifically, the high-frequency radio frequency power is, for example, 2000 W, 2010 W, 2100 W, 2400 W, 2500 W, or 2700 W. The specific value of the high-frequency radio frequency power is not limited herein.

[0265] Specifically, the low-frequency radio frequency power is, for example, 7000 W, 7010 W, 7100 W, 7500 W, 7800 W, or 8000 W. The specific value of the low-frequency radio frequency power is not limited herein.

[0266] Specifically, the pressure in the etching chamber is, for example, 20mT, 21mT, 25mT, 28mT, and 30mT. The specific value of the pressure in the etching chamber is not limited here. In this way, it can avoid the failure of ignition due to too low pressure, and it can also avoid the etching rate not being modulated by the aperture due to too high pressure.

[0267] Embodiment 13

[0268] In some optional embodiments, the process gas of the preset process conditions includes etching gas, inert gas and additive gas, and the flow ratio is (80-100):(600-1000):(480-800).

[0269] In this way, etching gas is used to provide free radicals to etch the contact hole 12, inert gas is used as a carrier gas and provides bombardment energy, and added gas is used to adjust the morphology of the formed etching hole. The flow ratio of each gas is in an appropriate range, which is conducive to forming a contact hole 12 with a high aspect ratio and better morphology.

[0270] Specifically, the flow ratio of the etching gas, the inert gas and the additive gas is, for example, 80:600:480, 100:1000:800. These are only examples, and the specific flow ratio of the etching gas, the inert gas and the additive gas is not limited here, and can be specifically set according to the actual material to be etched, the pattern to be etched, the etching depth, and the specific etching process.

[0271] Specifically, the etching gas includes a carbon fluorine gas, and the carbon fluorine gas includes, for example, at least one of C4F6 and C4F8. The specific type of the carbon fluorine gas is not limited here, and can be specifically set according to the actual material to be etched, the pattern to be etched, the etching depth, and the specific etching process. In this way, a variety of carbon fluorine gases are provided to adapt to more actual production scenarios.

[0272] Specifically, the inert gas includes at least one of Ar and Xe. The specific type of the inert gas is not limited here, and can be specifically set according to the actual material to be etched, the pattern to be etched, the etching depth, and the specific etching process.

[0273] Embodiment 14

[0274] In some optional embodiments, the added gas includes O2, CO and N2, and the flow ratio is (80-100):(300-500):(100-200).

[0275] In this way, the type and flow rate ratio of the added gas are appropriate, which can adjust the morphology of the contact hole obtained by etching and avoid the etching process being unable to continue due to the accumulation of by-products at the contact hole opening.

[0276] Specifically, the flow ratio of O2, CO and N2 is, for example, 80:300:100, 100:500:200, etc. The above is only an example, and the specific flow ratio of O2, CO and N2 is not limited here.

[0277] Embodiment 15

[0278] In some optional embodiments, the etching gas includes C4F6, and the inert gas includes Ar. The use of relatively cheap carbon fluorine gas and inert gas can reduce costs. It can be understood that in addition to the aforementioned gases, the process gas may also include other gases. Optionally, the temperature of the etching process is 20°C-90°C. For example, 20°C, 25°C, 50°C, 65°C, 75°C, 80°C, and 90°C. In this way, the etching temperature is in a suitable range, which can avoid deformation of the contact hole 12 caused by excessively high temperature, and can also avoid too low an etching rate caused by too low a temperature. In this way, it is beneficial to improve the quality of the contact hole 12. Preferably, the etching temperature is 65°C-75°C. For example, 65°C, 66°C, 68°C, 70°C, 72°C, and 75°C. In this way, the balance of the etching rate and the morphology of the contact hole 12 after etching are taken into account, and the overall effect is better.

[0279] Embodiment 16

[0280] See also Figure 2 The three-dimensional memory device of the embodiment of the present application includes a plurality of contact holes 12 with different depths, and the contact holes 12 are manufactured by the manufacturing method of the contact holes 12 of any one of the first to fifteenth embodiments.

[0281] In the three-dimensional memory device of the embodiment of the present application, since the aperture of the contact hole 12 is linearly positively correlated with the depth of the contact hole 12, multiple contact holes 12 with different depths can be made at the same time during manufacturing, and more contact holes 12 can be made with one mask 20, thereby reducing the number of masks 20, which is conducive to reducing costs and improving efficiency, and can reduce adverse effects on the front layer structure, and improve the yield and reliability of the three-dimensional memory device. For the explanation and description of this part, please refer to the previous text, and in order to avoid redundancy, it will not be repeated here.

[0282] Embodiment 17

[0283] See also Figure 2 The three-dimensional storage device of the embodiment of the present application includes a plurality of conductive layers and a plurality of contact holes 12 with different depths. The ends of the plurality of conductive layers form a step structure. The contact hole 12 connects the conductive layers at the step structure. The aperture of the contact hole 12 is linearly positively correlated with the depth of the contact hole 12.

[0284] In the three-dimensional memory device of the embodiment of the present application, since the aperture of the contact hole 12 is linearly positively correlated with the depth of the contact hole 12, multiple contact holes 12 with different depths can be made at the same time during manufacturing, and more contact holes 12 can be made with one mask 20, thereby reducing the number of masks 20, which is conducive to reducing costs and improving efficiency, and can reduce adverse effects on the front layer structure, and improve the yield and reliability of the three-dimensional memory device. For the explanation and description of this part, please refer to the previous text, and in order to avoid redundancy, it will not be repeated here.

[0285] Embodiment 18

[0286] In some optional embodiments, the diameter of the contact hole 12 and the depth of the contact hole 12 satisfy the following formula:

[0287] CD=d1*h+β1;

[0288] Wherein, CD is the aperture, h is the depth, d1 is the first constant, and β1 is the second constant.

[0289] Since the diameter of the contact hole 12 is linearly positively correlated with the depth of the contact hole 12, when manufacturing a mask that allows multiple contact holes 12 of different depths to be manufactured at the same time, the aperture design can be performed by testing the linear positively correlated relationship function, without the need to test and design the corresponding aperture for each contact hole of different hole depths, thereby reducing the difficulty and cost of contact hole aperture design. For the explanation and description of this part, please refer to the previous text, and to avoid redundancy, it will not be repeated here.

[0290] Embodiment 19

[0291] In some optional embodiments, the depth spacing between the landing surfaces of any two adjacent conductive layers is uniform.

[0292] The aperture of the contact hole 12 satisfies the following formula:

[0293] CD=d2×(Total_WL_No.-current_WL_No.)+β2;

[0294] Among them, CD is the aperture, Total_WL_No. is the total number of conductive layers, current_WL_No. is the number of conductive layers corresponding to the contact hole 12 along the stacking direction of the three-dimensional storage device, d2 is the third constant, and β2 is the fourth constant.

[0295] Since the aperture of the contact hole 12 is linearly positively correlated with the depth of the contact hole 12, and when the depth spacing of the landing surfaces of any two adjacent conductive layers is uniform, the depth of the contact hole changes with the number of layers of the conductive layer, that is, the aperture changes with the number of layers of the conductive layer, and this change conforms to the above formula. Therefore, when making a mask that allows multiple contact holes 12 with different depths to be made at the same time, the aperture of the contact holes corresponding to the conductive layers with different numbers of layers can be designed by the linear positive correlation relationship function obtained by testing. Under the condition that the layers to be etched remain unchanged and the depth spacing of the adjacent landing surfaces remains unchanged, even if the total number of conductive layers changes, there is no need to test and design the corresponding aperture for the contact holes of different depths corresponding to each conductive layer with different numbers of layers, thereby reducing the difficulty and cost of contact hole aperture design. For the explanation and description of this part, please refer to the previous text, and in order to avoid redundancy, it will not be repeated here.

[0296] Embodiment 20

[0297] In some optional embodiments, the landing surface has a conductive layer with uniform depth spacing, and a difference rate of the depth spacing of the landing surface is less than or equal to 10%.

[0298] For explanations and descriptions of this part, please refer to the previous text. To avoid redundancy, we will not repeat them here.

[0299] Embodiment 21

[0300] In some optional embodiments, the contact hole 12 includes a dense contact hole 12 and a non-dense contact hole 12, and the three-dimensional memory device includes a virtual hole 13, and the virtual hole 13 is located at the periphery of the non-dense contact hole 12. For the explanation and description of this part, please refer to the previous text, and it will not be repeated here to avoid redundancy.

[0301] In the description of this specification, the description with reference to the terms "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0302] In addition, the above are only preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A method for manufacturing a contact hole of a three-dimensional memory device, characterized in that: include: Providing a stacking structure for etching contact holes, the stacking structure comprising a plurality of landing layers, wherein ends of the plurality of landing layers form a step structure; According to the preset depth of the contact hole to be etched, determining the aperture of the contact hole corresponding to the landing layer, wherein the aperture of the contact hole is linearly positively correlated with the depth of the contact hole; Making a mask on the stacked structure according to the aperture; Under preset process conditions, the area of ​​the stacked structure exposed from the mask is etched to form a plurality of contact holes, wherein the contact holes are connected to the landing layer at the step structure.

2. The method for manufacturing a contact hole according to claim 1, characterized in that: The production method comprises: In the case where the landing layer is a sacrificial layer, replacing the sacrificial layer with a conductive layer; In the case where the landing layer is a non-sacrificial layer, the non-sacrificial layer serves as a conductive layer.

3. The method for manufacturing a contact hole according to claim 1, characterized in that: Determining the aperture of the contact hole corresponding to the landing layer according to the preset depth of the contact hole to be etched, comprising: Get the first constant and the second constant; The aperture is determined according to the first constant, the second constant, the depth and the following first formula: CD=d1*h+β1; Wherein, CD is the aperture, h is the depth, d1 is the first constant, and β1 is the second constant.

4. The method for manufacturing a contact hole according to claim 3, characterized in that: Before the step of determining the aperture according to the first constant, the second constant, the depth and the following first formula, the manufacturing method includes: Providing a first test structure having a first test mask, wherein the first test mask is formed with a plurality of first test holes having different apertures; Under a first test process condition, etching the area of ​​the first test structure exposed from the first test hole to form a plurality of first test contact holes, wherein the first test contact holes include first reference test contact holes, and the first test process condition includes a first etching time; When the current depth of the first reference test contact hole corresponding to the first etching duration is equal to the preset depth of the first reference test contact hole, determining a first test value and a second test value according to a plurality of the first test contact holes; determining whether the first test value and the second test value meet the contact hole requirement of the stack structure; In the case that the first test value and the second test value meet the contact hole requirement, the first test value and the second test value are respectively determined as the first constant and the second constant, and the corresponding first test process condition is used as the preset process condition; When the first test value and the second test value do not meet the contact hole requirement, the first test process condition is adjusted, and the step of etching the area of ​​the first test structure exposed from the first test hole under the first test process condition to form a plurality of first test contact holes is performed.

5. The method for manufacturing a contact hole according to claim 4, characterized in that: Determining a first test value and a second test value according to the plurality of the first test contact holes comprises: Measuring the apertures of the plurality of first test contact holes to obtain a first test aperture; Measuring the depths of the plurality of first test contact holes to obtain a first test hole depth; The first test value and the second test value are determined according to a plurality of corresponding groups of the first test hole diameters and the first test hole depths.

6. The method for manufacturing a contact hole according to claim 1, characterized in that: The production method comprises: When the depth intervals of the landing surfaces of any two adjacent landing layers are uniform, the apertures of the contact holes corresponding to the landing layers are determined according to the following second formula: CD=d2×(Total_WL_No.-current_WL_No.)+β2; Among them, CD is the aperture, Total_WL_No. is the total number of layers of the landing layer, current_WL_No. is the number of layers of the landing layer corresponding to the contact hole along the stacking direction of the three-dimensional memory device, d2 is the third constant, and β2 is the fourth constant.

7. The method for manufacturing a contact hole according to claim 6, characterized in that: Before the step of determining the aperture of the contact hole corresponding to the landing layer according to the following second formula when the depth spacing of the landing surfaces of any two adjacent landing layers is uniform, the manufacturing method includes: When the difference rate of the depth spacing between any two adjacent landing surfaces is less than or equal to 10%, it is determined that the depth spacing of the landing surfaces is uniform.

8. The method for manufacturing a contact hole according to claim 6, characterized in that: Before the step of determining the aperture of the contact hole corresponding to the landing layer according to the following second formula when the depth spacing of the landing surfaces of any two adjacent landing layers is uniform, the manufacturing method includes: Providing a second test structure provided with a second test mask, wherein the second test mask is formed with a plurality of second test holes having different apertures; Under a second test process condition, etching the area of ​​the second test structure exposed from the second test hole to form a plurality of second test contact holes, wherein the second test contact holes include second reference test contact holes, and the second test process condition includes a second etching time; When the current depth of the second benchmark test contact hole corresponding to the second etching time is equal to the preset depth of the second benchmark test contact hole, determining a third test value according to the depth spacing between the plurality of second test contact holes and the landing surface; determining whether the third test value meets the contact hole requirement of the stack structure; In the case where the third test value meets the contact hole requirement, determining the third test value as the third constant, and using the corresponding second test process condition as the preset process condition; When the third test value does not meet the contact hole requirement, the second test process condition is adjusted, and the step of etching the second test structure in the area exposed from the second test hole under the second test process condition to form a plurality of second test contact holes is performed.

9. The method for manufacturing a contact hole according to claim 8, characterized in that: Determining a third test value according to the depth spacing between the plurality of the second test contact holes and the landing surface comprises: Measuring the apertures of the plurality of second test contact holes to obtain second test apertures; Measuring the depths of the plurality of second test contact holes to obtain a second test hole depth; Determine an intermediate value according to a plurality of corresponding groups of the second test hole diameters and the second test hole depths; The third test value is determined according to the intermediate value and the depth interval of the landing surface.

10. The method for manufacturing a contact hole according to claim 6, characterized in that: Before the step of determining the aperture of the contact hole corresponding to each landing layer according to the preset depth of the contact hole to be etched, the manufacturing method includes: Acquiring contact hole requirements of the stacked structure, wherein the contact hole requirements include an aperture value of the contact hole with the smallest aperture; The aperture value is determined as the fourth constant.

11. The method for manufacturing a contact hole according to claim 1, characterized in that: The contact holes include dense contact holes and non-dense contact holes, and a mask is made in the stacked structure according to the hole diameter, including: manufacturing a mask material layer on the stacked structure; Making a first opening, a second opening and a third opening in the mask material layer according to the aperture, wherein the first opening, the second opening and the third opening correspond to the dense contact hole, the non-dense contact hole and the virtual hole of the three-dimensional memory device respectively; Etching the area of ​​the stacked structure exposed from the mask to form the contact hole under preset process conditions includes: Under the preset process conditions, the areas of the stacked structure exposed from the first opening, the second opening and the third opening are etched to form the dense contact hole, the non-dense contact hole and the virtual hole, and the virtual hole is located at the periphery of the non-dense contact hole.

12. A three-dimensional memory device, characterized in that: It comprises a plurality of contact holes with different depths, and the contact holes are made by the contact hole making method according to any one of claims 1 to 11.

13. A three-dimensional storage device, characterized in that: It comprises multiple conductive layers and multiple contact holes with different depths, wherein the ends of the multiple conductive layers form a step structure, the contact holes are connected to the conductive layers at the step structure, and the aperture of the contact holes is linearly positively correlated with the depth of the contact holes.

14. The three-dimensional memory device according to claim 13, characterized in that: The diameter of the contact hole and the depth of the contact hole satisfy the following formula: CD=d1*h+β1; Wherein, CD is the aperture, h is the depth, d1 is the first constant, and β1 is the second constant.

15. The three-dimensional memory device according to claim 13, characterized in that: The depth spacing between any two adjacent landing surfaces of the conductive layer is uniform. The aperture of the contact hole satisfies the following formula: CD=d2×(Total_WL_No.-current_WL_No.)+β2; Among them, CD is the hole diameter, Total_WL_No. is the total number of layers of the conductive layer, current_WL_No. is the number of layers of the conductive layer corresponding to the contact hole along the stacking direction of the three-dimensional memory device, d2 is the third constant, and β2 is the fourth constant.

16. The three-dimensional memory device according to claim 15, characterized in that: The conductive layer has uniform depth spacing of the landing surface, and a difference rate of the depth spacing of the landing surface is less than or equal to 10%.

17. The three-dimensional memory device according to claim 13, characterized in that: The contact holes include dense contact holes and non-dense contact holes, and the three-dimensional memory device includes dummy holes located at the periphery of the non-dense contact holes.

Images