Multi-phase power supply and control circuit and control method thereof

Abstract

The invention discloses a multi-phase power supply and a control circuit and a control method thereof. The control circuit comprises a current reference module configured to obtain a current reference signal according to a current sampling signal of a first phase power conversion circuit in N phase power conversion circuits; the conduction time adjusting module is configured to compare the current sampling signals of the N-phase power conversion circuits with the current reference signal respectively and obtain a plurality of conduction time control signals according to the comparison result, and the conduction time control signals control the conduction time of the second-phase power conversion circuit to the Nth-phase power conversion circuit respectively; and the control module is configured to respectively obtain pulse width modulation signals of the power conversion circuits from the second phase to the Nth phase according to the plurality of on-time control signals so as to control the average value of the output current of each phase of power conversion circuit to be equal. According to the control circuit of the multi-phase power supply, the current balancing speed can be improved on the premise that the current balancing precision is met.

Description

Technical Field

[0001] The present invention relates to the technical field of switching power supplies, and more specifically, to a multi-phase power supply and a control circuit and a control method thereof. Background Art

[0002] The exponential growth of the scale of Internet of Things (IoT) cloud services has driven significant advances in data centers, networks, and telecommunications equipment. At the same time, the continued increase in data and information has posed new challenges to the processing efficiency of servers in data centers. Therefore, how to efficiently power and dissipate heat for these devices while minimizing power consumption has become an important issue in the existing power supply technology field.

[0003] Multiphase power supply is a technology that connects multiple power conversion circuits in parallel and interleaves them. Each channel has a corresponding power switch tube and inductor, and the switching modulation process is distributed to different phases to achieve the adjustment and control of the power supply. The PWM (pulse width modulation) signals between phases in a multiphase power supply can be the same or staggered by a certain phase, so that the fluctuation frequency seen by the output and input is the product of the switching frequency in each phase and the number of phases, thereby reducing the need for filter capacitors and reducing the current impact on the input, while speeding up the response to load changes.

[0004] In a multi-phase power supply system, the current sharing problem between phases has a great impact on the performance of the multi-phase power supply. The mismatch of delay and impedance between phases will lead to the imbalance of their steady-state current, which will lead to the reduction of overall system efficiency, temperature imbalance between phases, and false triggering of overcurrent protection. Therefore, it is necessary to adopt additional control strategies to maintain the balance of current between phases.

[0005] The current multi-phase power system to achieve multi-phase current sharing generally relies on the analog-to-digital converter (ADC) to sample the current information of each phase, and directly compare the current information with the overall average current information to generate the current information difference of each phase, and use this current information difference to control the conduction time of each phase to achieve multi-phase current sharing. The current sharing speed of this circuit design is often limited by the ADC sampling rate, and as the requirements for dynamic response capabilities of high-performance digital chips become higher and higher, the load jump becomes more severe. Therefore, the traditional current sharing control solution cannot meet new application requirements due to its slow control speed. Summary of the invention

[0006] In view of the above problems, an object of the present invention is to provide a multi-phase power supply and a control circuit and a control method thereof, so as to improve the speed of current balancing while satisfying the current balancing accuracy.

[0007] According to one aspect of the present invention, a control circuit of a multi-phase power supply is provided, the multi-phase power supply includes N-phase power conversion circuits, N is an integer greater than 1, wherein the control circuit includes: a current reference module, used to obtain a current reference signal according to a current sampling signal of a first-phase power conversion circuit in the N-phase power conversion circuits; an on-time adjustment module, used to compare the current sampling signals of the N-phase power conversion circuits with the current reference signals, and obtain a plurality of on-time control signals according to the comparison results and pulse width modulation signals of the second-phase to N-phase power conversion circuits, the plurality of on-time control signals respectively controlling the on-time of the second-phase to N-phase power conversion circuits; and a control module, used to obtain the pulse width modulation signals of the next cycle of the second-phase to N-phase power conversion circuits according to the plurality of on-time control signals.

[0008] Optionally, average values ​​of output currents of the N-phase power conversion circuits are equal.

[0009] Optionally, the on-time adjustment module is further configured to compare the current sampling signal of the first-phase power conversion circuit with the current reference signal, and provide a first bias control signal to the current reference module according to the comparison result.

[0010] Optionally, the on-time adjustment module includes: multiple comparison units and multiple current sharing control units corresponding one by one to the N-phase power conversion circuits, wherein each comparison unit is used to compare the current sampling signal of the corresponding phase power conversion circuit with the current reference signal to obtain a comparison signal, and each current sharing control unit counts the corresponding comparison signal and obtains a first count value, wherein the current sharing control unit corresponding to the first phase power conversion circuit among the multiple current sharing control units is used to generate the first bias control signal according to the first count value, and the multiple current sharing control units corresponding to the second to Nth phase power conversion circuits among the multiple current sharing control units are used to generate the on-time control signal according to the first count value.

[0011] Optionally, the multiple current sharing control units corresponding to the 2nd to Nth phase power conversion circuits are also used to increase the conduction time of the corresponding phase power conversion circuit when the first count value is a positive value, and to reduce the conduction time of the corresponding phase power conversion circuit when the first count value is a negative value.

[0012] Optionally, the current equalization control unit corresponding to the first phase power conversion circuit is used to generate the first bias control signal according to the first count value, so as to adjust the current reference signal in real time so that the current reference signal gradually approaches the cycle-by-cycle current average value of the first phase power conversion circuit.

[0013] Optionally, each current sharing control unit is also used to receive a pulse width modulation signal of the corresponding phase power conversion circuit, and count the received comparison signal after the falling edge of the pulse width modulation signal arrives and a second preset time has passed, and stop counting when the rising edge of the pulse width modulation signal arrives.

[0014] Optionally, each current sharing control unit is used to count forward when the comparison signal is at the second level and increase the first count value, and to count backward when the comparison signal is at the first level and decrease the first count value.

[0015] Optionally, each current sharing control unit is further configured to clear the first count value to zero when the falling edge of the pulse width modulation signal arrives, and start counting after the second preset time.

[0016] Optionally, each comparison unit includes: a comparator, whose non-phase input terminal is used to receive the current reference signal, whose inverting input terminal is used to receive the current sampling signal of the corresponding phase power conversion circuit, and whose output terminal is used to output a comparison signal; and a first current source connected in series between the power supply voltage and the inverting input terminal of the comparator, the first current source being used to apply a second bias voltage to the inverting input terminal of the comparator according to a second bias control signal.

[0017] Optionally, the first current source is a bidirectional current source, and the second bias control signal is used to control the positive or negative of the second bias voltage.

[0018] Optionally, the current reference module includes: a valley sampling module, used to obtain a valley detection signal based on a sampling control signal and a current sampling signal of the first phase power conversion circuit; a first bias module, used to provide a first bias voltage, and superimpose the first bias voltage with the valley detection signal to obtain the current reference signal.

[0019] Optionally, the valley sampling module is configured to sample the current sampling signal of the first-phase power conversion circuit when the sampling control signal is at a first level, and to maintain the valley detection signal when the sampling control signal is at a second level.

[0020] Optionally, the sampling control signal jumps from the first level to the second level when the rising edge of the pulse width modulation signal of the first phase power conversion circuit arrives, and jumps from the second level to the first level after the falling edge of the pulse width modulation signal of the first phase power conversion circuit arrives and a first preset time has passed.

[0021] Optionally, the valley sampling module includes: a first switch, whose first end is used to receive the current sampling signal of the first phase power conversion circuit; a first capacitor, whose first end is connected to the second end of the first switch, and the second end is connected to the ground; a second switch, whose first end is connected to the second end of the first switch; a second capacitor, whose first end is connected to the second end of the second switch, and the second end is connected to the ground; an operational amplifier, whose non-phase input end is connected to the second end of the second switch, whose inverting input end is short-circuited with the output end, and whose output end is used to output the valley detection signal, wherein the first switch is controlled by the first switch signal, the second switch is controlled by the second switch signal, and the first switch signal is in phase with the sampling control signal, and the second switch signal is in phase with the sampling control signal.

[0022] Optionally, the first bias module includes: a first current source, used to provide a first bias current according to the first bias control signal; and a first resistor, wherein a first end of the first resistor is connected to the valley detection signal, a second end of the first resistor is connected to the first current source, and an intermediate node between the two is used to output the current reference signal.

[0023] Optionally, each current sharing control unit includes: a shielding control module, which is used to generate the sampling control signal according to the pulse width modulation signal of the corresponding phase power conversion circuit, a clock signal and a delay signal for setting the second preset time; a counting module, which is used to receive the sampling control signal, the second level time of the sampling control signal is the sum of the pulse width of the pulse width modulation signal and the second preset time, wherein the counting module shields the counting during the second level period of the sampling control signal, and counts the corresponding comparison signal during the first level period of the sampling control signal to obtain a first counting value; and an operation module, which is used to calculate the first counting value according to the pulse width modulation signal of the corresponding phase power conversion circuit to obtain the first bias control signal or the conduction time control signal, wherein the sampling control signal jumps to the first level when the falling edge of the pulse width modulation signal arrives and after the second preset time, and changes to the second level when the rising edge of the pulse width modulation signal arrives.

[0024] Optionally, the operation module is used to perform proportional-integral calculation on the first count value to obtain the first bias control signal or the on-time control signal.

[0025] Optionally, the operation module of the current sharing control unit corresponding to the first phase power conversion circuit includes: a first calculation module, used to calculate the first count value when the rising edge of the pulse width modulation signal of the first phase power conversion circuit arrives, so as to obtain the first bias control signal.

[0026] Optionally, the operation module of the current sharing control unit corresponding to the 2nd to Nth phase power conversion circuit includes: a second calculation unit, used to operate the first count value when the rising edge of the pulse width modulation signal of the corresponding phase power conversion circuit arrives to obtain the on-time compensation value; and an adder, used to add the on-time compensation value and the on-time normal value preset in the register to obtain the on-time control signal.

[0027] Optionally, the operation module also includes: a calculation shielding module, which is used to count the clock signal between adjacent rising edges of the pulse width modulation signal of the corresponding phase power conversion circuit to obtain a second count value, and compare the second count value with a set cycle range, wherein the calculation shielding module is used to provide a valid calculation shielding signal to the second calculation module when the second count value exceeds the cycle range to shut down the PI controller.

[0028] Optionally, the calculation shielding module is further used to receive an external hold signal, and to set the calculation shielding signal to be valid when the external hold signal is valid.

[0029] Optionally, the calculation shielding module is further used to validate the calculation shielding signal when the on-time control signal decreases to a defined on-time.

[0030] Optionally, the first calculation module and the second calculation module include PI controllers.

[0031] According to another aspect of the present invention, a multi-phase power supply is provided, comprising: the above-mentioned control circuit, and a multi-phase power conversion circuit, wherein each phase power conversion circuit comprises a driver and a switching circuit, the input end of each phase power conversion circuit receives a pulse width modulation signal output by the control circuit of the corresponding phase, the driver drives the switch tube in the switching circuit, and the output ends of the multiple switching circuits are coupled together to power the load.

[0032] According to another aspect of the present invention, a control method for a multi-phase power supply is provided, the multi-phase power supply comprising an N-phase power conversion circuit, N being an integer greater than 1, wherein the control method comprises: obtaining a current reference signal according to a current sampling signal of a first-phase power conversion circuit in the N-phase power conversion circuit; comparing the current sampling signals of the N-phase power conversion circuit with the current reference signal respectively, and obtaining a plurality of on-time control signals according to the comparison results and pulse width modulation signals of the second-phase to N-phase power conversion circuits, the plurality of on-time control signals respectively controlling the on-time of the second-phase to N-phase power conversion circuits; and obtaining the pulse width modulation signals of the next cycle of the second-phase to N-phase power conversion circuits respectively according to the plurality of on-time control signals.

[0033] Optionally, average values ​​of output currents of the N-phase power conversion circuits are equal.

[0034] Optionally, the control method further includes: comparing the current sampling signal of the first-phase power conversion circuit with the current reference signal, and generating a first bias control signal according to the comparison result, wherein the first bias control signal is used to control the magnitude of the current reference signal.

[0035] Optionally, it also includes: comparing the current sampling signal of each phase power conversion circuit with the current reference signal to obtain a comparison signal; and counting the comparison signal to obtain a first count value, and obtaining the first bias control signal according to the first count value, or the conduction time control signal of the 2nd phase to Nth phase power conversion circuit.

[0036] Optionally, the step of obtaining the on-time control signal of the 2nd phase to Nth phase power conversion circuit according to the first count value includes: when the first count value is a positive value, increasing the on-time of the corresponding phase power conversion circuit, and when the first count value is a negative value, reducing the on-time of the corresponding phase power conversion circuit.

[0037] Optionally, the step of obtaining the first bias control signal according to the first count value includes: generating the first bias control signal according to the first count value to adjust the current reference signal in real time so that the current reference signal gradually approaches the cycle-by-cycle current average value of the first-phase power conversion circuit.

[0038] Optionally, the step of counting the comparison signal to obtain a first count value includes: receiving a pulse width modulation signal of a corresponding phase power conversion circuit, and counting the received comparison signal after the falling edge of the pulse width modulation signal arrives and a second preset time has passed, and stopping counting when the rising edge of the pulse width modulation signal arrives.

[0039] Optionally, the step of counting the comparison signal to obtain a first count value further includes: counting forward when the comparison signal is at the second level and increasing the first count value, and counting backward when the comparison signal is at the first level and decreasing the first count value.

[0040] Optionally, the step of counting the comparison signal to obtain a first count value further comprises: clearing the first count value when a falling edge of the pulse width modulation signal arrives, and starting counting after the second preset time.

[0041] Optionally, the step of obtaining a current reference signal based on the current sampling signal of the first phase power conversion circuit in the N-phase power conversion circuit includes: obtaining a valley detection signal based on a sampling control signal and the current sampling signal of the first phase power conversion circuit; and providing a first bias voltage based on the first bias control signal, and superimposing the first bias voltage with the valley detection signal to obtain the current reference signal.

[0042] Optionally, the step of obtaining a valley detection signal based on a sampling control signal and a current sampling signal of the first-phase power conversion circuit includes: sampling the current sampling signal of the first-phase power conversion circuit when the sampling control signal is at a first level, and maintaining the valley detection signal when the sampling control signal is at a second level.

[0043] Optionally, the sampling control signal jumps from the first level to the second level when the rising edge of the pulse width modulation signal of the first phase power conversion circuit arrives, and jumps from the second level to the first level after the falling edge of the pulse width modulation signal of the first phase power conversion circuit arrives and a first preset time has passed.

[0044] Optionally, the control method also includes: generating a sampling control signal according to a pulse width modulation signal of a corresponding phase power conversion circuit, a clock signal, and a delay signal for setting the second preset time, wherein the second level time of the sampling control signal is the sum of the pulse width of the pulse width modulation signal and the second preset time; counting the corresponding comparison signal when the sampling control signal is at a first level to obtain the first count value; and calculating the first count value according to the pulse width modulation signal of the corresponding phase power conversion circuit to obtain the first bias control signal or the on-time control signal, wherein the sampling control signal jumps to the first level when the falling edge of the pulse width modulation signal arrives and after the second preset time has passed, and changes to the second level when the rising edge of the pulse width modulation signal arrives.

[0045] Optionally, the calculation process of calculating the first count value according to the pulse width modulation signal of the corresponding phase power conversion circuit is a proportional-integral calculation.

[0046] Optionally, the step of calculating the first count value according to the pulse width modulation signal of the corresponding phase power conversion circuit to obtain the first bias control signal or the on-time control signal also includes: counting the clock signal between adjacent rising edges of the pulse width modulation signal of the corresponding phase power conversion circuit to obtain a second count value, and comparing the second count value with a set cycle range; and generating a valid calculation masking signal when the second count value exceeds the cycle range.

[0047] Optionally, the step of calculating the first count value according to the pulse width modulation signal of the corresponding phase power conversion circuit to obtain the first bias control signal or the on-time control signal also includes: receiving an external hold signal and setting the calculation shielding signal to valid when the external hold signal is valid.

[0048] Optionally, the step of calculating the first count value according to the pulse width modulation signal of the corresponding phase power conversion circuit to obtain the first bias control signal or the on-time control signal also includes: when the on-time control signal is reduced to a limited on-time, setting the calculation shielding signal to valid.

[0049] The control circuit of the multi-phase power supply provided in the embodiment of the present invention obtains a current reference signal by sampling the inductor current of the first phase power conversion circuit in the multi-phase power supply, and then compares the real-time current sampling signal of the second phase to the Nth phase power conversion circuit with the current reference signal, and generates a conduction time control signal of the second phase to the Nth phase power conversion circuit according to the comparison result. The conduction time control signal can control the switching duty cycle of the corresponding phase power conversion circuit, thereby realizing multi-phase current sharing control, which has the advantages of simple design, low cost and fast current sharing speed, and has broad application prospects.

[0050] In addition, the current reference module and the comparison unit in the control circuit of the embodiment of the present invention can be implemented by analog circuits, and the current balancing control unit and the PWM controller can be implemented by digital circuits. The positive and negative comparison signals generated by the analog circuit are counted and proportional-integral calculated by the digital circuit to obtain the on-time control signal of the power conversion circuit from the second phase to the Nth phase. Compared with the prior art, the current balancing speed will not be limited by the ADC sampling rate, and therefore can meet the application requirements of various high-performance digital chips.

[0051] In addition, the current balancing control unit of the embodiment of the present invention has periodic shielding, external hold control and minimum on-time shielding functions, which can effectively avoid the negative impact caused by continuing to apply current balancing when the current changes rapidly due to load fluctuations, etc., which is beneficial to improving the dynamic response capability of the multi-phase power supply system. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0053] Figure 1 A schematic structural diagram of a multi-phase power supply according to an embodiment of the present invention is shown;

[0054] Figure 2 A schematic circuit diagram of a current reference module according to an embodiment of the present invention is shown;

[0055] Figure 3 A schematic circuit diagram of a comparison unit according to an embodiment of the present invention is shown;

[0056] Figure 4 A schematic structural diagram of a current sharing control unit according to an embodiment of the present invention is shown;

[0057] Figure 5a A schematic structural diagram of a computing module according to a first embodiment of the present invention is shown;

[0058] Figure 5b A schematic structural diagram of a computing module according to a second embodiment of the present invention is shown;

[0059] Figure 6 A schematic waveform diagram showing a current sharing control method according to an embodiment of the present invention;

[0060] Figure 7 A waveform comparison diagram showing a current balancing control method according to an embodiment of the present invention and a current balancing control method of a conventional technology;

[0061] Figure 8 A schematic waveform diagram of the current sharing control method according to an embodiment of the present invention when periodic shielding is triggered is shown. DETAILED DESCRIPTION

[0062] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, identical elements are represented by identical or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown.

[0063] It should be understood that in the following description, "circuit" refers to a conductive loop composed of at least one element or subcircuit through electrical connection or electromagnetic connection. When an element or circuit is said to be "connected to" another element or an element / circuit is said to be "connected between" two nodes, it can be directly coupled or connected to another element or there can be an intermediate element, and the connection between the elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there is no intermediate element between the two.

[0064] It should be noted that, in this article, the switching device is a transistor that works in a switching mode to provide a current path, including one selected from a bipolar transistor or a field effect transistor. The first end and the second end of the switching device are respectively a high potential end and a low potential end on the current path, and the control end of the switching device is used to receive a drive signal to control the on and off of the transistor. In addition, in the present application, the description of the on and off of the power conversion circuit corresponds to the on and off of the main switching device that receives the input voltage in the power conversion circuit. For example, turning on the power conversion circuit corresponds to turning on the main switching device in the power conversion circuit to connect the energy storage element in the circuit to the input for charging and energy storage, and start to provide power output to the load (that is, generate a corresponding output voltage according to the input voltage); turning off the power conversion circuit corresponds to turning off the main switching device in the power conversion circuit to end the charging and energy storage state of the energy storage element in the circuit, and stop providing power output to the load.

[0065] Figure 1 A schematic structural diagram of a multi-phase power supply according to an embodiment of the present invention is shown. The multi-phase power supply according to the embodiment of the present invention comprises a control circuit of the multi-phase power supply and an N-phase power conversion circuit, where N is an integer greater than 1, and the control circuit of the multi-phase power supply is used to control the conduction sequence and charging time of the N-phase power conversion circuit to jointly provide an output voltage Vout.

[0066] Specifically, refer to Figure 1 The multi-phase power supply 100 includes N-phase parallel coupled power conversion circuits 101 - 10N (N is the number of phases set by the multi-phase power supply, and N is an integer greater than 1) and a control circuit (hereinafter referred to as the control circuit) 200 of the multi-phase power supply.

[0067] Each phase power conversion circuit includes a driver, a first switch device T1 and a second switch device T2, and an inductor Lx. The first switch device T1 and the second switch device T2 are connected between the input voltage Vin and the reference ground. The first end of the inductor Lx is connected to the middle node of the first switch device T1 and the second switch device T2, and the second end is connected to the first end of the output capacitor Cout. The second end of the output capacitor Cout is grounded. The drivers in each phase power conversion circuit 101-10N receive the control signal provided by the control circuit 200, that is, the pulse width modulation signal PWM1-PWMN, and control the conduction and shutdown of the corresponding switch device according to the received control signal, charge the energy storage element of the current phase for a corresponding time, provide output current to the output end of the N-phase power conversion circuit, output voltage Vout at the output end of the N-phase power conversion circuit, and drive the load based on the output capacitor Cout.

[0068] It should be noted that although each phase power conversion circuit can refer to Figure 1The structure of the power conversion circuit 101 in the embodiment can be understood. In this embodiment, each phase inductor corresponding to each phase power conversion circuit in the N-phase power conversion circuit 101-10N can be discrete or mutually coupled (for example, the first phase inductor is coupled with the second phase inductor; the third phase inductor is coupled with the fourth phase inductor, and so on). At the same time, although the power conversion circuit is described as having a buck topology layout (Buck), the technical solution of the present invention can be adopted for any type of layout design, such as boost, flyback, buck-boost, Cuk, Sepic and Zeta.

[0069] like Figure 1 As shown, the control circuit 200 includes a current reference module 210, a conduction time adjustment module 220 and a control module 240. The current reference module 210 is configured to obtain a current reference signal CS_ref according to a current sampling signal CS1 in the first phase power conversion circuit 101, wherein the current sampling signal CS1 represents the inductor current in the first phase power conversion circuit. The conduction time adjustment module 220 is configured to respectively compare the current sampling signals CS2-CSN of the second phase to the Nth phase power conversion circuit except the first phase power conversion circuit with the current reference signal CS_ref, and obtain a plurality of conduction time control signals Ton_ctrl according to the comparison results, wherein the conduction time control signals Ton_ctrl respectively control the conduction time (or charging time) of the second phase to the Nth phase power conversion circuit, wherein the current sampling signals CS2-CSN respectively represent the inductor current of the corresponding phase power conversion circuit. The control module 240 is configured to obtain pulse width modulation signals PWM2 -PWMN of the second to Nth phase power conversion circuits respectively according to the plurality of on-time control signals Ton_ctrl, so as to control the average value of the output current of each phase power conversion circuit to be equal.

[0070] Furthermore, the on-time adjustment module 220 is also configured to increase the on-time of the corresponding phase power conversion circuit when the average value of the current sampling signal of any working phase power conversion circuit among the 2nd to N-phase power conversion circuits is less than the current reference signal, and to reduce the on-time of the corresponding phase power conversion circuit when the average value of the current sampling signal of any working phase power conversion circuit among the 2nd to N-phase power conversion circuits is greater than the current reference signal.

[0071] Furthermore, the on-time adjustment module 220 is also configured to compare the current sampling signal CS1 of the first phase power conversion circuit with the current reference signal CS_ref, and provide a first bias control signal CS_offset to the current reference module 210 according to the comparison result, so that the current reference signal CS_ref is close to the average value of the output current of the first phase power conversion circuit.

[0072] Furthermore, each power conversion circuit of this embodiment can be implemented by a separate chip. Similarly, multiple modules in the control circuit 200 can also be integrated into the same chip.

[0073] In this embodiment, the on-time adjustment module 220 further includes a plurality of comparison units 221-22N and a plurality of current sharing control units 231-23N. It should be noted that in this embodiment, the plurality of comparison units 221-22N and the plurality of current sharing control units 231-23N and the N-phase power conversion circuits 101-10N are in a one-to-one correspondence with each other.

[0074] Among them, multiple comparison units 221-22N are respectively connected to the inductance elements of the N-phase power conversion circuits 101-10N to respectively receive the current sampling signals CS1-CSN of the corresponding phases, and compare the multiple current sampling signals CS1-CSN with the current reference signal CS_ref to obtain multiple comparison signals Cb1-CbN. Multiple current balancing control units 231-23N are connected to multiple comparison units 221-22N in a one-to-one correspondence, and are configured to count the corresponding comparison signals Cb1-CbN and obtain multiple first count values ​​Cb_counter_x (x=1, 2, ..., N). Among them, the current balancing control unit 231 is further configured to obtain the first bias control signal CS_offset according to the first count value Cb_counter_x, and the multiple current balancing control units 232-23N are further configured to obtain the conduction time control signal Ton_ctrl of the corresponding phase according to the first count value Cb_counter_x.

[0075] Furthermore, the multiple current sharing control units 231-23N in this embodiment are also used to receive the pulse width modulation signal PWMx (x=1, 2, ..., N) of the corresponding phase power conversion circuit, and clear and reset the first count value Cb_counter_x previously counted when the falling edge of the pulse width modulation signal PWMx arrives, and then restart counting the received comparison signal Cbx (x=1, 2, ..., N) after a second preset time, and stop counting the comparison signal Cbx and maintain the first count value Cb_counter_x when the rising edge of the pulse width modulation signal arrives.

[0076] Furthermore, the multiple current sharing control units 231-23N in this embodiment are also used to count forward or backward according to the high and low levels of the received comparison signal Cbx. For example, when the comparison signal Cbx is at a high level (e.g., logic "1"), the current sharing control unit counts forward and increases the first count value Cb_counter_x; when the comparison signal Cbx is at a low level (e.g., logic "0"), the current sharing control unit counts backward and decreases the first count value Cb_counter_x.

[0077] In this embodiment, for the 2nd to Nth phase power conversion circuits, the polarity and amplitude of the first count value Cb_counter_x can reflect the difference between the cycle-by-cycle average value of the inductor current of the working phase power conversion circuit and the reference current signal. If the first count value Cb_counter_x is a positive value, it indicates that the average value of the inductor current of the working phase power conversion circuit is less than the current reference signal CS_ref, thereby increasing the on-time or charging time of the corresponding phase power conversion circuit; if the first count value Cb_counter_x is a negative value, it indicates that the average value of the inductor current of the working phase power conversion circuit is greater than the current reference signal CS_ref, thereby reducing the on-time or charging time of the corresponding phase power conversion circuit.

[0078] For the first-phase power conversion circuit, the polarity and amplitude of the first count value Cb_counter_x corresponding to the first-phase power conversion circuit can reflect the difference between the cycle-by-cycle average value of the inductor current of the first-phase power conversion circuit and the reference current signal. In order to make the reference current signal equal to the cycle-by-cycle average value of the inductor current of the first-phase power conversion circuit, the current sharing control unit 231 performs proportional-integral calculation on the obtained first count value Cb_counter_x to obtain the first offset control signal CS_offset, so as to adjust the value of the current reference signal CS_ref in real time, so that the current reference signal CS_ref gradually approaches the cycle-by-cycle current average value of the first-phase power conversion circuit 101.

[0079] Further, the control module 240 of the present embodiment includes a plurality of PWM controllers 241-24N. It should be noted that the plurality of PWM controllers 241-24N in the present embodiment correspond one to one with the plurality of power conversion circuits 101-10N. Among them, the PWM controller 241 is used to generate a pulse width modulation signal PWM1 of the first phase power conversion circuit 101, and the PWM controllers 242-24N are used to generate pulse width modulation signals PWM2-PWMN of the second phase to the Nth phase power conversion circuits 102-10N according to the received on-time control signal Ton_ctrl. It should be noted that the plurality of PWM controllers 241-24N and the manner in which they generate pulse width modulation signals PWM1-PWMN are conventional technical means in the art and will not be described in detail herein.

[0080] Figure 2 A schematic circuit diagram of a current reference module 301 according to an embodiment of the present invention is shown. In an exemplary embodiment, the current reference module 301 includes a valley sampling module 311 and a first bias module 312. The valley sampling module 311 is configured to sample the current sampling signal CS1 representing the inductor current of the first phase power conversion circuit 101 before the rising edge of the pulse width modulation signal PWM1 of the first phase power conversion circuit 101 arrives according to the sampling control signal CS_ctrl, and obtain the valley detection signal CS1_valley. The first bias module 312 is configured to superimpose a first bias voltage on the obtained valley detection signal CS1_valley according to the first bias control signal CS_offset, and finally obtain the current reference signal CS_ref.

[0081] Specifically, the valley sampling module 311 includes inverters INV1 and INV2, switches S1 and S2, capacitors C1 and C2, and an operational amplifier AMP. The first end of the switch S1 is used to receive the current sampling signal CS1 of the first phase power conversion circuit 101, the second end of the switch S1 is connected to the first end of the capacitor C1, the second end of the capacitor C1 is connected to the ground, the first end of the switch S2 is connected to the common node of the switch S1 and the capacitor C1, the second end of the switch S2 is connected to the first end of the capacitor C2 and the positive phase input end of the operational amplifier AMP, the second end of the capacitor C2 is connected to the ground, and the operational amplifier AMP is connected to form a follower structure, that is, the inverting input end and the output end of the operational amplifier AMP are short-circuited together, and the valley detection signal CS1_valley is provided through the output end of the operational amplifier AMP. The input end of the inverter INV1 is used to receive the sampling control signal CS_ctrl, and the output end is connected to the input end of the inverter INV2. The output end of the inverter INV1 is also used to provide a first switching signal to control the switch S1 to be turned on and off, and the output end of the inverter INV2 is used to provide a second switching signal to control the switch S2 to be turned on and off.

[0082] like Figure 2 As shown, the first switch signal is in phase with the sampling control signal CS_ctrl, and the second switch signal is in phase with the sampling control signal CS_ctrl. Therefore, before the rising edge of the pulse width modulation signal PWM1 (hereinafter referred to as the pulse width modulation signal PWM1) of the first phase power conversion circuit 101 arrives, the sampling control signal CS_ctrl is at a first level (e.g., a low level), so the switch S1 is turned on and the switch S2 is turned off, thereby converting the current sampling signal CS1 of the first phase power conversion circuit 101 from current information to voltage information and storing it on the capacitor C1. When the rising edge of the pulse width modulation signal PWM1 arrives, the sampling control signal CS_ctrl jumps from the first level (e.g., a low level) to the second level (e.g., a high level), so the switch S2 is turned on and the switch S1 is turned off, so that the current sampling signal CS1 no longer affects the voltages on the capacitors C1 and C2, and the voltage in the capacitor C1 is transferred to the capacitor C2 through the switch S2, so as to achieve the purpose of sampling the first phase inductor current information to the capacitor C2. Since the operational amplifier AMP is connected in a follower structure, the output voltage of the operational amplifier AMP follows the voltage of its non-inverting input terminal, so the valley detection signal CS1_valley is equal to the voltage on the capacitor C2. After the falling edge of the pulse width modulation signal PWM1 determined by programming arrives and the first preset time has passed, the sampling control signal CS_ctrl changes from the second level to the first level again, closing the switch S1 and opening the switch S2, so the voltage on the capacitor C2 will remain unchanged in the subsequent PWM cycle, that is, the value of the valley detection signal CS1_valley will remain unchanged in the entire current sharing cycle until the next rising edge of the pulse width modulation signal PWM1 arrives.

[0083] Specifically, the first bias module 312 includes a current source I1 and a resistor R1, wherein the current source I1 is used to provide a first bias current according to the first bias control signal CS_offset, the first end of the resistor R1 is connected to the output end of the operational amplifier AMP, the second end of the resistor R1 is connected to the current source I1, and the middle node between the two is used to output the current reference signal CS_ref. In this embodiment, an offset voltage is superimposed on the valley detection signal CS1_valley by the current source I1 controlled by the first bias control signal CS_offset to obtain the current reference signal , where R1 represents the resistance value of resistor R1, It should be noted that the signal superposition method of the present invention is not limited to the above embodiment, and those skilled in the art may also use other forms of signal superposition methods to superimpose the bias voltage on the obtained valley detection signal CS1_valley.

[0084] Figure 3 FIG. 3 is a schematic circuit diagram of a comparison unit 302 according to an embodiment of the present invention. Figure 3 The circuit structure of the comparison unit 302 shown in FIG. Figure 3 As shown, the comparison unit 302 includes a comparator COMP, a resistor R2 and a second bias module 321 .

[0085] The non-phase input terminal of the comparator COMP is used to receive the current reference signal CS_ref, the inverting input terminal is connected to the second end of the resistor R2, the first end of the resistor R2 is used to receive the current sampling signal CSx (x=1, 2, ..., N) of the power conversion circuit of the corresponding phase, and the output terminal of the comparator COMP is used to output the comparison signal Cbx (x=1, 2, ..., N).

[0086] The second bias module 321 includes a current source I2 connected in series between the power supply voltage VCC and the inverting input terminal of the comparator, wherein the current source I2 is used to apply a second bias voltage to the inverting input terminal of the comparator COMP according to the second bias control signal Offsetx (x=1, 2, ..., N). The current source I2 is a bidirectional current source, and the second bias control signal Offsetx is used to control the positive and negative of the second bias voltage. Among them, the voltage CSx_post at the inverting input terminal of the comparator COMP is used to represent the signal after the real-time inductor current of the corresponding phase power conversion circuit is converted into a voltage. The voltage CSx_post is a real-time signal, and the voltage , where R2 represents the resistance value of resistor R2, represents the voltage corresponding to the output current of the current source I2 under the control of the second bias control signal Offsetx.

[0087] Figure 4 A schematic structural diagram of a current balancing control unit 303 according to an embodiment of the present invention is shown. The multiple current balancing control units 231-23N of this embodiment can be Figure 4 The circuit structure of the current sharing control unit 303 shown in FIG. Figure 4 As shown, the current sharing control unit 303 includes a shielding control module 331 , a counting module 332 and a calculation module 333 .

[0088] Among them, the shielding control module 331 is used to receive the pulse width modulation signal PWMx (x=1, 2, ..., N), the clock signal CLK and the delay signal Delay of the corresponding phase power conversion circuit, and generate the sampling control signal CS_ctrl according to the pulse width modulation signal PWMx, the clock signal CLK and the delay signal Delay used to set the second preset time.

[0089] The counting module 332 is used for receiving the corresponding comparison signal Cbx and the sampling control signal CS_ctrl, and counting the received comparison signal Cbx when the sampling control signal CS_ctrl is at a first level (eg, a low level) to obtain the first count value Cb_counter_x.

[0090] The operation module 333 is used to perform proportional-integral calculation on the first count value Cb_counter_x according to the pulse width modulation signal PWMx of the corresponding phase power conversion circuit to obtain the first offset control signal CS_offset or the on-time control signal Ton_ctrl. For example, when the current sharing control unit 303 is used Figure 1 When the current sharing control unit 231 in the embodiment of the present invention is used, the operation module 333 is used to output the first bias control signal CS_offset; when the current sharing control unit 303 is used to Figure 1 When the current sharing control unit 232-23N is used, the operation module 333 is used to output the conduction time control signal Ton_ctrl.

[0091] Further, the shielding control module 331 is configured to set the sampling control signal CS_ctrl to a second level (e.g., a high level) when the received pulse width modulation signal PWMx is at a high level, at which time the counting module 332 stops counting the comparison signal Cbx and maintains the obtained first count value Cb_counter_x. After the falling edge of the pulse width modulation signal PWMx arrives and the second delay time set by the delay signal DelayDelay passes, the shielding control module 331 changes the sampling control signal CS_ctrl from the second level to the first level, at which time the counting module 332 starts counting the comparison signal Cbx and counts up or down according to the high or low level of the comparison signal Cbx.

[0092] Figure 5a FIG. 3 shows a schematic structural diagram of the operation module 333-1 according to the first embodiment of the present invention. Figure 5a As shown, the operation module 333-1 is applied to the current sharing control unit corresponding to the first phase power conversion circuit 101, including a first calculation module 344, and the first calculation module 344 is used to calculate the received first count value Cb_counter_x when the rising edge of the pulse width modulation signal PWM1 of the first phase power conversion circuit arrives to obtain the first bias control signal CS_offset. Further, the calculation process is, for example, a proportional-integral calculation, and the first calculation module 344 is implemented, for example, by a PI controller.

[0093] Figure 5bFIG. 3 shows a schematic structural diagram of the operation module 333-2 according to the second embodiment of the present invention. Figure 5b As shown, the operation module 333-2 is applied to the current sharing control unit corresponding to the power conversion circuit of the 2nd phase to the Nth phase, including a second calculation module 341 and an adder 343. Among them, the second calculation module 341 is used to receive the pulse width modulation signal PWMx of the corresponding phase power conversion circuit and the first count value Cb_counter_x, and when the rising edge of the pulse width modulation signal PWMx arrives, the first count value Cb_counter_x is calculated to obtain the on-time compensation value Ton_add. The adder 343 is used to add the on-time compensation value Ton_add to the on-time conventional value Ton_common preset in the register to obtain the on-time control signal Ton_ctrl. Further, the calculation process is, for example, a proportional-integral operation, and the second calculation module 341 is implemented, for example, by a PI controller.

[0094] Further, the operation module 333-2 of this embodiment further includes a calculation shielding module 342, wherein the calculation shielding module 342 includes a counter 3421, and the counter 3421 is configured to count the clock signal CLK between adjacent rising edges of the pulse width modulation signal PWMx of the corresponding phase power conversion circuit to obtain a second count value PWM_counter (not shown in the figure), and compare the second count value PWM_counter with the set cycle range Tsw_min~Tsw_max, and when the second count value PWM_counter exceeds the cycle range (for example, the second count value PWM_counter is less than the minimum cycle Tsw_min or greater than the maximum cycle Tsw_max), provide a valid (for example, high level) calculation shielding signal Blank to the PI controller 341 to turn off the PI controller, so as not to perform current sharing control. At this time, according to the needs of the application, the on-time of the power tube of the corresponding phase can be controlled according to the on-time control signal Ton_ctrl obtained last time, or the on-time of the power tube of the corresponding phase can be controlled according to the on-time common value Ton_common.

[0095] Furthermore, the current balancing control unit 303 of this embodiment also has an input pin for an external hold signal Hold. When other dynamic processes occur in the system but have little impact on the switching cycle and thus do not trigger cycle shielding, the calculation shielding module 342 can set the calculation shielding signal Blank to valid (for example, a high level) according to the provided external hold signal Hold, thereby turning off the PI controller and shielding the current balancing control function of the circuit.

[0096] Furthermore, the current sharing control unit 303 of this embodiment is also used to receive the minimum adjustment range Ton_min_abs set by the programmable register, and the calculation shielding module 342 is also used to compare the on-time defined by the on-time control signal Ton_ctrl with the minimum on-time Ton_common_min or the maximum on-time Ton_common_max defined by the minimum adjustment range Ton_min_abs, and when the on-time defined by the on-time control signal Ton_ctrl is equal to the minimum on-time Ton_common_min or the maximum on-time Ton_common_max, the calculation shielding signal Blank is set to a valid state.

[0097] Figure 6 Schematic waveform diagram of the current sharing control method according to an embodiment of the present invention is shown. Figure 6 1 and 2 respectively show the waveforms of the pulse width modulation signal PWMx, the current reference signal CS_ref, the sampling control signal CS_ctrl, the first count value Cb_counter_x and the on-time control signal Ton_ctrl of a certain phase power conversion circuit. Figures 2 to 6 The principle of the current sharing control method provided in the embodiment of the present invention is explained.

[0098] like Figure 6 As shown, when the pulse width modulation signal PWMx of a certain phase power conversion circuit is at a high level, the sampling control signal CS_ctrl is at a high level, and the counting module 332 does not count the received comparison signal, that is, the counting is shielded during the period when the sampling control signal is at a high level, and the first count value Cb_counter_x remains at the previously obtained value. When the falling edge of the pulse width modulation signal PWMx flips from a high level to a low level arrives, the counting module 332 clears and resets the first count value Cb_counter_x, and after the second preset time set by the delay signal Delay, the sampling control signal CS_ctrl flips to a low level, at which time the counting module 332 starts to count the comparison signal Cbx, and increases or decreases the first count value Cb_counter_x according to the positive / negative of the comparison signal Cbx. When the next rising edge of the pulse width modulation signal PWMx arrives, the counting module 332 stops counting again and maintains the value of the first counting value Cb_counter_x, and repeats the above cycle. After multiple cycles of adjustment, the purpose of adjusting the output current to a balanced state by adjusting the rising time of the inductor current of this phase is achieved.

[0099] Figure 7 A waveform comparison diagram of the current balancing control method according to an embodiment of the present invention and the current balancing control method of the conventional technology is shown. Figure 7In FIG. 1 , Ia and Ib respectively represent the current regulation effects of the current balancing control method of the embodiment of the present invention and the current balancing control method of the conventional technology, Ton_ctrl is the change waveform of the on-time control signal obtained by the embodiment of the present invention, Cs_ad is the change waveform of the sampling value obtained by the conventional technology after analog-to-digital conversion of the current, and Ton_ctrl_ad is the change waveform of the on-time control signal obtained by the conventional technology. Figure 7 As shown, the current balancing control method of the embodiment of the present invention can achieve a cycle-by-cycle current adjustment effect, while the current balancing control method of the traditional technology can only adjust the current once every 2 cycles even in the best case, and the adjustment speed is also slower.

[0100] Figure 8 A schematic waveform diagram of the current sharing control method according to an embodiment of the present invention when periodic shielding is triggered is shown. Figure 8 , respectively, shows the waveforms of the pulse width modulation signal PWMx, the clock signal CLK, the second count value PWM_counter, the calculation shielding signal Blank, the sampling control signal CS_ctrl, the first count value Cb_counter_x, and the on-time control signal Ton_ctrl of a certain phase power conversion circuit. Among them, the principle of controlling the counting process of the comparison signal Cbx by the sampling control signal CS_ctrl has been explained in the above embodiment and will not be repeated here. Assuming that the minimum period Tsw_min defined by the set period range is 80, as Figure 8 As shown, when the second count value PWM_counter between adjacent rising edges of the pulse width modulation signal PWMx is equal to 62, which is less than the minimum period of the set period range, the calculation shielding module 342 provides a high-level calculation shielding signal Blank to the PI controller 341 to turn off the PI controller 341. At this time, the value of the on-time control signal Ton_ctrl is equal to the value of the on-time normal value Ton_common (for example, Ton_ctrl=12).

[0101] To summarize, the control circuit of the multi-phase power supply provided in the embodiment of the present invention obtains a current reference signal by sampling the inductor current of the first phase power conversion circuit in the multi-phase power supply, and then compares the real-time current sampling signal of the second phase to the Nth phase power conversion circuit with the current reference signal, and generates a conduction time control signal of the second phase to the Nth phase power conversion circuit according to the comparison result. The conduction time control signal can control the switching duty cycle of the corresponding phase power conversion circuit, thereby realizing multi-phase current sharing control, which has the advantages of simple design, low cost, and fast current sharing speed, and has broad application prospects.

[0102] In addition, the current reference module and the comparison unit in the control circuit of the embodiment of the present invention can be implemented by analog circuits, and the current balancing control unit and the PWM controller can be implemented by digital circuits. The positive and negative comparison signals generated by the analog circuit are counted and proportional-integral calculated by the digital circuit to obtain the on-time control signal of the power conversion circuit from the second phase to the Nth phase. Compared with the prior art, the current balancing speed will not be limited by the ADC sampling rate, and therefore can meet the application requirements of various high-performance digital chips.

[0103] In addition, the current balancing control unit of the embodiment of the present invention has periodic shielding, external hold control and minimum on-time shielding functions, which can effectively avoid the negative impact caused by continuing to apply current balancing when the current changes rapidly due to load fluctuations, etc., which is beneficial to improving the dynamic response capability of the multi-phase power supply system.

[0104] In the above description, the well-known structural elements and steps are not described in detail. However, it should be understood by those skilled in the art that the corresponding structural elements and steps can be realized by various technical means. In addition, in order to form the same structural elements, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although each embodiment is described above respectively, this does not mean that the measures in each embodiment cannot be advantageously used in combination.

[0105] According to the embodiments of the present invention, as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to specific embodiments. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The scope of protection of the present invention shall be based on the scope defined by the claims of the present invention.

Claims

1. A control circuit of a multi-phase power supply, the multi-phase power supply comprising an N-phase power conversion circuit, N being an integer greater than 1, wherein: The control circuit comprises: A current reference module, used for obtaining a current reference signal according to a current sampling signal of a first-phase power conversion circuit in the N-phase power conversion circuit; a conduction time adjustment module, used to compare the current sampling signals of the N-phase power conversion circuit with the current reference signal respectively, and obtain a plurality of conduction time control signals according to the comparison results and the pulse width modulation signals of the second-phase to the N-phase power conversion circuit, wherein the plurality of conduction time control signals respectively control the conduction time of the second-phase to the N-phase power conversion circuit; and A control module is used to obtain the pulse width modulation signal of the next cycle of the second phase to the Nth phase power conversion circuit according to the multiple conduction time control signals.

2. The control circuit according to claim 1, wherein: The average values ​​of the output currents of the N-phase power conversion circuits are equal.

3. The control circuit according to claim 1, wherein: The on-time adjustment module is further used for comparing the current sampling signal of the first-phase power conversion circuit with the current reference signal, and providing a first bias control signal to the current reference module according to the comparison result.

4. The control circuit according to claim 3, wherein: The on-time adjustment module comprises: a plurality of comparison units and a plurality of current sharing control units corresponding one by one to the N-phase power conversion circuits, Each comparison unit is used to compare the current sampling signal of the corresponding phase power conversion circuit with the current reference signal to obtain a comparison signal. Each current sharing control unit counts the corresponding comparison signal and obtains a first count value. Among them, the current balancing control unit corresponding to the first phase power conversion circuit among the multiple current balancing control units is used to generate the first bias control signal according to the first count value, and the multiple current balancing control units corresponding to the second phase to the Nth phase power conversion circuits among the multiple current balancing control units are used to generate the on-time control signal according to the first count value.

5. The control circuit according to claim 4, wherein: The multiple current sharing control units corresponding to the 2nd to Nth phase power conversion circuits are also used to increase the conduction time of the corresponding phase power conversion circuit when the first count value is a positive value, and to reduce the conduction time of the corresponding phase power conversion circuit when the first count value is a negative value.

6. The control circuit according to claim 4, wherein: The current sharing control unit corresponding to the first phase power conversion circuit is used to generate the first bias control signal according to the first count value to adjust the current reference signal in real time so that the current reference signal gradually approaches the cycle-by-cycle current average value of the first phase power conversion circuit.

7. The control circuit according to claim 4, wherein: Each current sharing control unit is also used to receive a pulse width modulation signal of a corresponding phase power conversion circuit, and count the received comparison signal after the falling edge of the pulse width modulation signal arrives and a second preset time has passed, and stop counting when the rising edge of the pulse width modulation signal arrives.

8. The control circuit according to claim 4, wherein: Each current sharing control unit is used for forward counting when the comparison signal is at the second level and causing the first count value to increase, and for reverse counting when the comparison signal is at the first level and causing the first count value to decrease.

9. The control circuit according to claim 7, wherein: Each current sharing control unit is further configured to clear the first count value to zero when the falling edge of the pulse width modulation signal arrives, and start counting after the second preset time.

10. The control circuit according to claim 4, wherein: Each comparison unit includes: a comparator, whose non-phase input terminal is used to receive the current reference signal, whose inverting input terminal is used to receive the current sampling signal of the corresponding phase power conversion circuit, and whose output terminal is used to output a comparison signal; and A first current source is connected in series between a power supply voltage and an inverting input terminal of the comparator, wherein the first current source is used to apply a second bias voltage to the inverting input terminal of the comparator according to a second bias control signal.

11. The control circuit according to claim 10, wherein: The first current source is a bidirectional current source, and the second bias control signal is used to control the positive and negative of the second bias voltage.

12. The control circuit according to claim 3, wherein: The current reference module comprises: A valley sampling module, used for obtaining a valley detection signal according to a sampling control signal and a current sampling signal of the first phase power conversion circuit; The first bias module is used to provide a first bias voltage, and superimpose the first bias voltage with the valley detection signal to obtain the current reference signal.

13. The control circuit according to claim 12, wherein: The valley sampling module is configured to sample the current sampling signal of the first-phase power conversion circuit when the sampling control signal is at a first level, and to maintain the valley detection signal when the sampling control signal is at a second level.

14. The control circuit according to claim 13, wherein: The sampling control signal jumps from the first level to the second level when the rising edge of the pulse width modulation signal of the first phase power conversion circuit arrives, and jumps from the second level to the first level after the falling edge of the pulse width modulation signal of the first phase power conversion circuit arrives and a first preset time has passed.

15. The control circuit according to claim 12, wherein: The valley sampling module comprises: A first switch, a first end of which is used to receive a current sampling signal of the first-phase power conversion circuit; a first capacitor, a first end of which is connected to the second end of the first switch, and a second end of which is connected to the ground; a second switch, a first end of which is connected to the second end of the first switch; a second capacitor, a first end of which is connected to the second end of the second switch, and a second end of which is connected to ground; an operational amplifier, wherein the non-inverting input terminal is connected to the second end of the second switch, the inverting input terminal is short-circuited with the output terminal, and the output terminal is used to output the valley detection signal, The first switch is controlled by a first switch signal, the second switch is controlled by a second switch signal, the first switch signal is in anti-phase with the sampling control signal, and the second switch signal is in phase with the sampling control signal.

16. The control circuit according to claim 12, wherein: The first bias module comprises: a first current source, configured to provide a first bias current according to the first bias control signal; and A first resistor, wherein a first end of the first resistor is connected to the valley detection signal, a second end of the first resistor is connected to the first current source, and an intermediate node between the two is used to output the current reference signal.

17. The control circuit according to claim 9, wherein: Each current sharing control unit includes: A shielding control module, used for generating the sampling control signal according to a pulse width modulation signal of a corresponding phase power conversion circuit, a clock signal and a delay signal for setting the second preset time; a counting module, configured to receive the sampling control signal, wherein the second level time of the sampling control signal is the sum of the pulse width of the pulse width modulation signal and a second preset time, wherein the counting module shields counting during the second level period of the sampling control signal, and counts the corresponding comparison signal during the first level period of the sampling control signal to obtain a first count value; and a calculation module, configured to calculate the first count value according to the pulse width modulation signal of the corresponding phase power conversion circuit to obtain the first bias control signal or the conduction time control signal, The sampling control signal changes to the first level when the falling edge of the pulse width modulation signal arrives and after a second preset time has passed, and changes to the second level when the rising edge of the pulse width modulation signal arrives.

18. The control circuit according to claim 17, wherein: The operation module is used to perform proportional-integral calculation on the first count value to obtain the first bias control signal or the on-time control signal.

19. The control circuit according to claim 18, wherein: The computing module of the current sharing control unit corresponding to the first phase power conversion circuit includes: The first calculation module is used to calculate the first count value when the rising edge of the pulse width modulation signal of the first phase power conversion circuit arrives, so as to obtain the first bias control signal.

20. The control circuit according to claim 19, wherein: The computing module of the current sharing control unit corresponding to the second phase to the Nth phase power conversion circuit includes: a second calculation unit, configured to calculate the first count value when a rising edge of a pulse width modulation signal of a corresponding phase power conversion circuit arrives, so as to obtain a conduction time compensation value; and An adder is used to add the on-time compensation value to the on-time normal value preset in the register to obtain the on-time control signal.

21. The control circuit according to claim 20, wherein: The operation module also includes: a calculation shielding module, used for counting the clock signal between adjacent rising edges of the pulse width modulation signal of the corresponding phase power conversion circuit to obtain a second count value, and comparing the second count value with a set period range, The calculation shielding module is used to provide a valid calculation shielding signal to the second calculation module when the second count value exceeds the period range, so as to shut down the PI controller.

22. The control circuit according to claim 21, wherein: The calculation shielding module is further used to receive an external holding signal, and to set the calculation shielding signal to be valid when the external holding signal is valid.

23. The control circuit according to claim 21, wherein: The calculation shielding module is further used to enable the calculation shielding signal when the on-time control signal decreases to a limited on-time (Ton-min-abs).

24. The control circuit according to claim 20, wherein: The first calculation module and the second calculation module include PI controllers.

25. A multi-phase power supply, characterized in that: include: The control circuit according to any one of claims 1 to 24, and A multi-phase power conversion circuit, wherein each phase power conversion circuit includes a driver and a switching circuit, the input end of each phase power conversion circuit receives a pulse width modulation signal output by a control circuit of the corresponding phase, the driver drives the switch tube in the switching circuit, and the output ends of multiple switching circuits are coupled together to power the load.

26. A control method for a multi-phase power supply, the multi-phase power supply comprising an N-phase power conversion circuit, N being an integer greater than 1, wherein: The control method comprises: Obtaining a current reference signal according to a current sampling signal of a first-phase power conversion circuit in the N-phase power conversion circuit; Respectively comparing the current sampling signals of the N-phase power conversion circuit with the current reference signal, and obtaining a plurality of on-time control signals according to the comparison results and the pulse width modulation signals of the second-phase to the N-phase power conversion circuits, wherein the plurality of on-time control signals respectively control the on-times of the second-phase to the N-phase power conversion circuits; and The pulse width modulation signals of the next cycle of the second-phase to N-phase power conversion circuits are respectively obtained according to the multiple conduction time control signals.

27. The control method according to claim 26, wherein: The average values ​​of the output currents of the N-phase power conversion circuits are equal.

28. The control method according to claim 26, wherein: It also includes: comparing the current sampling signal of the first-phase power conversion circuit with the current reference signal, and generating a first bias control signal according to the comparison result, wherein the first bias control signal is used to control the magnitude of the current reference signal.

29. The control method according to claim 28, wherein: Also includes: Comparing the current sampling signal of each phase power conversion circuit with the current reference signal to obtain a comparison signal; as well as The comparison signal is counted to obtain a first count value, and the first bias control signal or the on-time control signal of the second-phase to N-phase power conversion circuit is obtained according to the first count value.

30. The control method according to claim 29, wherein: The step of obtaining the on-time control signal of the second-phase to N-phase power conversion circuit according to the first count value comprises: When the first count value is a positive value, increasing the on-time of the corresponding phase power conversion circuit, and When the first count value is a negative value, the on-time of the corresponding phase power conversion circuit is reduced.

31. The control method according to claim 29, wherein: The step of obtaining the first bias control signal according to the first count value comprises: The first bias control signal is generated according to the first count value to adjust the current reference signal in real time so that the current reference signal gradually approaches the cycle-by-cycle current average value of the first-phase power conversion circuit.

32. The control method according to claim 29, wherein: The step of counting the comparison signal to obtain a first count value comprises: A pulse width modulation signal of a corresponding phase power conversion circuit is received, and after a falling edge of the pulse width modulation signal arrives and a second preset time has passed, the received comparison signal is counted, and the counting is stopped when a rising edge of the pulse width modulation signal arrives.

33. The control method according to claim 29, wherein: The step of counting the comparison signal to obtain a first count value further comprises: When the comparison signal is at the second level, the counting is performed in a positive direction, and the first count value is incremented; and when the comparison signal is at the first level, the counting is performed in a negative direction, and the first count value is decremented.

34. The control method according to claim 32, wherein: The step of counting the comparison signal to obtain a first count value further comprises: When the falling edge of the pulse width modulation signal arrives, the first count value is cleared to zero, and counting starts after the second preset time.

35. The control method according to claim 28, wherein: The step of obtaining a current reference signal according to a current sampling signal of a first-phase power conversion circuit in the N-phase power conversion circuit comprises: Obtaining a valley detection signal according to a sampling control signal and a current sampling signal of the first phase power conversion circuit; and A first bias voltage is provided according to the first bias control signal, and the first bias voltage is superimposed on the valley detection signal to obtain the current reference signal.

36. The control method according to claim 35, wherein: The step of obtaining a valley detection signal according to the sampling control signal and the current sampling signal of the first phase power conversion circuit comprises: The current sampling signal of the first-phase power conversion circuit is sampled when the sampling control signal is at a first level, and the valley detection signal is maintained when the sampling control signal is at a second level.

37. The control method according to claim 36, wherein: The sampling control signal jumps from the first level to the second level when the rising edge of the pulse width modulation signal of the first phase power conversion circuit arrives, and jumps from the second level to the first level after the falling edge of the pulse width modulation signal of the first phase power conversion circuit arrives and a first preset time has passed.

38. The control method according to claim 34, wherein: Also includes: Generate a sampling control signal according to the pulse width modulation signal of the corresponding phase power conversion circuit, the clock signal and the delay signal for setting the second preset time, wherein the second level time of the sampling control signal is the sum of the pulse width of the pulse width modulation signal and the second preset time; When the sampling control signal is at a first level, counting the corresponding comparison signal to obtain the first count value; and The first count value is calculated according to the pulse width modulation signal of the corresponding phase power conversion circuit to obtain the first bias control signal or the conduction time control signal, The sampling control signal changes to the first level when the falling edge of the pulse width modulation signal arrives and after a second preset time has passed, and changes to the second level when the rising edge of the pulse width modulation signal arrives.

39. The control method according to claim 38, wherein: The calculation process of calculating the first count value according to the pulse width modulation signal of the corresponding phase power conversion circuit is a proportional-integral calculation.

40. The control method according to claim 38, wherein: The step of calculating the first count value according to the pulse width modulation signal of the corresponding phase power conversion circuit to obtain the first bias control signal or the on-time control signal also includes: Counting the clock signal between adjacent rising edges of the pulse width modulation signal of the corresponding phase power conversion circuit to obtain a second count value, and comparing the second count value with a set cycle range; and An active calculation mask signal is generated when the second count value exceeds the period range.

41. The control method according to claim 40, wherein: The step of calculating the first count value according to the pulse width modulation signal of the corresponding phase power conversion circuit to obtain the first bias control signal or the on-time control signal also includes: An external hold signal is received, and the calculation mask signal is set to be valid when the external hold signal is valid.

42. The control method according to claim 40, wherein: The step of calculating the first count value according to the pulse width modulation signal of the corresponding phase power conversion circuit to obtain the first bias control signal or the on-time control signal also includes: When the on-time control signal decreases to a defined on-time, the calculation mask signal is enabled.

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