Storage device and manufacturing method thereof

Abstract

The invention belongs to the technical field of semiconductors, and particularly relates to a storage device and a manufacturing method thereof.The storage device comprises a reading transistor and a writing transistor, the reading transistor comprises a first grid electrode, a first grid dielectric layer, a first channel, a first drain electrode and a first source electrode, and the first channel is at least formed in a partial region of the side wall of an accommodating hole; the first drain electrode and the first source electrode are both connected with the first channel, the first gate dielectric layer at least covers the first channel, and the first gate electrode is formed in the containing hole and located on the side, away from the first channel, of the first gate dielectric layer; the write transistor comprises a second channel and a second source electrode, the second channel is at least partially located in the containing hole, and the second source electrode is connected with the second channel. And the channels of the reading transistor and the writing transistor are in the same accommodating hole, so that compared with a memory cell connected by thin film transistors of two horizontal channels on the same plane, the occupied area of the memory cell is reduced, and the integration density of the transistors is improved.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and specifically relates to a storage device and a manufacturing method thereof. Background Art

[0002] The common dynamic random access memory (DRAM) storage unit is a MOS (Metal Oxide Semiconductor) transistor drain connected to a capacitor. This storage unit needs to constantly refresh the charge in the capacitor to ensure that the data is not lost, and the charge in the capacitor needs to be released when reading, and then rewritten after the reading is completed, which consumes a lot of power. At the same time, due to the large area occupied by the capacitor, miniaturization becomes a problem.

[0003] The 2Transistor 0Capacitor (2T0C) DRAM uses two MOS transistors as storage units, where the drain of one transistor is connected to the gate of the other transistor, and uses the gate capacitance to store charge and change the transistor transconductance to store information.

[0004] The existing dynamic random access memory based on 2T0C storage unit generally uses two thin film transistors (TFT) with horizontal channels on the same plane to connect, which occupies a large area and has a low integration density. Summary of the invention

[0005] The purpose of the present application is to provide a storage device and a manufacturing method thereof, so as to reduce the occupied area of ​​the storage unit and improve the integration density of the dynamic random access memory.

[0006] In order to achieve the above object, the present application provides a storage unit, including a substrate and at least one storage device layer arranged on the substrate, wherein the storage device layer includes:

[0007] The insulating layer comprises a first insulating layer and a second insulating layer which are stacked in a vertical direction;

[0008] At least one storage unit, the storage unit includes a read transistor and a write transistor, the read transistor includes a first gate, a first gate dielectric layer, a first channel, a first drain and a first source, the first insulating layer is provided with a receiving hole on a side close to the second insulating layer, the first channel is formed at least in a partial area of ​​a sidewall of the receiving hole, the first drain and the first source are arranged outside the receiving hole with intervals, the first drain is located on a side of the first source away from the second insulating layer, the first drain and the first source are both connected to the first channel, the first gate dielectric layer at least covers the first channel, and the first gate is formed in the receiving hole and is located on a side of the first gate dielectric layer away from the first channel;

[0009] The write transistor includes a second gate, a second gate dielectric layer, a second channel and a second source, the second channel is at least partially located in the accommodating hole, the drain end of the second channel is connected to the first gate, the second source is connected to the second channel, the second gate is formed on the side of the second channel away from the first gate dielectric layer, and the second gate dielectric layer is formed between the second gate and the second channel.

[0010] Optionally, an upper surface of the first gate electrode close to the second insulating layer is located between an upper surface of the first insulating layer close to the second insulating layer and a lower surface of the first source electrode away from the second insulating layer.

[0011] Optionally, the orthographic projection of the accommodating hole on the substrate is located within the orthographic projection of the first drain on the substrate, the orthographic projection of the accommodating hole on the substrate is located within the orthographic projection of the first source on the substrate, and the orthographic projection of the accommodating hole on the substrate is located within the orthographic projection of the second source on the substrate, the first channel surrounds the first gate, the second gate is at least partially located in the accommodating hole, and at least a portion of the second channel surrounds the portion of the second gate located in the accommodating hole.

[0012] Optionally, the storage device layer includes a first channel layer and an isolation portion, the first channel layer is formed on the entire side wall of the accommodating hole, the first channel layer includes the first channel and an extension portion, the surface of the first source close to the second insulating layer is the upper surface of the first source, the first channel is located on the side of the upper surface of the first source away from the second insulating layer, the extension portion is located on the side of the upper surface of the first source close to the second insulating layer, the upper surface of the extension portion close to the second insulating layer is flush with or spaced from the upper surface of the first insulating layer close to the second insulating layer, and the isolation portion is formed between the extension portion and the second channel.

[0013] Optionally, the storage unit further includes a dielectric portion, the dielectric portion is formed in the accommodating hole and is located on a side of the first gate close to the second insulating layer, the dielectric portion has a first via hole, and the second channel passes through the first via hole and is connected to the first gate; and / or

[0014] The first gate dielectric layer also covers the extension portion, and the isolation portion includes a portion of the first gate dielectric layer covering the extension portion;

[0015] Wherein, when the isolation portion includes the dielectric portion and a portion of the first gate dielectric layer covering the extension portion, the dielectric portion is located on a side of the first gate dielectric layer away from the first channel layer.

[0016] Optionally, the material of the dielectric part includes a low dielectric constant material.

[0017] Optionally, the first via hole and the accommodating hole are coaxially arranged.

[0018] Optionally, the aperture of the first via hole at an end away from the first gate is greater than or equal to the aperture of the first via hole at an end close to the first gate, and the aperture of the first via hole at an end close to the first gate is greater than or equal to 20 nanometers; and / or

[0019] The inner diameter of the containing hole is 50 nanometers to 500 nanometers.

[0020] Optionally, the storage device layer includes a first channel layer, the first channel layer is formed on the sidewall of the accommodating hole, the first channel layer includes the first channel and an extension portion, the surface of the first source close to the second insulating layer is the upper surface of the first source, the first channel is located on the side of the upper surface of the first source away from the second insulating layer, the extension portion is located on the side of the upper surface of the first source close to the second insulating layer, there is a predetermined distance between the upper surface of the extension portion close to the second insulating layer and the upper surface of the first insulating layer close to the second insulating layer, and in the depth direction of the accommodating hole, the second channel and the first channel layer are spaced apart.

[0021] Optionally, the first gate dielectric layer covers the first channel and the bottom of the accommodating hole, the accommodating hole extends to the upper surface of the first drain electrode close to the second insulating layer, or the accommodating hole extends into the first drain electrode, or the accommodating hole passes through the first drain electrode.

[0022] Optionally, the storage device layer also includes a first signal line, a second signal line, a third signal line and a fourth signal line, the first signal line and the second signal line are both located in the first insulating layer and have different extension directions, the first signal line is connected to the first drain, the second signal line is connected to the first source, the fourth signal line is located in the second insulating layer, the third signal line and the fourth signal line have different extension directions, the third signal line is connected to the second source, and the fourth signal line is connected to the second gate.

[0023] Optionally, the first signal line and the first drain are arranged on the same layer, the second signal line and the first source are arranged on the same layer, the fourth signal line and the second gate are arranged on the same layer, or the fourth signal line is arranged on a side of the second gate away from the first gate.

[0024] Optionally, the fourth signal line and the second gate are arranged in the same layer, and the fourth signal line is a stacked structure, which includes a second gate material layer in contact with the second gate dielectric layer, and a conductor layer located on a side of the second gate material layer away from the second gate dielectric layer.

[0025] Optionally, the third signal line includes a first branch line, and the first branch line, the second source and the second channel are arranged in the same layer and are connected; and / or

[0026] The third signal line includes a second branch line, the second branch line is arranged on a side of the second insulating layer away from the first insulating layer, and the second branch line is connected to the second source electrode through a second via hole.

[0027] Optionally, the material of the second channel includes an oxide semiconductor, and the material of the second branch line includes tungsten, molybdenum, titanium nitride, doped polysilicon or doped single crystal silicon.

[0028] The present application also provides a method for manufacturing a storage device, comprising:

[0029] A stacking structure is formed on one side of the substrate, the stacking structure comprising a first insulating layer and a first lead layer and a second lead layer spaced apart in the first insulating layer, the second lead layer being located on a side of the first lead layer away from the substrate, the first lead layer comprising a first drain electrode, and the second lead layer comprising a first source electrode;

[0030] forming a receiving hole on a side of the stacking structure away from the substrate;

[0031] A first channel is formed at least in a partial area of ​​the side wall of the receiving hole, wherein the first channel connects the first drain electrode and the first source electrode;

[0032] forming a first gate dielectric layer at least covering the first channel;

[0033] Forming a first gate on a side of the first gate dielectric layer in the receiving hole away from the first channel;

[0034] A second channel and a second source electrode connected to each other are formed on a side of the first gate away from the substrate, wherein the second channel is at least partially located in the receiving hole;

[0035] A second gate dielectric layer and a second gate are sequentially formed on a side of the second channel away from the substrate, the first gate, the first channel, the first drain and the first source constitute a read transistor, and the second gate, the second channel and the second source constitute a write transistor;

[0036] A second insulating layer is formed to cover at least the second gate and the second source.

[0037] Optionally, forming a first channel at least in a partial area of ​​the side wall of the receiving hole includes:

[0038] forming a first channel material layer at least on the inner wall of the receiving hole;

[0039] The first channel material layer is dry-etched to remove at least a portion of the first channel material layer at the bottom of the accommodating hole to form a first channel layer covering the side wall of the accommodating hole, wherein the upper surface of the first channel layer close to the second insulating layer is flush with or spaced apart from the upper surface of the first insulating layer close to the second insulating layer, and the first channel layer includes the first channel.

[0040] Optionally, before forming the second gate dielectric layer, the method for manufacturing the storage device includes:

[0041] Forming a dielectric layer in the receiving hole and on a side of the first gate away from the substrate;

[0042] The dielectric layer is dry-etched to open a first via hole on the dielectric layer to form a dielectric portion that at least covers a portion of the first gate dielectric layer located in the receiving hole, wherein the first via hole exposes the first gate;

[0043] The second channel is formed so as to pass through the first via hole and be connected to the first gate.

[0044] Optionally, the second channel material layer is manufactured by an atomic layer deposition process.

[0045] Optionally, forming a second channel and a second source connected to each other on a side of the first gate away from the substrate includes:

[0046] forming a second channel material layer on a side of the first gate away from the substrate;

[0047] The second channel material layer is etched to form the second channel and the second source.

[0048] Optionally, forming a stacked structure on one side of the substrate includes:

[0049] A first insulating material layer, the first wiring layer, a second insulating material layer, the second wiring layer and a third insulating material layer are sequentially stacked on the substrate, the first wiring layer includes a first signal line connected to the first drain, the second wiring layer includes a second signal line connected to the first source, and the first signal line and the second signal line extend in different directions;

[0050] The etching of the second channel material layer to form the second channel and the second source includes: forming a first branch line connected to the second source; and / or, after the forming of the second insulating layer at least covering the second gate and the second source, the manufacturing method of the storage device includes: forming a second branch line on a side of the second insulating layer away from the substrate, the second branch line is connected to the second source through a second via hole, and the first branch line and / or the second branch line constitute a third signal line;

[0051] The step of sequentially forming a second gate dielectric layer and a second gate on a side of the second channel away from the substrate comprises:

[0052] forming the second gate dielectric layer at least covering the second channel;

[0053] The second gate and the fourth signal line are connected to each other, the second gate is located on the side of the second gate dielectric layer away from the substrate, and the fourth signal line and the third signal line extend in different directions.

[0054] Optionally, the orthographic projection of the accommodating hole on the substrate is located within the orthographic projection of the first drain on the substrate, the orthographic projection of the accommodating hole on the substrate is located within the orthographic projection of the first source on the substrate, and the orthographic projection of the accommodating hole on the substrate is located within the orthographic projection of the second source on the substrate, the accommodating hole is formed by dry etching, and the accommodating hole passes through the first drain.

[0055] The storage device and the manufacturing method thereof disclosed in the present application have the following beneficial effects:

[0056] In the present application, the storage device includes a substrate and at least one storage device layer arranged on the substrate, the storage device layer includes an insulating layer and at least one storage unit, the storage unit includes a read transistor and a write transistor, in the read transistor: the first channel is formed at least in a partial area of ​​the side wall of the receiving hole of the first insulating layer, the first gate dielectric layer at least covers the first channel, the first gate is formed in the receiving hole and is located on the side of the first gate dielectric layer away from the first channel; in the write transistor: the second channel is at least partially located in the receiving hole. Through the arrangement of the first channel and the second channel, the read transistor and the write transistor are formed as stacked vertical channel transistors, and the channels of the read transistor and the write transistor are in the same receiving hole, which reduces the area occupied by the storage unit and improves the integration density of the transistor compared to the storage unit connected by two thin film transistors with horizontal channels on the same plane.

[0057] Other features and advantages of the present application will become apparent from the following detailed description, or may be learned in part by the practice of the present application.

[0058] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] The drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the specification are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0060] Figure 1 is a schematic top view of a storage device in an embodiment of the present application.

[0061] Figure 2 yes Figure 1 Schematic diagram of the X-direction cross-section of the storage device.

[0062] Figure 3 yes Figure 1 Schematic diagram of the Y-direction cross-section of the storage device.

[0063] Figure 4 2 is a schematic diagram of a cross-section in the X direction of a storage device provided with a medium portion in an embodiment of the present application.

[0064] Figure 5 Schematic diagram of the circuit structure of the storage unit in the embodiment of the present application.

[0065] Figure 6 Schematic diagram of the circuit structure of the storage device in the embodiment of the present application.

[0066] Figure 7 It is a flow chart of a method for manufacturing a storage device in an embodiment of the present application.

[0067] Figure 8 2 is a schematic diagram of a cross-section in the X direction of a receiving hole formed in an embodiment of the present application.

[0068] Fig. 9 It is a schematic diagram of the X-direction cross-section of forming the first channel layer in the embodiment of the present application.

[0069] Fig.10 It is a schematic diagram of the X-direction cross-section of forming the first gate in the embodiment of the present application.

[0070] Fig.11 It is a schematic diagram of a Y-direction cross-section of forming a first gate in an embodiment of the present application.

[0071] Fig.12 It is a schematic diagram of the X-direction cross section of forming the second channel in the embodiment of the present application.

[0072] Fig.13 It is a schematic diagram of the Y-direction cross-section of forming the second channel in the embodiment of the present application.

[0073] Fig.14 2 is a schematic diagram of a cross-section in the X direction in forming a fourth signal line in an embodiment of the present application.

[0074] Fig.15 It is a schematic diagram of a Y-direction cross-section of forming a fourth signal line in an embodiment of the present application.

[0075] Fig.16 Schematic diagram of the X-direction cross section of the dielectric portion formed in the embodiment of the present application.

[0076] Description of reference numerals:

[0077] 100, substrate;

[0078] 210, first insulating layer; 211, receiving hole; 220, second insulating layer;

[0079] 311, first drain; 312, first signal line; 321, first source; 322, second signal line; 331, second branch line; 341, conductor layer;

[0080] 410, first channel layer; 411, first channel; 412, extension portion; 421, second channel; 422, second source; 423, first branch line;

[0081] 511, a first gate dielectric layer; 521, a second gate dielectric layer;

[0082] 611, a first gate; 621, a second gate material layer;

[0083] 710, dielectric portion; 711, first via hole;

[0084] 10. Read transistor; 20. Write transistor. DETAILED DESCRIPTION

[0085] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be more comprehensive and complete and fully convey the concept of the example embodiments to those skilled in the art.

[0086] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present application. However, those skilled in the art will appreciate that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, known methods, devices, realizations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0087] The present application is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be understood as limiting the present application.

[0088] See also Figures 1 to 3 As shown, the storage device in this embodiment includes a substrate 100 and at least one storage device layer disposed on the substrate 100. The substrate 100 can be any base material for carrying semiconductor integrated circuits that is well known to those skilled in the art. The substrate 100 is, for example, an insulating substrate, a semiconductor substrate, or a composite substrate, and this application does not limit this. It is understandable that the substrate 100 can be removed after the storage device layer is manufactured. After the storage device layer is manufactured and the substrate 100 is removed, it is bonded to other substrates with the top surface or the bottom surface. The other substrates are, for example, peripheral substrates or temporary support substrates containing peripheral devices, or substrates provided with other devices. The relationship between the substrate 100 and the storage device layer is not specifically limited in this application.

[0089] The memory device layer includes an insulating layer and at least one memory cell ( Figure 2 and Figure 3Only one memory cell is shown). The insulating layer includes a first insulating layer 210 and a second insulating layer 220 stacked in a vertical direction, and the vertical direction may be a direction perpendicular or approximately perpendicular to the substrate 100. The memory cell includes a read transistor 10 and a write transistor 20.

[0090] The read transistor 10 includes a first gate 611, a first gate dielectric layer 511, a first channel 411, a first drain 311 and a first source 321. A receiving hole 211 is provided on the side of the first insulating layer 210 close to the second insulating layer 220, and the first channel 411 is formed at least in a partial area of ​​the sidewall of the receiving hole 211. The first drain 311 and the first source 321 are arranged outside the receiving hole 211 at intervals, and the first drain 311 is located on the side of the first source 321 away from the second insulating layer 220, that is, the first drain 311 is closer to the substrate 100 than the first source 321. The first drain 311 and the first source 321 are both connected to the first channel 411. The first gate dielectric layer 511 at least covers the first channel 411, and the first gate 611 is formed in the receiving hole 211 and is located on the side of the first gate dielectric layer 511 away from the first channel 411.

[0091] The write transistor 20 includes a second gate, a second gate dielectric layer 521, a second channel 421 and a second source 422. The second channel 421 is at least partially located in the accommodating hole 211, the drain end of the second channel 421 is connected to the first gate 611, the second source 422 is located outside the accommodating hole 211, the second source 422 is connected to the second channel 421, the second gate is formed on the side of the second channel 421 away from the first gate dielectric layer 511, and the second gate dielectric layer 521 is formed between the second gate and the second channel 421.

[0092] The existing dynamic random access memory based on 2T0C storage unit generally uses two thin film transistors with horizontal channels on the same plane to connect, which occupies a large area and has a low storage density.

[0093] In this embodiment, the storage device includes a substrate 100 and at least one storage device layer disposed on the substrate 100. When the storage device layer is multi-layered, the multi-layer storage device layer is vertically stacked on the substrate 100. The storage device layer includes an insulating layer and at least one storage unit. The storage unit includes a read transistor 10 and a write transistor 20. In the read transistor 10, a first channel 411 is formed at least in a partial area of ​​a sidewall of a receiving hole 211 of a first insulating layer 210, a first gate dielectric layer 511 at least covers the first channel 411, and a first gate 611 is formed in the receiving hole 211 and is located on a side of the first gate dielectric layer 511 away from the first channel 411; in the write transistor 20, a second channel 421 is at least partially located in the receiving hole 211. By setting the first channel 411 and the second channel 421, the read transistor 10 and the write transistor 20 are formed as stacked vertical channel transistors, and the channels of the read transistor 10 and the write transistor 20 are in the same accommodating hole 211. Compared with the memory cell connected by thin film transistors with two horizontal channels on the same plane, the area occupied by the memory cell is reduced and the integration density of the transistor is improved.

[0094] See also Figures 2 to 3 As shown, the upper surface of the first gate 611 is lower than the upper surface of the first insulating layer 210 and higher than the lower surface of the first source 321. The upper surface of the first gate 611 may be a plane or a nearly plane.

[0095] The upper surface of the first gate 611 is higher than the lower surface of the first source 321 , which can ensure the control ability of the first gate 611 on the first channel 411 and improve the reading margin; the upper surface of the first gate 611 is lower than the upper surface of the first insulating layer 210 , ensuring that there is space on the upper part of the accommodating hole 211 to accommodate the write transistor 20 .

[0096] Preferably, the upper surface of the first gate 611 is slightly higher than the upper surface of the first source 321 , which can maximize the control capability of the first gate 611 over the first channel 411 and ensure that there is more space above the accommodating hole 211 to accommodate the write transistor 20 .

[0097] See also Figures 1 to 3 As shown, the orthographic projection of the accommodating hole 211 on the substrate 100 is located within the orthographic projection of the first drain 311 on the substrate 100; the orthographic projection of the accommodating hole 211 on the substrate 100 is located within the orthographic projection of the first source 321 on the substrate 100; and the orthographic projection of the accommodating hole 211 on the substrate 100 is located within the orthographic projection of the second source 422 on the substrate 100.

[0098] The first channel 411 is disposed in a partial area of ​​the side wall of the receiving hole 211, and the first channel 411 surrounds the first gate 611. The second gate is at least partially located in the receiving hole 211, and at least a portion of the second channel 421 surrounds the portion of the second gate located in the receiving hole 211. In other words, a portion of the second channel 421 is located between the second gate and the first gate 611, and a portion of the second channel 421 is located between the second gate and the receiving hole 211. The receiving hole 211 may be a circular hole, and the first gate 611 and the portion of the second gate located in the receiving hole 211 may be a cylinder.

[0099] It should be noted that the first channel 411 may be disposed in a partial area of ​​the side wall of the receiving hole 211 , but is not limited thereto. A portion of the first channel 411 may also be disposed at the bottom of the receiving hole 211 , depending on the specific circumstances.

[0100] The first channel 411 surrounds the first gate 611, and at least part of the second channel 421 surrounds the part of the second gate located in the accommodating hole 211, that is, the read transistor 10 and the write transistor 20 are both channel-wrap transistors. When occupying the same area on the substrate, the vertical channel-wrap transistor has a larger channel width than the horizontally arranged planar transistor, which improves the reading margin, and can change the channel length by adjusting the extension length of the channel between the source and the drain in the vertical direction to reduce charge leakage, which is beneficial to improving the performance of the storage device.

[0101] See also Figures 1 to 3 As shown, the memory device layer includes a first channel layer 410 and an isolation portion. The first channel layer 410 is formed on the sidewall of the receiving hole 211. The first channel layer 410 includes a first channel 411 and an extension portion 412. The surface of the first source 321 close to the second insulating layer 220 is the upper surface of the first source 321. The first channel 411 is located on the side of the upper surface of the first source 321 away from the second insulating layer 220. The extension portion 412 is located on the side of the upper surface of the first source 321 close to the second insulating layer 220. The upper surface of the extension portion 412 close to the second insulating layer 220 is flush with the upper surface of the first insulating layer 210 close to the second insulating layer 220 or forms a gap, that is, the first channel layer 410 covers the entire sidewall of the receiving hole 211 or the upper surface of the first channel layer 410 is slightly lower than the upper surface of the first insulating layer 210. The isolation portion is formed between the extension portion 412 and the second channel 421.

[0102] The first channel layer 410 is formed on the entire side wall of the receiving hole 211. When manufacturing the first channel layer 410, a first channel material layer can be formed on the inner wall of the receiving hole 211 and the upper surface of the first insulating layer 210, and then the upper surface of the first insulating layer 210 and the first channel material layer at the bottom of the receiving hole 211 are etched away to form the first channel layer 410. Compared with the solution in which the first channel layer 410 is formed in a partial area of ​​the side wall of the receiving hole 211, the manufacturing process of the first channel layer 410 is simpler, which can reduce the manufacturing cost of the storage device. In other embodiments, when manufacturing the first channel layer 410, a first channel material layer can be formed on the inner wall of the receiving hole 211 and the upper surface of the first insulating layer 210, and a sacrificial material layer is prepared to at least cover the portion of the first channel material layer located at the bottom of the receiving hole 211, and then the first channel material layer located on the upper surface of the first insulating layer 210 is etched and removed to form the first channel layer 410. The first channel layer 410 also includes a portion located at the bottom of the receiving hole 211, and the specific details may depend on the circumstances.

[0103] When etching to remove the upper surface of the first insulating layer 210 and the first channel material at the bottom of the accommodating hole 211, the first channel material layer can be partially over-etched so that a gap is formed between the upper surface of the extension portion 412 close to the second insulating layer 220 and the upper surface of the first insulating layer 210 close to the second insulating layer 220, that is, the upper surface of the first channel layer 410 is slightly lower than the upper surface of the first insulating layer 210, which can ensure that the upper surface of the first insulating layer 210 and the first channel material at the bottom of the accommodating hole 211 are removed while reducing the requirements for the accuracy of the etching process.

[0104] The isolation portion is formed between the extension portion 412 and the second channel 421. Figure 2 and Figure 3 As shown, the first gate dielectric layer 511 may cover the first channel layer 410 and the bottom of the receiving hole 211 , and the isolation portion includes a portion of the first gate dielectric layer 511 covering the extension portion 412 .

[0105] In other embodiments, see Figure 4 As shown, the isolation portion includes a dielectric portion 710, which is formed in the accommodating hole 211 and is located on the side of the first gate 611 close to the second insulating layer 220. The dielectric portion 710 has a first via hole 711, and the first via hole 711 exposes a portion of the upper surface of the first gate 611. The second channel 421 is connected to the first gate 611 through the first via hole 711, that is, the dielectric portion 710 is located between the second channel 421 and the first channel layer 410. For example, the aperture of the first via hole 711 away from the first gate 611 is greater than or equal to the aperture of the first via hole 711 close to the first gate 611.

[0106] The inner diameter of the accommodation hole 211 is 50 nanometers to 500 nanometers. When the inner diameter of the accommodation hole 211 is less than 50 nanometers, the difficulty of the preparation process of the accommodation hole 211 is increased, and it is not conducive to the filling of the film layers of the read transistor 10 and the write transistor 20 and the dielectric part 710 (if any) in the hole; when the inner diameter of the accommodation hole 211 is greater than 500nm, the occupied area is large, which is not conducive to the improvement of storage density.

[0107] The aperture of the first via hole 711 near the first gate 611 is greater than or equal to 20 nanometers. When the aperture of the first via hole 711 near the first gate 611 is less than 20 nanometers: the contact area between the first gate 611 and the second channel 421 is too small, and the impedance is large during writing and erasing through the write transistor 20; during the preparation of the second channel 421, the reliability of the connection between the second channel 421 and the first gate 611 is reduced due to the uniformity limitation of the film deposition.

[0108] It can be understood that when the inner diameter of the accommodating hole 211 is less than 50 nanometers and the storage unit also includes a dielectric portion 710, and the second channel 421 is connected to the first gate 611 via a first via hole 711 in the dielectric portion 710, the manufacturing process is difficult, including but not limited to increased requirements for uniformity of deposition and etching during the preparation of the dielectric portion 710.

[0109] Since the first channel layer 410 is formed on the entire sidewall of the accommodating hole 211, the second channel 421 is at least partially located in the accommodating hole 211, and the second channel 421 is partially surrounded by the first channel layer 410 in the accommodating hole 211, and the second channel 421 and the first channel layer 410 overlap in the vertical direction. The dielectric portion 710 is provided between the second channel 421 and the first channel layer 410, which can reduce the parasitic capacitance between the second channel 421 and the first channel layer 410, and reduce the crosstalk between the first channel layer 410 and the write transistor 20.

[0110] It should be understood that the isolation portion includes the portion of the first gate dielectric layer 511 covering the extension portion 412, or the isolation portion includes the portion of the first gate dielectric layer 511 covering the extension portion 412 and the dielectric portion 710, but is not limited to this. The isolation portion may also include the dielectric portion 710 but does not include the portion of the first gate dielectric layer 511 covering the extension portion 412, that is, when the isolation portion includes the dielectric portion 710, the first gate dielectric layer 511 may not cover the portion of the extension portion 412, which may depend on the specific circumstances.

[0111] See also Figure 4 As shown, the first through hole 711 and the receiving hole 211 are coaxially arranged.

[0112] The first via hole 711 and the receiving hole 211 are coaxially arranged, so that the second channel 421 and the first channel layer 410 are evenly spaced, which can further reduce the parasitic capacitance between the two layers of channels.

[0113] In some embodiments, the material of the dielectric portion 710 includes a low dielectric constant material.

[0114] The dielectric portion 710 is made of a low dielectric constant material to further reduce the parasitic capacitance between the two layers of channels.

[0115] In this embodiment, the first channel layer 410 is formed on the entire sidewall of the receiving hole 211 to simplify the manufacturing process of the first channel layer 410. In some embodiments, when the upper surface of the first insulating layer 210 and the first channel material layer at the bottom of the receiving hole 211 are etched away to form the first channel layer 410, the first channel layer 410 is located at the opening of the receiving hole 211, that is, the portion of the first channel layer 410 located at the upper end of the sidewall of the receiving hole 211 can be etched away by a predetermined amount, for example, a protective material layer is used to fill a partial depth of the receiving hole 211, and then a predetermined amount of the first channel material layer not covered by the protective material layer is etched away, and the protective material layer is removed, so that the first channel layer 410 can be formed in a partial area of ​​the sidewall of the receiving hole 211, and in the depth direction of the receiving hole 211, the second channel 421 and the first channel layer 410 are spaced apart.

[0116] The second channel 421 and the first channel layer 410 are spaced apart in the depth direction of the receiving hole 211, which can reduce the parasitic capacitance between the two channels and reduce the mutual influence between the read transistor 10 and the write transistor 20. At the same time, the process of manufacturing the dielectric portion 710 can be omitted to reduce the manufacturing cost of the storage device.

[0117] See also Figures 1 to 3 As shown, the first gate dielectric layer 511 covers the first channel layer 410 and the bottom of the receiving hole 211 , and the receiving hole 211 penetrates the first drain 311 .

[0118] It should be noted that the receiving hole 211 may penetrate the first drain electrode 311 , but is not limited thereto. The receiving hole 211 may also extend to the upper surface of the first drain electrode 311 close to the second insulating layer 220 or extend into the first drain electrode 311 , depending on the specific circumstances.

[0119] When the receiving hole 211 extends to the upper surface of the first drain electrode 311 or extends into the first drain electrode 311, the bottom surface of the receiving hole 211 may be covered by the first channel layer 410, so that the first channel layer 410 and the first drain electrode 311 have a sufficiently large contact surface. The receiving hole 211 penetrates the first drain electrode 311, and the first channel layer 410 may be formed only on the sidewall of the receiving hole 211, and the manufacturing process of the first channel layer 410 is simpler. When the accommodating hole 211 passes through the first drain 311 and the first channel layer 410 is formed on the side wall of the accommodating hole 211 but not formed on the bottom surface of the accommodating hole 211, the first gate dielectric layer 511 covers the bottom surface of the accommodating hole 211 and the first gate electrode 611 is formed on the surface of the first gate dielectric layer 511 away from the bottom surface of the accommodating hole 211. Compared with the case where the first gate dielectric layer 511 does not cover the bottom surface of the accommodating hole 211 and the first gate electrode 611 is formed on the surface of the first insulating layer 210 located on the bottom surface of the accommodating hole 211, the first gate electrode 611 is easier to prepare.

[0120] See also Figures 1 to 3 As shown, the memory device layer further includes a first signal line 312, a second signal line 322, a third signal line and a fourth signal line. The first signal line 312 and the second signal line 322 are both located in the first insulating layer 210 and extend in different directions. For example, the first signal line 312 may extend along the X direction, and the second signal line 322 may extend along the Y direction, wherein the X direction and the Y direction form an angle, such as a right angle or an acute angle, but the present invention is not limited thereto. The first signal line 312 is connected to the first drain 311, and the second signal line 322 is connected to the first source 321.

[0121] The fourth signal line is located in the second insulating layer 220, and the third signal line and the fourth signal line have different extension directions. The fourth signal line is located in the second insulating layer 220, for example, at least one side of the fourth signal line is covered by the second insulating layer 220, that is, the fourth signal line can be covered by the second insulating layer 220 on one side or on three sides; the third signal line and the fourth signal line have different extension directions, for example, the third signal line can extend along the X direction, and the fourth signal line can extend along the Y direction, wherein the X direction and the Y direction form an angle, such as a right angle or an acute angle, and the present invention is not limited thereto. The third signal line is connected to the second source 422, and the fourth signal line is connected to the second gate.

[0122] like Figure 6As shown, in the memory device layer, the memory devices are usually arranged in a matrix. For example, the first signal line 312 and the second signal line 322 connected to the same memory cell are respectively connected to a row of memory cells and a column of memory cells in the matrix, and the third signal line and the fourth signal line are respectively connected to a row of memory cells and a column of memory cells in the matrix. By making the first signal line 312 and the second signal line 322 extend in different directions, and the third signal line and the fourth signal line extend in different directions, through the intersection of the first signal line 312 and the second signal line 322, and the intersection of the third signal line and the fourth signal line, the memory cell is located at the intersection point and is connected to the first to fourth signal lines, so that the memory cell can be selected for reading and writing functions. The first signal line 312 can be parallel to one of the third and fourth signal lines, and the second signal line 322 can be parallel to the other of the third and fourth signal lines, but the present invention is not limited thereto, as long as the extension directions of the first signal line 312 and the second signal line 322, and the third signal line and the fourth signal line are different.

[0123] See also Figures 1 to 3 As shown, the first signal line 312 and the first drain 311 are arranged on the same layer, the second signal line 322 and the first source 321 are arranged on the same layer, and the fourth signal line and the second gate are arranged on the same layer.

[0124] It should be noted that the first signal line 312 and the first drain 311 can be arranged in the same layer, that is, the first signal line 312 and the first drain 311 are integrally connected and made of the same material in the same process, but not limited to this, the first signal line 312 and the first drain 311 can also be made of different materials and different processes, depending on the specific situation. Correspondingly, the second signal line 322 and the first source 321 can be arranged in the same layer, that is, the second signal line 322 and the first source 321 are integrally connected and made of the same material in the same process, but not limited to this, the second signal line 322 and the first source 321 can also be made of different materials and different processes. The fourth signal line and the second gate are arranged in the same layer, that is, the fourth signal line and the second gate are integrally connected and made of the same material in the same process, but not limited to this, the fourth signal line and the second gate can also be made of different materials and different processes, depending on the specific situation.

[0125] The first signal line 312 is disposed on the same layer as the first drain 311 , the second signal line 322 is disposed on the same layer as the first source 321 , and the fourth signal line is disposed on the same layer as the second gate, which can reduce the manufacturing cost of the storage device.

[0126] It should be noted that the fourth signal line can also be arranged on the side of the second gate away from the first gate 611, and connected to the second gate directly or through a through hole. The present invention does not specifically limit the connection method between the fourth signal line and the second gate.

[0127] It can be understood that in order to simultaneously obtain the write transistor 20 that meets the electrical characteristic requirements and the fourth signal line with lower impedance, the fourth signal line and the second gate prepared in the same layer can be multi-layered, such as Figure 2 , 3 As shown, the fourth signal line and the second gate prepared in the same layer include a stacked structure, the stacked structure includes a second gate material layer 621 close to the second gate dielectric layer 521, and a conductor layer 341 away from the second gate dielectric layer 521. The second gate material layer 621 is, for example, an oxide semiconductor or titanium nitride. The oxide semiconductor includes, for example, indium oxide, zinc oxide, gallium oxide, indium gallium zinc oxide, etc. The conductor layer 341 material includes, for example, tungsten, molybdenum, titanium nitride, doped polysilicon, doped single crystal silicon, etc. The materials of the second gate material layer 621 and the conductor layer 341 can be the same or different, depending on the specific situation. By configuring the second gate material layer 621 as a material that meets the electrical characteristics requirements of the write transistor 20 and configuring the conductor layer 341 as a high conductivity material, the manufacturing cost of preparing the fourth signal line and the second gate can be reduced while making the write transistor 20 meet the electrical characteristics requirements and the fourth signal line have low impedance.

[0128] Figure 2 , 3 In the illustrated embodiment, the stacked structure includes two layers, namely, a second gate material layer 621 and a conductor layer 341. In other embodiments, the stacked structure may include multiple film layers. Other conductive film layers may be provided between the second gate material layer 621 and the conductor layer 341. The conductor layer 341 may also have other conductive film layers on the side facing away from the second gate material layer 621. The second gate material layer 621 and the conductor layer 341 may also be multi-layer structures respectively. The present invention does not specifically limit the number of film layers in the stacked structure.

[0129] See also Figures 1 to 3 As shown, the third signal line includes a first branch line 423, and the first branch line 423, the second source 422 and the second channel 421 are arranged in the same layer and connected. The third signal line may also include a second branch line 331, the second branch line 331 is arranged on the side of the second insulating layer 220 away from the first insulating layer 210, and the second branch line 331 is connected to the second source 422 through a second via.

[0130] It should be noted that when the memory device layer includes the second branch line 331, a third insulating layer may be provided on the side of the second insulating layer 220 away from the first insulating layer 210 to cover the second branch line 331. The third signal line may include one of the first branch line 423 and the second branch line 331, or may include both the first branch line 423 and the second branch line 331.

[0131] The first branch line 423, the second source 422 and the second channel 421 are arranged in the same layer, which can reduce the manufacturing cost of the storage device. At the same time, the first branch line 423 is made of the material of the second channel 421, which saves the step of separately manufacturing the first branch line 423, thereby reducing the manufacturing cost of the storage device. When the impedance of the first branch line 423 is large, it is not conducive to signal transmission. The second branch line 331 is made on the side of the second insulating layer 220 away from the first insulating layer 210, which can reduce the impedance between the second source 422 of two adjacent storage units and reduce the signal delay on the third signal line.

[0132] The material of the second channel 421 includes an oxide semiconductor. The off-state current of the thin film transistor made of an oxide semiconductor is extremely small, and the dynamic random access memory used for 2TOC can significantly reduce the leakage current. It should be understood that the first channel 411 and the second channel 421 can be made of an oxide semiconductor material, such as indium oxide, zinc oxide, gallium oxide, indium gallium zinc oxide, etc., but not limited thereto. The first channel 411 and the second channel 421 can also be other metal oxides or semiconductor materials, depending on the specific situation.

[0133] When the material of the second channel 421 is an oxide semiconductor, the second branch line 331 is made of a material with good conductivity such as tungsten, molybdenum, titanium nitride, doped polysilicon or doped single crystal silicon, which can reduce the impedance between the second source 422 of two adjacent storage cells and reduce the signal attenuation on the third signal line.

[0134] In addition, the insulating layer can be made of insulating materials commonly used in the art, such as silicon oxide and silicon nitride. The insulating layer preferably includes a low dielectric constant material, or includes an air gap to reduce crosstalk between wiring or devices. It should be understood that the insulating layer can be an insulating dielectric material commonly used in the art, and this application is not limited thereto. The material used to make the insulating layer and the material used to make the dielectric portion 710 can be the same or different. The gate dielectric layer can be made of a material with a high dielectric constant or other materials commonly used in the art for gate dielectric layers, such as hafnium dioxide, silicon dioxide, and aluminum oxide.

[0135] The first gate 611 may be made of a conductive material capable of storing charges, such as doped polysilicon, but the present application is not limited thereto, and may also be made of tungsten, doped single crystal silicon, molybdenum or titanium nitride, etc., as long as the material of the first gate 611 can achieve charge storage. The material of the second gate material layer 621 includes an oxide semiconductor or titanium nitride, which may be the same as or different from the material of the first gate 611. The materials of the first drain 311, the first source 321 and the conductor layer 341 may be the same as or different from the second branch line 331.

[0136] See also Figures 2 to 6As shown, the first signal line 312 can be used as a read word line RWL, the second signal line 322 can be used as a read bit line RBL, the third signal line can be used as a write bit line WBL, and the fourth signal line can be used as a write word line WWL. It can be understood that the connection relationship between the write word line WWL, the write bit line WBL and the write transistor 20 can be interchanged, the connection relationship between the read word line RWL, the read bit line RBL and the read transistor 10 can be interchanged, and the operation method of the write word line WWL, the write bit line WBL, the read word line RWL, and the read bit line RBL in the storage operation is also changed accordingly, and the present invention does not make specific limitations.

[0137] The memory cell changes the charge in the gate capacitance of the read transistor 10 by writing the transistor 20, thereby affecting the resistance between the source and drain of the read transistor 10, thereby realizing the distinction between "0" and "1". It can be understood that in this embodiment, the gate capacitance of the read transistor 10 is Figure 5 Node A is stored in the middle.

[0138] The specific storage principle of the storage unit is as follows:

[0139] During the writing process of "1", the write word line WWL adds a positive voltage (greater than the threshold voltage Vth) to the gate of the write transistor 20 to turn on the write transistor 20, and the write bit line WBL adds a positive voltage to the source of the write transistor 20 to the gate capacitance of the read transistor 10 (i.e. Figure 5 After the charge injection, the gate and source voltages of the write transistor 20 are removed to store the "1" state;

[0140] In the process of reading "1", the read word line RWL adds a read voltage to the source of the read transistor 10. Since a certain charge is stored in the gate capacitor, the read transistor 10 is in a relatively low resistance state, and the read bit line RBL obtains a relatively large current, which can be amplified and identified by the peripheral circuit to complete the process of reading "1";

[0141] In the process of writing "0", the write word line WWL adds a positive voltage (greater than the threshold voltage Vth) to the gate electrode of the write transistor 20 to turn on the write transistor 20, and the write bit line WBL adds a negative voltage to the source of the write transistor 20 to extract charge from the gate capacitance (i.e., the storage node) of the read transistor 10. After the charge is extracted, the gate and source voltages of the write transistor 20 are removed to save the "0" state;

[0142] In the process of reading "0", the read word line RWL adds a read voltage to the source of the read transistor 10. Since there is no charge in the gate capacitance, the read transistor 10 is in a higher resistance state, and the read bit line RBL obtains a smaller current, which can be amplified and identified by the peripheral circuit to complete the reading of "0".

[0143] The present application also provides a method for manufacturing a storage device, which is used to manufacture the storage device disclosed above. Figure 7 As shown, see Figures 7 to 15 As shown, the manufacturing method of the storage device includes:

[0144] S100: forming a stack structure on one side of the substrate 100, the stack structure comprising a first insulating layer 210 and a first lead layer and a second lead layer spaced apart in the first insulating layer 210, the second lead layer being located on a side of the first lead layer away from the substrate 100, the first lead layer comprising a first drain electrode 311, and the second lead layer comprising a first source electrode 321;

[0145] S200: forming a receiving hole 211 on a side of the stack structure away from the substrate 100;

[0146] S300 : forming a first channel 411 at least in a partial area of ​​the sidewall of the receiving hole 211 , wherein the first channel 411 connects the first drain 311 and the first source 321 ;

[0147] S400: forming a first gate dielectric layer 511 at least covering the first channel 411;

[0148] S500: forming a first gate 611 on a side of the first gate dielectric layer 511 in the receiving hole 211 away from the first channel 411;

[0149] S600: forming a second channel 421 and a second source 422 connected to each other on a side of the first gate 611 away from the substrate 100, wherein the second channel 421 is at least partially located in the receiving hole 211;

[0150] S700: forming a second gate dielectric layer 521 and a second gate in sequence on a side of the second channel 421 away from the substrate 100, the first gate 611, the first channel 411, the first drain 311 and the first source 321 constitute a read transistor 10, and the second gate, the second channel 421 and the second source 422 constitute a write transistor 20;

[0151] S800 : forming a second insulating layer 220 covering at least the second gate electrode and the second source electrode 422 .

[0152] In this embodiment, the first channel 411 and the first gate 611 of the read transistor 10, and the second channel 421 and the second gate of the write transistor 20 are formed in the same accommodating hole 211, forming a stacked vertical channel dual-transistor memory cell. Compared with a memory cell connected using two horizontal channel thin film transistors on the same plane, the area occupied by the memory cell is reduced and the integration density of the transistor is improved.

[0153] In some embodiments, when forming the stacked structure in step S100, a first insulating material layer, a first lead layer, a second insulating material layer, a second lead layer, and a third insulating material layer may be sequentially formed on the substrate 100. The first lead layer further includes a first signal line 312 connected to the first drain 311, and the second lead layer further includes a second signal line 322 connected to the first source 321. The first signal line 312 and the second signal line 322 extend in different directions. For example, the first signal line 312 may extend along the X direction, and the second signal line 322 may extend along the Y direction.

[0154] The first signal line 312 and the first drain 311 are disposed in the same layer, and the second signal line 322 and the first source 321 are disposed in the same layer, which can reduce the manufacturing cost of the storage device.

[0155] In some embodiments, the orthographic projection of the receiving hole 211 on the substrate 100 is located within the orthographic projection of the first drain 311 on the substrate 100; the orthographic projection of the receiving hole 211 on the substrate 100 is located within the orthographic projection of the first source 321 on the substrate 100, and the orthographic projection of the receiving hole 211 on the substrate 100 is located within the orthographic projection of the second source 422 on the substrate 100. The receiving hole 211 is formed by dry etching, and the receiving hole 211 passes through the first drain 311.

[0156] The accommodating hole 211 penetrates the first drain electrode 311, so that the first gate 611 formed subsequently overlaps more with the drain end of the first channel 411 in the depth direction of the accommodating hole 211, thereby improving the control capability of the first gate 611 over the first channel 411 and improving the reading margin. The first channel 411 can be formed only on the sidewall of the accommodating hole 211, and the manufacturing process of the first channel 411 is simpler.

[0157] In some embodiments, forming the first channel 411 at least in a portion of the sidewall of the receiving hole 211 includes:

[0158] Forming a first channel material layer at least on the inner wall of the receiving hole 211;

[0159] The first channel material layer is dry-etched to remove at least a portion of the first channel material layer at the bottom of the accommodating hole 211 to form a first channel layer 410 covering the side wall of the accommodating hole 211. The upper surface of the first channel layer 410 close to the second insulating layer 220 is flush with or spaced apart from the upper surface of the first insulating layer 210 close to the second insulating layer 220. The first channel layer 410 includes a first channel 411.

[0160] The first channel layer 410 is formed on the entire sidewall of the receiving hole 211 . Compared with the solution in which the first channel layer 410 is formed on a partial area of ​​the sidewall of the receiving hole 211 , the manufacturing process of the first channel layer 410 is simpler, which can reduce the manufacturing cost of the storage device.

[0161] Accordingly, in step S400 , forming the first gate dielectric layer 511 covering at least the first channel 411 includes: forming a first gate dielectric material layer covering the first channel layer 410 , the first gate dielectric material layer including the first gate dielectric layer 511 .

[0162] In some embodiments, in step S500, forming the first gate 611 on the side of the first gate dielectric layer 511 in the receiving hole 211 away from the first channel 411 includes: depositing a first gate material layer to fill the receiving hole 211 formed in step S400, and etching back to form the first gate 611. Preferably, the top surface of the first gate 611 is slightly higher than the upper surface of the first source 321, so that the first gate 611 formed subsequently overlaps more with the source end of the first channel 411 in the depth direction of the receiving hole 211, thereby improving the control capability of the first gate 611 over the first channel 411 and improving the reading margin.

[0163] In some embodiments, in step S600, forming a second channel 421 and a second source 422 connected to each other on a side of the first gate 611 away from the substrate 100 includes: Fig.12 As shown, in the receiving hole 211 formed in step S500, a second channel material layer is deposited, and then Fig.13 As shown, the second channel material layer is patterned to form a second channel 421 and a second source 422 .

[0164] In some embodiments, when patterning the second channel material layer, etching stops in the first gate dielectric material layer to ensure that the second channel material layer is cut off during patterning to avoid short circuit; preferably, etching stops in the first insulating layer 210 to further reduce the difficulty of controlling the etching process during patterning.

[0165] In some embodiments, see Fig.16 As shown, the first gate dielectric layer 511 covers the first channel layer 410. Before forming the second gate dielectric layer 521, the method for manufacturing the storage device includes:

[0166] A dielectric layer is formed in the receiving hole 211 and on a side of the first gate 611 away from the substrate 100;

[0167] A first via hole 711 is opened in the dielectric layer by dry etching the dielectric layer to form a dielectric portion 710 that at least covers the portion of the first gate dielectric layer 511 located in the receiving hole 211 , and the first via hole 711 exposes a portion of the upper surface of the first gate 611 ;

[0168] The second channel 421 is formed so as to pass through the first via hole 711 and connect to the first gate 611 .

[0169] Under the condition that the inner diameter of the accommodating hole 211 is constant, the inner diameter of the first via hole 711 is related to the thickness of the dielectric portion 710 in the radial direction. The method for preparing the dielectric layer preferably uses a deposition process with good step coverage, such as ALD (Atomic Layer Deposition), so that the thickness of the dielectric layer in the deposition surface has a high degree of uniformity. The inner diameter of the first via hole 711 is controlled by controlling the deposition thickness of the dielectric layer, so that the inner diameter of the first via hole 711 is not too small, resulting in the difficulty of the manufacturing process when the second channel 421 is connected to the first gate 611 via the first via hole 711 in the dielectric portion 710, and the inner diameter of the first via hole 711 is not too large, resulting in the distance between the two layers of channels being too close and the parasitic capacitance being increased.

[0170] Since the first channel layer 410 is formed on the entire sidewall of the receiving hole 211, the second channel 421 is at least partially located in the receiving hole 211, and the second channel 421 is located in the receiving hole 211 and partially located in the first channel layer 410, the second channel 421 and the first channel layer 410 overlap in the vertical direction. The dielectric portion 710 is provided between the second channel 421 and the first channel layer 410, which can reduce the parasitic capacitance between the two layers of channels and reduce the mutual influence between the read transistor 10 and the write transistor 20.

[0171] For example, the aperture of the first via hole 711 away from the first gate 611 is greater than or equal to the aperture of the first via hole 711 close to the first gate 611, so as to facilitate the filling of the second channel material layer. The aperture of the first via hole 711 close to the first gate 611 is greater than or equal to 20 nanometers. The second channel material layer is manufactured by atomic layer deposition process.

[0172] Since the second channel 421 passes through the first via hole 711 and is connected to the first gate 611 , the second channel material layer is manufactured by an atomic layer deposition process. The film layer formed by the atomic layer deposition process has good step coverage, which can improve the yield of the storage device.

[0173] In some embodiments, forming a second channel 421 and a second source 422 connected to each other on a side of the first gate 611 away from the substrate 100 includes:

[0174] forming a second channel material layer on a side of the first gate 611 away from the substrate 100;

[0175] The second channel material layer is etched to form a second channel 421 and a second source 422 .

[0176] The second source 422 and the second channel 421 are disposed in the same layer, which can reduce the manufacturing cost of the storage device.

[0177] In some embodiments, etching the second channel material layer to form the second channel 421 and the second source 422 includes:

[0178] A first branch line 423 connected to the second source 422 is formed, and the first branch line 423 constitutes a third signal line.

[0179] The second channel 421 , the second source 422 and the first branch line 423 are arranged in the same layer, which can reduce the manufacturing cost of the storage device.

[0180] In some embodiments, sequentially forming a second gate dielectric layer 521 and a second gate on a side of the second channel 421 away from the substrate 100 includes:

[0181] forming a second gate dielectric layer 521 at least covering the second channel 421;

[0182] A second gate and a fourth signal line are formed to be connected. The second gate is located on a side of the second gate dielectric layer 521 away from the substrate 100 . The fourth signal line and the third signal line extend in different directions.

[0183] The first signal line 312 and the second signal line 322 extend in different directions, and the fourth signal line and the third signal line extend in different directions. Through the intersection of the first signal line 312 and the second signal line 322, and the intersection of the third signal line and the fourth signal line, the storage unit is located at the intersection and is connected to the first to fourth signal lines, so that the storage unit can be selected for reading and writing functions.

[0184] In some embodiments, the material of the second channel 421 includes an oxide semiconductor, and the oxide semiconductor includes indium oxide, zinc oxide, or gallium oxide. After forming the second insulating layer 220 covering at least the second gate and the second source 422, the manufacturing method of the storage device includes:

[0185] A second branch line 331 is formed on the side of the second insulating layer 220 away from the substrate 100, and the second branch line 331 is connected to the second source 422 through a second via hole, and the first branch line 423 and / or the second branch line 331 constitute a third signal line. The material of the second branch line 331 includes tungsten, molybdenum, titanium nitride, doped polysilicon or doped single crystal silicon.

[0186] When the material of the second channel 421 is an oxide semiconductor, the second branch line 331 is made of a material with good conductivity such as tungsten, molybdenum, titanium nitride, doped polysilicon or doped single crystal silicon, which can reduce the impedance of the third signal line and reduce the signal delay on the third signal line.

[0187] The terms "first", "second", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", etc. may explicitly or implicitly include one or more of the feature. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0188] In this application, unless otherwise clearly specified and limited, the terms "assembly", "connection" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0189] In the description of this specification, the description with reference to the terms "some embodiments", "exemplarily", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0190] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application. Therefore, any changes or modifications made in accordance with the claims and description of the present application should fall within the scope of the patent of this application.

Claims

1. A storage device, characterized in that: The invention comprises a substrate and at least one storage device layer arranged on the substrate, wherein the storage device layer comprises: The insulating layer comprises a first insulating layer and a second insulating layer which are stacked in a vertical direction; At least one storage unit, the storage unit includes a read transistor and a write transistor, the read transistor includes a first gate, a first gate dielectric layer, a first channel, a first drain and a first source, the first insulating layer is provided with a receiving hole on a side close to the second insulating layer, the first channel is formed at least in a partial area of ​​a sidewall of the receiving hole, the first drain and the first source are arranged outside the receiving hole with intervals, the first drain is located on a side of the first source away from the second insulating layer, the first drain and the first source are both connected to the first channel, the first gate dielectric layer at least covers the first channel, and the first gate is formed in the receiving hole and is located on a side of the first gate dielectric layer away from the first channel; The write transistor includes a second gate, a second gate dielectric layer, a second channel and a second source, the second channel is at least partially located in the accommodating hole, the drain end of the second channel is connected to the first gate, the second source is connected to the second channel, the second gate is formed on the side of the second channel away from the first gate dielectric layer, and the second gate dielectric layer is formed between the second gate and the second channel.

2. The storage device according to claim 1, characterized in that An upper surface of the first gate electrode close to the second insulating layer is located between an upper surface of the first insulating layer close to the second insulating layer and a lower surface of the first source electrode away from the second insulating layer.

3. The storage device according to claim 2, characterized in that: The orthographic projection of the accommodating hole on the substrate is located within the orthographic projection of the first drain on the substrate, the orthographic projection of the accommodating hole on the substrate is located within the orthographic projection of the first source on the substrate, and the orthographic projection of the accommodating hole on the substrate is located within the orthographic projection of the second source on the substrate, the first channel surrounds the first gate, the second gate is at least partially located in the accommodating hole, and at least a portion of the second channel surrounds the portion of the second gate located in the accommodating hole.

4. The storage device according to any one of claims 1 to 3, characterized in that: The storage device layer includes a first channel layer and an isolation portion, the first channel layer is formed on the sidewall of the accommodating hole, the first channel layer includes the first channel and an extension portion, the surface of the first source electrode close to the second insulating layer is the upper surface of the first source electrode, the first channel is located on the side of the upper surface of the first source electrode away from the second insulating layer, the extension portion is located on the side of the upper surface of the first source electrode close to the second insulating layer, the upper surface of the extension portion close to the second insulating layer is flush with or spaced from the upper surface of the first insulating layer close to the second insulating layer, and the isolation portion is formed between the extension portion and the second channel.

5. The storage device according to claim 4, characterized in that: The isolation portion includes a dielectric portion, the dielectric portion is formed in the accommodating hole and is located on a side of the first gate close to the second insulating layer, the dielectric portion has a first via hole, and the second channel passes through the first via hole and is connected to the first gate; and / or The first gate dielectric layer also covers the extension portion, and the isolation portion includes a portion of the first gate dielectric layer covering the extension portion; Wherein, when the isolation portion includes the dielectric portion and a portion of the first gate dielectric layer covering the extension portion, the dielectric portion is located on a side of the first gate dielectric layer away from the first channel layer.

6. The storage device according to claim 5, characterized in that: The material of the dielectric portion includes a low dielectric constant material.

7. The storage device according to claim 5, characterized in that: The first through hole and the accommodating hole are coaxially arranged.

8. The storage device according to claim 5, characterized in that: The aperture of the first via hole at the end away from the first gate is greater than or equal to the aperture of the first via hole at the end close to the first gate, and the aperture of the first via hole at the end close to the first gate is greater than or equal to 20 nanometers; and / or The inner diameter of the containing hole is 50 nanometers to 500 nanometers.

9. The storage device according to claim 3, characterized in that: The storage device layer includes a first channel layer, the first channel layer is formed on the sidewall of the accommodating hole, the first channel layer includes the first channel and an extension portion, the surface of the first source electrode close to the second insulating layer is the upper surface of the first source electrode, the first channel is located on the side of the upper surface of the first source electrode away from the second insulating layer, the extension portion is located on the side of the upper surface of the first source electrode close to the second insulating layer, there is a predetermined distance between the upper surface of the extension portion close to the second insulating layer and the upper surface of the first insulating layer close to the second insulating layer, and in the depth direction of the accommodating hole, the second channel and the first channel layer are spaced apart.

10. The storage device according to claim 3, characterized in that: The first gate dielectric layer covers the first channel and the bottom of the accommodating hole, the accommodating hole extends to the upper surface of the first drain electrode close to the second insulating layer, or the accommodating hole extends into the first drain electrode, or the accommodating hole passes through the first drain electrode.

11. The storage device according to claim 1, characterized in that: The storage device layer also includes a first signal line, a second signal line, a third signal line and a fourth signal line. The first signal line and the second signal line are both located in the first insulating layer and extend in different directions. The first signal line is connected to the first drain, the second signal line is connected to the first source, and the fourth signal line is located in the second insulating layer. The third signal line and the fourth signal line extend in different directions. The third signal line is connected to the second source, and the fourth signal line is connected to the second gate.

12. The storage device according to claim 11, characterized in that: The first signal line and the first drain are arranged in the same layer, the second signal line and the first source are arranged in the same layer, the fourth signal line and the second gate are arranged in the same layer or the fourth signal line is arranged on a side of the second gate away from the first gate.

13. The storage device according to claim 12, characterized in that: The fourth signal line and the second gate are arranged in the same layer. The fourth signal line is a stacked structure, which includes a second gate material layer in contact with the second gate dielectric layer, and a conductor layer located on a side of the second gate material layer away from the second gate dielectric layer.

14. The storage device according to claim 11, characterized in that: The third signal line includes a first branch line, and the first branch line, the second source electrode and the second channel are arranged in the same layer and are connected; and / or The third signal line includes a second branch line, the second branch line is arranged on a side of the second insulating layer away from the first insulating layer, and the second branch line is connected to the second source electrode through a second via hole.

15. The storage device according to claim 14, characterized in that: The material of the second channel includes an oxide semiconductor, and the material of the second branch line includes tungsten, molybdenum, titanium nitride, doped polysilicon or doped single crystal silicon.

16. A method for manufacturing a storage device, characterized in that: include: A stacking structure is formed on one side of the substrate, the stacking structure comprising a first insulating layer and a first lead layer and a second lead layer spaced apart in the first insulating layer, the second lead layer being located on a side of the first lead layer away from the substrate, the first lead layer comprising a first drain electrode, and the second lead layer comprising a first source electrode; forming a receiving hole on a side of the stacking structure away from the substrate; A first channel is formed at least in a partial area of ​​the side wall of the receiving hole, wherein the first channel connects the first drain electrode and the first source electrode; forming a first gate dielectric layer at least covering the first channel; Forming a first gate on a side of the first gate dielectric layer in the receiving hole away from the first channel; A second channel and a second source electrode connected to each other are formed on a side of the first gate away from the substrate, wherein the second channel is at least partially located in the receiving hole; A second gate dielectric layer and a second gate are sequentially formed on a side of the second channel away from the substrate, the first gate, the first channel, the first drain and the first source constitute a read transistor, and the second gate, the second channel and the second source constitute a write transistor; A second insulating layer is formed to cover at least the second gate and the second source.

17. The method for manufacturing a storage device according to claim 16, characterized in that: The forming of the first channel at least in a partial area of ​​the side wall of the receiving hole comprises: forming a first channel material layer at least on the inner wall of the receiving hole; The first channel material layer is dry-etched to remove at least a portion of the first channel material layer at the bottom of the accommodating hole to form a first channel layer covering the side wall of the accommodating hole, wherein the upper surface of the first channel layer close to the second insulating layer is flush with or spaced apart from the upper surface of the first insulating layer close to the second insulating layer, and the first channel layer includes the first channel.

18. The method for manufacturing a storage device according to claim 17, characterized in that: The first gate dielectric layer at least covers the first channel layer. Before forming the second gate dielectric layer, the method for manufacturing the storage device includes: Forming a dielectric layer in the receiving hole and on a side of the first gate away from the substrate; The dielectric layer is dry-etched to open a first via hole on the dielectric layer to form a dielectric portion that at least covers a portion of the first gate dielectric layer located in the receiving hole, wherein the first via hole exposes the first gate; The second channel is formed so as to pass through the first via hole and be connected to the first gate.

19. The method for manufacturing a storage device according to claim 18, characterized in that: The second channel material layer is manufactured by an atomic layer deposition process.

20. The method for manufacturing a storage device according to claim 16, characterized in that: The second channel and the second source electrode connected to each other are formed on the side of the first gate away from the substrate, comprising: forming a second channel material layer on a side of the first gate away from the substrate; The second channel material layer is etched to form the second channel and the second source.

21. The method for manufacturing a storage device according to claim 20, characterized in that: The forming of the stacked structure on one side of the substrate comprises: A first insulating material layer, the first wiring layer, a second insulating material layer, the second wiring layer and a third insulating material layer are sequentially stacked on the substrate, the first wiring layer includes a first signal line connected to the first drain, the second wiring layer includes a second signal line connected to the first source, and the first signal line and the second signal line extend in different directions; The etching of the second channel material layer to form the second channel and the second source includes: forming a first branch line connected to the second source; and / or, after the forming of the second insulating layer at least covering the second gate and the second source, the manufacturing method of the storage device includes: forming a second branch line on a side of the second insulating layer away from the substrate, the second branch line is connected to the second source through a second via hole, and the first branch line and / or the second branch line constitute a third signal line; The step of sequentially forming a second gate dielectric layer and a second gate on a side of the second channel away from the substrate comprises: forming the second gate dielectric layer at least covering the second channel; The second gate and the fourth signal line are connected to each other, the second gate is located on the side of the second gate dielectric layer away from the substrate, and the fourth signal line and the third signal line extend in different directions.

22. The method for manufacturing a storage device according to claim 16, characterized in that: The orthographic projection of the accommodating hole on the substrate is located within the orthographic projection of the first drain on the substrate, the orthographic projection of the accommodating hole on the substrate is located within the orthographic projection of the first source on the substrate, and the orthographic projection of the accommodating hole on the substrate is located within the orthographic projection of the second source on the substrate. The accommodating hole is formed by dry etching, and the accommodating hole passes through the first drain.

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