IGBT (Insulated Gate Bipolar Translator) device capable of suppressing short-circuit oscillation and preparation method thereof

Abstract

The invention discloses an IGBT device capable of suppressing short-circuit oscillation and a preparation method, and relates to the field of semiconductor devices, and the IGBT device comprises a semiconductor substrate and an active region prepared in the central region of the semiconductor substrate; the semiconductor substrate comprises a first conduction type drift region, and the first conduction type is an N type; the active region comprises a plurality of cells which are distributed in parallel, and any cell comprises a plurality of carrier adjusting units; the carrier adjusting unit is located in the first conduction type drift region, so that the electron concentration in the first conduction type drift region is reduced, the hole concentration is increased, and the IGBT device can effectively suppress the short-circuit oscillation phenomenon.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and in particular to an IGBT device capable of suppressing short-circuit oscillation and a preparation method thereof. Background Art

[0002] IGBT (insulated gate bipolar transistor) is the core device of power electronic system. As the device changes from planar design to trench design, the trench spacing continues to decrease, the IGBT current density continues to increase, and its short-circuit performance becomes more and more important. When an IGBT short-circuits, the IGBT is required to be able to withstand high voltage and high current for a period of time (5-10μs) before the gate drive protection circuit successfully shuts down the IGBT. However, existing IGBT devices may fail due to short-circuit oscillation before the gate drive protection circuit is activated. Figure 1 The graph shows the change curves of VGE (gate-emitter voltage), IGE (gate-emitter current), and VCE (collector-emitter voltage) over time when a short circuit occurs in an existing IGBT device. Figure 1 As shown in the figure, under the short-circuit state, the VGE, IGE and VCE of the IGBT device all oscillate within 7-10μs.

[0003] This oscillation phenomenon is caused by the negative impedance inside the IGBT when a short circuit occurs. This negative impedance will continue to increase as the short circuit time increases, and eventually offset the positive resistance in the entire loop. With the participation of external parasitic parameters, the short circuit oscillation amplitude may be very large, thus damaging the device. In addition, this high-frequency oscillation also poses the risk of electromagnetic interference (EMI). Figure 2 This is the equivalent impedance (including parasitic parameters) spectrum of a traditional IGBT device as seen from the gate. It can be seen that the real part of the impedance is negative in a certain frequency range, that is, negative impedance appears inside the device.

[0004] Under the condition of the same parasitic parameters, the magnitude of negative impedance is considered to be related to the carrier ratio inside the IGBT. When the electron / hole concentration ratio decreases, the negative impedance generated by the device decreases, and the short-circuit oscillation phenomenon is weakened. One of the methods for suppressing short-circuit oscillation in the prior art is to increase the hole concentration in the drift region by increasing the injection efficiency of the collector, and reduce the negative impedance generated inside the device to suppress the short-circuit oscillation phenomenon. However, this method will increase the tail current, thereby increasing the turn-off loss and sacrificing the performance of the normal working state. In addition, the prior art also suppresses the short-circuit oscillation phenomenon by reducing the current density. When the current density is small, the negative impedance generated by the device will disappear and become a positive impedance. The disadvantage of this method is that it will cause the conductivity modulation effect of the drift region to weaken, resulting in an increase in the on-state loss. It can be seen from the above description that the current methods for suppressing the short-circuit oscillation phenomenon of the IGBT will sacrifice the working performance of the device. Therefore, how to suppress the short-circuit oscillation phenomenon of the IGBT device without changing the injection efficiency or current density is a problem that needs to be solved urgently. Summary of the invention

[0005] In view of the above problems and technical requirements, the inventors have proposed an IGBT device and a preparation method capable of suppressing short-circuit oscillation. The technical solution of the present invention is as follows:

[0006] An IGBT device capable of suppressing short-circuit oscillation comprises a semiconductor substrate and an active region prepared in the central region of the semiconductor substrate;

[0007] The semiconductor substrate includes a first conductivity type drift region, and the first conductivity type is N type;

[0008] The active area includes a plurality of parallel distributed cells, and any cell includes a plurality of carrier adjustment units;

[0009] The carrier adjustment unit is located in the first conductive type drift region, so that the electron concentration in the first conductive type drift region is reduced and the hole concentration is increased.

[0010] A further technical solution is that the carrier adjustment unit includes a first conductive type doping region and a second conductive type doping region located in the first conductive type doping region, and the second conductive type is P type;

[0011] The second conductive type doping region is isolated from the first conductive type drift region by the first conductive type doping region, and the doping concentration of the first conductive type doping region is greater than the doping concentration of the first conductive type drift region.

[0012] A further technical solution is that the cell includes two trench gate units;

[0013] A second conductive type floating region is disposed between the two trench gate units;

[0014] The second conductive type floating region is in contact with both trench gate units, and a field oxide layer is disposed above the second conductive type floating region;

[0015] All trench gate units are electrically connected to a gate metal for forming a gate on a semiconductor substrate.

[0016] A further technical solution thereof is characterized in that the carrier adjustment unit corresponds to the trench gate unit one by one, and the trench gate unit includes a cell trench;

[0017] The carrier adjustment unit covers the bottom of the corresponding cell trench, and the second conductive type doping region in the carrier adjustment unit contacts the bottom of the corresponding cell trench.

[0018] A further technical solution is that the trench gate unit also includes a gate oxide layer prepared on the inner wall of the cell trench, and gate polysilicon filled in the cell trench, and the gate polysilicon is insulated and isolated from the inner wall of the cell trench by the gate oxide layer.

[0019] A further technical solution is that a polysilicon bridge is arranged above the field oxide layer, the polysilicon bridge is in contact with the gate polysilicon in the two trench gate units, and the second conductive type floating region is insulated and isolated from the polysilicon bridge by the field oxide layer;

[0020] The polysilicon bridge is in ohmic contact with a gate metal on a semiconductor substrate for forming a gate.

[0021] A further technical solution is that a second conductive type base region is provided on a side of each cell trench away from the second conductive type floating region;

[0022] The second conductive type base region is provided with a first conductive type emitter region and a second conductive type emitter region, and the first conductive type emitter region is in contact with the corresponding cell trench sidewall;

[0023] The first conductive type emitter region and the second conductive type emitter region are both in ohmic contact with an emitter metal on the semiconductor substrate for forming an emitter.

[0024] A further technical solution is that a first conductive type buffer layer and a second conductive type collector region are also provided in the semiconductor substrate;

[0025] The first conductive type buffer layer is located between the first conductive type drift region and the second conductive type collector region, and the doping concentration of the first conductive type buffer layer is greater than the doping concentration of the first conductive type drift region;

[0026] The second conductive type collector region is in ohmic contact with a collector metal on the back side of the semiconductor substrate for forming a collector.

[0027] A method for preparing an IGBT device capable of suppressing short-circuit oscillation, which is used to prepare the above-mentioned IGBT device, and the method for preparing the IGBT device capable of suppressing short-circuit oscillation comprises:

[0028] A semiconductor substrate is provided, wherein the semiconductor substrate includes a first conductive type drift region, and a front cell process is performed on the front surface of the semiconductor substrate, wherein:

[0029] When the front side cell process is performed on the front side of the semiconductor substrate, an active area is prepared in the central area of ​​the semiconductor substrate, and a plurality of cells connected in parallel are prepared in the active area;

[0030] For any cell, it includes several carrier adjustment units;

[0031] The carrier adjustment unit is located in a first conductive type drift region, so as to reduce the electron concentration and increase the hole concentration in the first conductive type drift region, and the first conductive type is N type.

[0032] A further technical solution is that the unit cell includes two trench gate units, and the carrier adjustment unit corresponds to the trench gate unit in a one-to-one manner;

[0033] When preparing any trench gate unit, it includes preparing a cell trench in the first conductive type drift region;

[0034] When preparing any carrier adjustment unit, the method includes implanting first conductive type doping ions into the first conductive type drift region by using the corresponding cell trench bottom to form a first conductive type doping region;

[0035] After preparing the first conductive type doped region, the second conductive type doping ions are implanted into the first conductive type doped region using the corresponding cell groove bottom to form a second conductive type doped region, wherein the second conductive type is P type, and the first conductive type doped region and the second conductive type doped region are both in contact with the corresponding cell groove.

[0036] The beneficial technical effects of the present invention are:

[0037] The present invention provides an IGBT device capable of suppressing short-circuit oscillation, wherein a carrier adjustment unit is provided in an N-type drift region, so that the electron concentration in the N-type drift region is reduced and the hole concentration is increased, thereby reducing the concentration ratio of electrons to holes in the drift region, reducing the negative impedance generated by the IGBT device, and weakening the short-circuit oscillation phenomenon. The short-circuit oscillation phenomenon of the IGBT device is suppressed without changing the injection efficiency or current density. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1This is the curve of VGE, IGE and VCE changing with time when a short circuit occurs in a traditional IGBT device.

[0039] Figure 2 This is the equivalent impedance spectrum of a traditional IGBT device viewed from the gate.

[0040] Figure 3 It is a cross-sectional schematic diagram of an embodiment of an IGBT device capable of suppressing short-circuit oscillation provided by the present invention.

[0041] Figure 4 This is a simulation result diagram of the carrier concentration ratio inside the device provided by the present invention.

[0042] Figure 5 It is a simulation result diagram of the variation of VGE, IGE and VCE with time when a short circuit occurs in a conventional IGBT device provided by the present invention.

[0043] Figure 6 It is a simulation result diagram of the changes of VGE, IGE and VCE over time when the IGBT device capable of suppressing short-circuit oscillation provided by the present invention is short-circuited.

[0044] Figure 7-Figure 13 1 is a cross-sectional view of the process steps of an embodiment of a method for preparing an IGBT device capable of suppressing short-circuit oscillation provided by the present invention, wherein:

[0045] Figure 7 It is a cross-sectional view of an embodiment after the cell groove is prepared in the present invention.

[0046] Figure 8 It is a cross-sectional view of an embodiment of the present invention after the carrier adjustment unit is prepared.

[0047] Fig. 9 It is a cross-sectional view of an embodiment of the present invention after the polysilicon bridge is prepared.

[0048] Fig.10 It is a cross-sectional view of an embodiment of the present invention after the insulating dielectric layer is prepared.

[0049] Fig.11 It is a cross-sectional view of an embodiment of the present invention after preparing a P-type emitter region.

[0050] Fig.12 It is a cross-sectional view of an embodiment of the present invention after preparing the front metal layer.

[0051] Fig.13 It is a cross-sectional view of an embodiment of the present invention after the P-type collector region is prepared.

[0052] Figure numerals: 1-N-type drift region, 2-N-type buffer layer, 3-P-type collector region, 4-N-type doped region, 5-P-type doped region, 6-cell trench, 7-gate oxide layer, 8-gate polysilicon, 9-P-type floating region, 10-P-type base region, 11-N-type emitter region, 12-P-type emitter region, 13-field oxide layer, 14-polysilicon bridge, 15-insulating dielectric layer, 16-emitter metal, 17-prepared field oxide layer, 18-prepared N-type emitter region, 19-contact trench. DETAILED DESCRIPTION

[0053] The specific implementation of the present invention will be further described below in conjunction with the accompanying drawings.

[0054] The present invention provides an IGBT device capable of suppressing short-circuit oscillation. In one embodiment of the present invention, the IGBT device comprises a semiconductor substrate and an active region prepared in a central region of the semiconductor substrate;

[0055] The active region includes a plurality of parallel distributed cells, the semiconductor substrate includes an N-type drift region 1, and any cell includes a plurality of carrier adjustment units;

[0056] The carrier adjustment unit is located in the N-type drift region 1, so that the electron concentration of the N-type drift region 1 is reduced and the hole concentration is increased;

[0057] The carrier adjustment unit includes an N-type doping region 4 and a P-type doping region 5 located in the N-type doping region 4;

[0058] The P-type doping region 5 is isolated from the N-type drift region 1 by the N-type doping region 4 , and the doping concentration of the N-type doping region 4 is greater than the doping concentration of the N-type drift region 1 .

[0059] Specifically, the semiconductor substrate generally has a front side and a back side corresponding to the front side. In the present embodiment, the semiconductor substrate includes an N-type drift region 1, and the N-type drift region 1 corresponds to the front side of the semiconductor substrate, that is, the front side of the N-type drift region 1 is used as the front side of the semiconductor substrate. For an IGBT device, it generally includes an active area located in the semiconductor substrate and a terminal protection area surrounding the active area. The specific functions and distribution states of the active area and the terminal protection area may be consistent with the prior art. Generally, the active area includes a plurality of parallel distributed cells, and in the active area, the cells may generally adopt the same structural form. It should be noted that the IGBT devices described in this application are all N-type IGBT devices.

[0060] As can be seen from the background technology, the strength of the short-circuit oscillation phenomenon of the IGBT device is positively correlated with the negative impedance generated when the IGBT device is short-circuited. Under the condition of the same parasitic parameters, the negative impedance generated by the IGBT device is positively correlated with the concentration ratio of electrons and holes inside the IGBT device. The carrier adjustment unit reduces the electron concentration in the drift region and increases the hole concentration in the drift region to reduce the ratio of the electron concentration / hole concentration, so as to reduce the negative impedance generated when the IGBT device is short-circuited, thereby suppressing the short-circuit oscillation phenomenon of the IGBT device. In addition, in the present invention, by improving the device structure to adjust the carrier ratio of the N-type drift region 1, the short-circuit oscillation phenomenon of the IGBT device can be suppressed without changing the injection efficiency or current density, thereby avoiding sacrificing the normal working performance of the device while suppressing the short-circuit oscillation phenomenon.

[0061] The carrier adjustment unit includes an N-type doping region 4 and a P-type doping region 5 located in the N-type doping region 4, wherein the doping concentration of the N-type doping region 4 is greater than the doping concentration of the N-type drift region 1, and the P-type doping region 5 is isolated from the N-type drift region 1 by the N-type doping region 4, so that the P-type doping region 5 is only in contact with the N-type doping region 5 with a higher doping concentration, so as to ensure the adjustment effect of the carrier adjustment unit on the carrier ratio. In order to prevent the carrier adjustment unit from reducing the breakdown voltage of the IGBT device, preferably, the doping concentration of the N-type doping region 4 is one order of magnitude greater than the doping concentration of the N-type drift region 1, and the doping concentration of the P-type doping region 5 is the same as the doping concentration of the N-type doping region 4.

[0062] Furthermore, the cell includes two trench gate units, and a P-type floating region 9 is provided between the two trench gate units;

[0063] The P-type floating region 9 contacts both trench gate units, and a field oxide layer 13 is disposed above the P-type floating region 9;

[0064] All trench gate units are electrically connected to a gate metal for forming a gate on a semiconductor substrate.

[0065] Specifically, the P-type floating region 9 is located in the N-type drift region 1, and the P-type floating region 9 is not in contact with the carrier adjustment unit. The cell is a trench-type cell, including two trench gate units, each of which includes a cell trench 6, and the P-type floating region 9 is located between the two cell trenches 6 and in contact with the sidewalls of the two cell trenches 6. When the IGBT device is forward-conducted, the P-type floating region 9 can store a large number of holes to enhance the conductivity modulation effect, thereby reducing the conduction voltage drop, and at the same time, the large-area P-type floating region 9 can reduce the saturation current of the device.

[0066] For an IGBT device, the front side of the semiconductor substrate is generally provided with a gate metal for forming a gate and an emitter metal 16 for forming an emitter, and the back side of the semiconductor substrate is provided with a collector metal for forming a collector. The two trench gate units in the same cell are electrically connected to the gate metal for forming a gate on the semiconductor substrate. The manner in which the trench gate unit is electrically connected to the gate metal can refer to the following description.

[0067] Furthermore, the carrier adjustment unit corresponds to the trench gate unit one by one;

[0068] The carrier adjustment unit covers the bottom of the corresponding cell trench 6 , and the P-type doping region 5 in the carrier adjustment unit is in contact with the bottom of the corresponding cell trench 6 .

[0069] Since the proportion of the carrier concentration under the trench gate unit in the N-type drift region 1 has a more significant effect on the negative impedance of the IGBT device, a carrier adjustment unit is provided under each trench gate unit in this embodiment, and the carrier adjustment unit entirely covers the bottom of the corresponding cell trench 6. In specific implementation, the carrier adjustment unit may not correspond to the trench gate unit one by one, and may be located in the N-type drift region 1. In this embodiment, Figure 1 As shown, the cell trench 6 is a U-shaped trench, the P-type doping region 5 in the carrier adjustment unit covers a portion of the bottom of the corresponding cell trench 6, and the N-type doping region 4 in the carrier adjustment unit contacts the bottom of the cell trench 6 not covered by the P-type doping region 5, and extends to the outer side wall of the corresponding cell trench 6. When the carrier adjustment unit is located below the trench gate unit, it not only has a better carrier concentration adjustment effect, but also can further improve the withstand voltage of the IGBT device through the P-type doping region 5 in contact with the bottom of the cell trench 6.

[0070] Furthermore, the trench gate unit also includes a gate oxide layer 7 formed on the inner wall of the cell trench 6 , and a gate polysilicon 8 filled in the cell trench 6 . The gate polysilicon 8 is insulated and isolated from the inner wall of the cell trench 6 by the gate oxide layer 7 .

[0071] Specifically, the trench gate unit is electrically connected to the gate metal, that is, the gate polysilicon 8 in the trench gate unit is electrically connected to the gate metal, a polysilicon bridge 14 is arranged above the field oxide layer 13, the polysilicon bridge 14 is in contact with the gate polysilicon 8 in both trench gate units, the P-type floating region 9 is insulated and isolated from the polysilicon bridge 14 by the field oxide layer 13, and the polysilicon bridge 14 is in ohmic contact with the gate metal for forming the gate above the semiconductor substrate, so that the gate polysilicon 8 in the trench gate unit is electrically connected to the gate metal through the polysilicon bridge. Optionally, the material of the field oxide layer 13 can be silicon dioxide.

[0072] Furthermore, a P-type base region 10 is disposed on one side of each cell trench 6 away from the P-type floating region 9;

[0073] An N-type emitter region 11 and a P-type emitter region 12 are disposed in the P-type base region 10, and the N-type emitter region 11 is in contact with the sidewall of the corresponding cell trench 6;

[0074] The N-type emitter region 11 and the P-type emitter region 12 are both in ohmic contact with an emitter metal 16 on the semiconductor substrate for forming an emitter.

[0075] Specifically, the doping concentration of the N-type emitter region 11 is greater than the doping concentration of the N-type drift region 1, and the doping concentration of the P-type emitter region 12 is greater than the doping concentration of the P-type base region 10. For the N-type emitter region 11 and the P-type emitter region 12 located in the same P-type base region 10, the N-type emitter region 11 is located between the corresponding cell trench 6 and the P-type emitter region 12. The P-type base region 10 is located in the N-type drift region 1, and the junction depth of the P-type base region 10 is generally greater than the junction depth of the P-type floating region 9.

[0076] Furthermore, an N-type buffer layer 2 and a P-type collector region 3 are also provided in the semiconductor substrate;

[0077] The N-type buffer layer 2 is located between the N-type drift region 1 and the P-type collector region 3, and the doping concentration of the N-type buffer layer 2 is greater than the doping concentration of the N-type drift region 1;

[0078] The P-type collector region 3 is in ohmic contact with the collector metal on the back side of the semiconductor substrate for forming a collector.

[0079] Specifically, the P-type collector region 3 traverses the active region, and the back side of the P-type collector region 3 serves as the back side of the semiconductor substrate. On the cross section of the active region, the thickness of the N-type drift region 1 is greater than the thickness of the N-type buffer layer 2 .

[0080] In order to verify the inhibitory effect of the IGBT device provided by the present invention on short-circuit oscillation, the present invention established a simulation software Figure 1 The simulation model of the IGBT device of the structure shown and the simulation model of the traditional IGBT device are simulated, and the changes of the carrier concentration ratio inside the device and the VGE (gate-emitter voltage), IGE (gate-emitter current), and VCE (collector-emitter voltage) over time when the device is short-circuited are simulated respectively. The simulation software can use Synopsys SentaurusTCAD.

[0081] Specifically, when simulating and testing the carrier concentration ratio inside the device, the injection efficiency of the collector of the traditional IGBT device simulation model is set to the first injection efficiency and the second injection efficiency, respectively, the first injection efficiency is less than the second injection efficiency, and the variation of the carrier concentration ratio inside the traditional IGBT device with the depth of the device is simulated at the first injection efficiency and the second injection efficiency. At the same time, the injection efficiency of the collector of the IGBT device simulation model with a carrier adjustment unit is set to the first injection efficiency, and the variation of the carrier concentration ratio inside the device with the depth of the device is simulated. The simulation results are as follows: Figure 4 As shown, Figure 4 The device 1 with a higher injection efficiency of the traditional structure represents a traditional IGBT device with a collector injection efficiency of the second injection efficiency, the device 2 with a lower injection efficiency of the traditional structure represents a traditional IGBT device with a collector injection efficiency of the first injection efficiency, and the device 3 with a lower injection efficiency of the new structure represents an IGBT device with a carrier adjustment unit and a collector injection efficiency of the first injection efficiency. Figure 4 It can be seen that the IGBT device capable of suppressing short-circuit oscillation provided by the present invention can also achieve the effect of reducing the electron concentration / hole concentration ratio in the drift region without changing the collector injection efficiency.

[0082] Figure 5 and Figure 6 The simulation results of the VGE, IGE and VCE of the conventional IGBT device and the IGBT device provided by the present invention when the device is short-circuited are shown respectively. Figure 5 and Figure 6 It can be seen that when a short circuit occurs, there is almost no short-circuit oscillation phenomenon in the VGE, IGE, and VCE of the IGBT device provided by the present invention before the device is turned off, indicating that the IGBT device capable of suppressing short-circuit oscillation provided by the present invention has a good short-circuit oscillation suppression effect.

[0083] For the above-mentioned IGBT device capable of suppressing short-circuit oscillation, the present invention provides a method for preparing the IGBT device capable of suppressing short-circuit oscillation, and the method for preparing the IGBT device capable of suppressing short-circuit oscillation comprises:

[0084] A semiconductor substrate is provided, wherein the semiconductor substrate comprises an N-type drift region 1, and a front cell process is performed on the front side of the semiconductor substrate, wherein:

[0085] When the front side cell process is performed on the front side of the semiconductor substrate, an active area is prepared in the central area of ​​the semiconductor substrate, and a plurality of cells connected in parallel are prepared in the active area;

[0086] For any cell, it includes several carrier adjustment units;

[0087] The carrier adjustment unit is located in the N-type drift region 1, so that the electron concentration in the N-type drift region 1 is reduced and the hole concentration is increased;

[0088] The carrier adjustment unit includes an N-type doping region 4 and a P-type doping region 5 located in the N-type doping region 4 . The doping concentration of the N-type doping region 4 is greater than the doping concentration of the N-type drift region 1 .

[0089] Specifically, the cell includes two trench gate units, the carrier adjustment unit and the trench gate unit are in one-to-one correspondence, and when preparing any trench gate unit, it includes preparing a cell trench 6 in the N-type drift region 1, and when preparing any carrier adjustment unit, it includes using the corresponding cell trench 6 groove bottom to implant N-type doping ions in the N-type drift region 1 to form an N-type doping region 4. After the N-type doping region 4 is prepared, the corresponding cell trench 6 groove bottom is used to implant P-type doping ions in the N-type doping region 4 to form a P-type doping region 5, and the P-type doping region 5 is isolated from the N-type drift region 1 by the N-type doping region 4, and the P-type doping region 5 and the N-type doping region 4 are both in contact with the corresponding cell trench 6.

[0090] Furthermore, the method for preparing the IGBT device capable of suppressing short-circuit oscillations further includes performing a backside process on the backside of the semiconductor substrate. Generally, the frontside cell process is performed first and then the backside cell process.

[0091] Figure 7-Figure 13 An embodiment of the process steps for preparing the above-mentioned IGBT device capable of suppressing short-circuit oscillation is shown below. Figure 7-Figure 13 The specific process steps are described in detail. Figure 7-Figure 13 Only Figure 3 The half-cell structure of the cell shown in FIG. 1 is the portion from the center of the P-type floating region 9 to the P-type base region 10 corresponding to a certain trench gate unit. The process conditions of other portions may refer to the corresponding drawings.

[0092] like Figure 7 As shown, a semiconductor substrate is provided. In this embodiment, the semiconductor substrate provided includes only an N-type drift region 1, that is, the semiconductor substrate provided as a whole is used as the N-type drift region 1. A P-type floating region 9 is prepared in the N-type drift region 1 by ion implantation and high-temperature push-junction process. The P-type floating region 9 extends vertically downward from the front side of the semiconductor substrate, that is, the front side of the N-type drift region 1. An oxide layer is grown on the front side of the semiconductor substrate and selectively etched to prepare a preparatory field oxide layer 17, and the preparatory field oxide layer 17 is located above the P-type floating region 9. Cell trenches 6 are etched on both sides of the P-type floating region 9, and the P-type floating region 9 is located between the two cell trenches 6.

[0093] like Figure 8As shown, for any cell trench 6, N-type doping ions are implanted into the N-type drift region 1 using the bottom of the cell trench 6 to form an N-type doping region 4. At this time, the N-type doping region 4 covers the bottom of the cell trench 6 and extends to the sidewall of the cell trench 6. After the N-type doping region 4 is prepared, P-type doping ions are implanted into the N-type doping region 4 using the bottom of the corresponding cell trench 6 to invert part of the N-type doping region 4 to form a P-type doping region 5. The P-type doping region 5 is isolated from the N-type drift region 1 by the N-type doping region 4, and the P-type doping region 5 is in contact with the bottom of the cell trench 6. The doping concentration of the formed N-type doping region 4 is greater than the doping concentration of the N-type drift region 1.

[0094] like Fig. 9 As shown, an oxide layer is formed on the inner wall of the cell trench 6 and the front side of the semiconductor substrate by thermal oxidation, and polysilicon is deposited on the front side of the semiconductor substrate and in the cell trench 6 where the oxide layer is prepared. The oxide layer on the front side of the semiconductor substrate located at the side of the cell trench 6 away from the P-type floating region 9 is removed by etching to form a field oxide layer 13 above the P-type floating region 9, and a gate oxide layer 7 is formed on the inner wall of the cell trench 6. When the oxide layer on the front side of the semiconductor substrate located at the side of the cell trench 6 away from the P-type floating region 9 is removed by etching, the polysilicon on the front side of the semiconductor substrate located at the side of the cell trench 6 away from the P-type floating region 9 is removed by etching at the same time, so as to prepare a polysilicon bridge 14 and gate polysilicon 8 at the same time, and form an injection window for the P-type base region 10, the polysilicon bridge 14 is in contact with the gate polysilicon 8, and the gate polysilicon 8 is insulated and isolated from the inner wall of the cell trench 6 by the gate oxide layer 7.

[0095] like Fig.10 As shown, the P-type base region 10 is implanted into the N-type drift region 1 using the implantation window of the P-type base region 10 and subjected to high temperature annealing to form the P-type base region 10, the junction depth of the P-type base region 10 being greater than the P-type floating region 9. After the P-type base region 10 is prepared, N-type doping ions are implanted into the P-type base region and subjected to high temperature annealing to form a preliminary N-type emitter region 18, the preliminary N-type emitter region 18 being in contact with the corresponding cell trench 6. Oxide is deposited on the semiconductor substrate on which the preliminary N-type emitter region 18 is prepared to form an insulating dielectric layer 15.

[0096] like Fig.11As shown, the insulating dielectric layer 15 and the prepared N-type emitter region 18 are selectively etched to prepare a contact groove 19, and the area of ​​the prepared N-type emitter region 18 that is not etched is used as the N-type emitter region 18. The bottom of the contact groove 19 is located in the P-type base region 10, and the bottom of the contact groove 19 is used as an injection window to inject P-type impurities into the P-type base region 10 and perform high-temperature annealing to form a P-type emitter region 12, and the P-type emitter region 12 extends vertically downward from the bottom of the contact groove 19, and the doping concentration of the P-type emitter region 12 is greater than the doping concentration of the P-type base region 10. The specific process conditions of ion implantation and high-temperature annealing can be selected according to actual needs to meet the preparation requirements of the P-type emitter region 12.

[0097] like Fig.12 As shown, a front metal layer is deposited on the insulating dielectric layer 15 and patterned to prepare a gate metal for forming a gate and a source metal 16 for forming a source. Fig.12 As shown in the figure, a source metal 16 is also deposited in the contact trench 19, and the source metal 16 deposited in the contact trench 19 is in ohmic contact with both the N-type emitter region 11 and the P-type emitter region 12. The polysilicon bridge 14 is in ohmic contact with the gate metal, and the form of the ohmic contact between the polysilicon bridge 14 and the gate metal can be consistent with the prior art.

[0098] The semiconductor substrate is turned over to perform backside processing on the backside of the semiconductor substrate, such as Fig.13 As shown, the back process includes preparing a P-type collector region 3 on the back of the semiconductor substrate by ion implantation and high-temperature push-junction process, and injecting N-type doping ions into the P-type collector region 3 to invert the part of the P-type collector region 3 close to the N-type drift region 1 to N-type, so as to prepare an N-type buffer layer 2. The N-type buffer layer 2 is located between the N-type drift region 1 and the P-type collector region 3, and is in contact with both the N-type drift region 1 and the P-type collector region 3. Metal is deposited on the back of the semiconductor substrate on which the N-type buffer layer 2 is prepared to form a collector metal. The collector metal is not Fig.13 The P-type collector region 3 is in ohmic contact with the collector metal.

[0099] It should be noted that the words "front", "rear", "left", "right", "upper" and "lower" used in the above description refer to directions in the drawings of the present application specification, and the words "front" and "back", "inner" and "outer" refer to directions toward or away from a specific component, respectively. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.

[0100] The above is only a preferred embodiment of the present invention, and the present invention is not limited to the above embodiments. It is understood that other improvements and changes directly derived or associated by those skilled in the art without departing from the spirit and concept of the present invention should be considered to be included in the protection scope of the present invention.

Claims

1. An IGBT device capable of suppressing short-circuit oscillation, characterized in that: It includes a semiconductor substrate and an active area prepared in the central area of ​​the semiconductor substrate; The semiconductor substrate includes a first conductivity type drift region, and the first conductivity type is N type; The active area includes a plurality of parallel distributed cells, and any cell includes a plurality of carrier adjustment units; The carrier adjustment unit is located in the first conductive type drift region, so that the electron concentration in the first conductive type drift region is reduced and the hole concentration is increased.

2. The IGBT device capable of suppressing short-circuit oscillation according to claim 1, characterized in that: The carrier adjustment unit includes a first conductive type doping region and a second conductive type doping region located in the first conductive type doping region, and the second conductive type is P type; The second conductive type doping region is isolated from the first conductive type drift region by the first conductive type doping region, and the doping concentration of the first conductive type doping region is greater than the doping concentration of the first conductive type drift region.

3. The IGBT device capable of suppressing short-circuit oscillation according to claim 2, characterized in that: The cell includes two trench gate units; A second conductive type floating region is disposed between the two trench gate units; The second conductive type floating region is in contact with both trench gate units, and a field oxide layer is disposed above the second conductive type floating region; All trench gate units are electrically connected to a gate metal for forming a gate on a semiconductor substrate.

4. The IGBT device capable of suppressing short-circuit oscillation according to claim 3, characterized in that: The carrier adjustment unit corresponds to the trench gate unit one by one, and the trench gate unit includes a cell trench; The carrier adjustment unit covers the bottom of the corresponding cell trench, and the second conductive type doping region in the carrier adjustment unit contacts the bottom of the corresponding cell trench.

5. The IGBT device capable of suppressing short-circuit oscillation according to claim 4, characterized in that: The trench gate unit also includes a gate oxide layer prepared on the inner wall of the cell trench, and gate polysilicon filled in the cell trench, and the gate polysilicon is insulated and isolated from the inner wall of the cell trench by the gate oxide layer.

6. The IGBT device capable of suppressing short-circuit oscillation according to claim 5, characterized in that: A polysilicon bridge is arranged above the field oxide layer, the polysilicon bridge is in contact with the gate polysilicon in the two trench gate units, and the second conductive type floating region is insulated and isolated from the polysilicon bridge by the field oxide layer; The polysilicon bridge is in ohmic contact with a gate metal on a semiconductor substrate for forming a gate.

7. The IGBT device capable of suppressing short-circuit oscillation according to claim 4, characterized in that: A second conductive type base region is disposed on one side of each cell trench away from the second conductive type floating region; The second conductive type base region is provided with a first conductive type emitter region and a second conductive type emitter region, and the first conductive type emitter region is in contact with the corresponding cell trench sidewall; The first conductive type emitter region and the second conductive type emitter region are both in ohmic contact with an emitter metal on the semiconductor substrate for forming an emitter.

8. The IGBT device capable of suppressing short-circuit oscillation according to claim 1, characterized in that: The semiconductor substrate is also provided with a first conductive type buffer layer and a second conductive type collector region; The first conductive type buffer layer is located between the first conductive type drift region and the second conductive type collector region, and the doping concentration of the first conductive type buffer layer is greater than the doping concentration of the first conductive type drift region; The second conductive type collector region is in ohmic contact with a collector metal on the back side of the semiconductor substrate for forming a collector.

9. A method for preparing an IGBT device capable of suppressing short-circuit oscillation, characterized in that: The method for preparing the IGBT device capable of suppressing short-circuit oscillation is used for preparing the IGBT device according to any one of claims 1 to 8, wherein the method comprises: A semiconductor substrate is provided, wherein the semiconductor substrate includes a first conductive type drift region, and a front cell process is performed on the front surface of the semiconductor substrate, wherein: When the front side cell process is performed on the front side of the semiconductor substrate, an active area is prepared in the central area of ​​the semiconductor substrate, and a plurality of cells connected in parallel are prepared in the active area; For any cell, it includes several carrier adjustment units; The carrier adjustment unit is located in a first conductive type drift region, so as to reduce the electron concentration and increase the hole concentration in the first conductive type drift region, and the first conductive type is N type.

10. The method for preparing an IGBT device capable of suppressing short-circuit oscillation according to claim 9, characterized in that: The unit cell includes two trench gate units, and the carrier adjustment unit corresponds to the trench gate unit in a one-to-one manner; When preparing any trench gate unit, it includes preparing a cell trench in the first conductive type drift region; When preparing any carrier adjustment unit, the method includes implanting first conductive type doping ions into the first conductive type drift region by using the corresponding cell trench bottom to form a first conductive type doping region; After preparing the first conductive type doped region, the second conductive type doping ions are implanted into the first conductive type doped region using the corresponding cell groove bottom to form a second conductive type doped region, wherein the second conductive type is P type, and the first conductive type doped region and the second conductive type doped region are both in contact with the corresponding cell groove.

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