Pseudo self-aligned p-type gallium nitride gate high electron mobility transistor and preparation method thereof

Abstract

The invention discloses a pseudo self-aligned p-type gallium nitride gate high electron mobility transistor and a preparation method thereof, and relates to the technical field of transistors. According to the method, an existing epitaxial wafer is selected, mesa isolation and surface treatment are carried out, a p-GaN cap layer is etched to expose a contact region, a passivation layer is deposited, a mask material in a gate region is removed, n-type ohmic contact metal is evaporated to form a source electrode and a drain electrode, gate contact metal is evaporated, and finally the pseudo self-aligned p-type gallium nitride gate high-electron-mobility transistor is prepared. On the basis of a conventional high-electron-mobility transistor, after pGaN is etched, a mask material is continuously used for masking, after a passivation layer is epitaxially grown, the epitaxially grown passivation layer is selectively stripped through the mask material, and a pGaN cap layer is exposed, so that grid pseudo self-alignment is realized.

Description

Technical Field

[0001] The present application relates to the field of transistor technology, and in particular to a pseudo self-aligned p-type gallium nitride gate high electron mobility transistor and a preparation method thereof. Background Art

[0002] Conventional pGaN gate HEMT devices work using a two-dimensional electron gas with very high mobility, and can be used for ultra-high frequency and ultra-high speed operation. Currently, the two most mature pGaN gate HEMT manufacturing processes can be divided into two types: the gate-last error alignment process and the gate-first self-alignment process. The gate-last error alignment process is to achieve the deposition of gate metal by aligning the alignment mark after the drain-source high-temperature ohmic contact. Although this solution can repair the surface state and low ohmic contact after etching through high temperature, it has high requirements for the alignment of the lithography equipment and requires sufficient alignment error to be reserved.

[0003] However, the gate-first self-aligned process uses metal as a hard mask for the gate to simultaneously achieve the etching of the pGaN cap layer and the aligned deposition of the gate metal. However, due to the presence of the gate metal, most surface treatment processes cannot be used after the device is etched. Summary of the invention

[0004] The purpose of the present application is to provide a pseudo self-aligned p-type gallium nitride gate high electron mobility transistor and a preparation method thereof, which can achieve gate pseudo self-alignment.

[0005] To achieve the above objectives, this application provides the following solutions:

[0006] In a first aspect, the present application provides a method for preparing a pseudo self-aligned p-type gallium nitride gate high electron mobility transistor, comprising:

[0007] An epitaxial wafer having formed a substrate, a buffer layer, a GaN channel layer, an AlGaN barrier layer and a p-GaN cap layer is selected.

[0008] The epitaxial wafer on which the substrate, the buffer layer, the GaN channel layer, the AlGaN barrier layer and the p-GaN cap layer have been formed is subjected to mesa isolation.

[0009] Perform surface treatment on the device with completed mesa isolation.

[0010] Using the mask material, the p-GaN cap layer is etched to expose the contact areas of the source and drain electrodes.

[0011] The device surface is processed without removing or damaging the gate mask material.

[0012] On the basis of the gate mask material, a passivation layer is deposited by PVD or CVD.

[0013] The mask material in the gate area is removed by lift-off.

[0014] The n-type ohmic contact metal is evaporated on the drain electrode and source electrode area windows by electron beam evaporation, thermal evaporation or magnetron sputtering process, and high-temperature annealing is performed to form the source and drain electrodes.

[0015] The gate contact metal is evaporated on the gate electrode region window by electron beam evaporation, thermal evaporation or magnetron sputtering process to obtain a prepared pseudo self-aligned p-type gallium nitride gate high electron mobility transistor.

[0016] In a second aspect, the present application provides a pseudo self-aligned p-type gallium nitride gate high electron mobility transistor, which includes: a substrate, a buffer layer, a GaN channel layer, an AlGaN barrier layer, a p-GaN cap layer, a passivation layer, a gate, a source and a drain.

[0017] The buffer layer covers the substrate; the GaN channel layer covers the buffer layer; the AlGaN barrier layer covers the GaN channel layer; a source and a drain are provided at both ends of the AlGaN barrier layer; the p-GaN cap layer is located on the AlGaN barrier layer and is not connected to the source and the drain; the passivation layer is located above the AlGaN barrier layer and a portion of the p-GaN cap layer; and the gate is located above the p-GaN cap layer and a portion of the passivation layer.

[0018] According to the specific embodiments provided in this application, this application discloses the following technical effects:

[0019] The present application proposes a pseudo self-aligned p-type gallium nitride gate high electron mobility transistor and a preparation method thereof, the method comprising: firstly selecting an epitaxial wafer having formed a substrate, a buffer layer, a GaN channel layer, an AlGaN barrier layer and a p-GaN cap layer; then, performing a mesa isolation process on these layers to enhance the independence of the device; then, finely processing the device surface after the mesa isolation to optimize the subsequent process effect; using a mask material to accurately etch the p-GaN cap layer to accurately expose the contact area between the source and drain electrodes; performing a surface treatment on the device without removing or damaging the gate mask material; based on the treatment The gate mask material after treatment is used to deposit a passivation layer using PVD or CVD technology to enhance the stability and protection of the device; the mask material in the gate area is cleverly removed through the lift-off process to demonstrate precise process control; advanced processes such as electron beam evaporation, thermal evaporation or magnetron sputtering are used to evaporate n-type ohmic contact metal on the windows of the drain electrode and source electrode regions, and after high-temperature annealing, high-quality source and drain electrodes are formed; similarly, on the windows of the gate electrode region, the gate contact metal is evaporated using the above process, and finally a pseudo-self-aligned p-type gallium nitride gate high electron mobility transistor with a compact structure and excellent performance is prepared. Based on the conventional p-GaN gate HEMT preparation process, the present application creatively introduces a mask material for masking after etching the p-GaN cap layer, and then epitaxially grows a passivation layer. Through the selective stripping of the mask material, the p-GaN cap layer is accurately exposed, thereby achieving pseudo-self-alignment of the gate, greatly improving the performance and reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1 The present invention is a schematic flow chart of a method for preparing a pseudo self-aligned p-type gallium nitride gate high electron mobility transistor provided in an embodiment of the present application.

[0022] Figure 2 This is an alternative process flow chart provided in one embodiment of the present application.

[0023] Figure 3 A schematic diagram of a three-dimensional structure of a pseudo self-aligned p-type gallium nitride gate high electron mobility transistor provided in an embodiment of the present application.

[0024] Figure 4 It is a cross-sectional view of a cut surface 1 of a pseudo self-aligned p-type gallium nitride gate high electron mobility transistor provided in an embodiment of the present application.

[0025] Figure 5 It is a cross-sectional view of a cut surface 2 of a pseudo self-aligned p-type GaN gate high electron mobility transistor provided in an embodiment of the present application.

[0026] Figure 6 It is a cross-sectional view of a cut surface 3 of a pseudo self-aligned p-type GaN gate high electron mobility transistor provided in an embodiment of the present application.

[0027] Figure 7 An alternative process flow provided in an embodiment of the present application Figure 1 .

[0028] Figure 8 An alternative process flow provided in an embodiment of the present application Figure 2 .

[0029] Fig. 9 An alternative process flow provided in an embodiment of the present application Figure 3 .

[0030] Fig.10 An alternative process flow provided in an embodiment of the present application Figure 4 .

[0031] Fig.11 An alternative process flow provided in an embodiment of the present application Figure 5 .

[0032] Fig.12 An alternative process flow provided in an embodiment of the present application Figure 6 .

[0033] Fig.13 An alternative process flow provided in an embodiment of the present application Figure 7 . DETAILED DESCRIPTION

[0034] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0035] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0036] Embodiment 1

[0037] like Figure 1As shown, this embodiment provides a method for preparing a pseudo self-aligned p-type gallium nitride gate high electron mobility transistor, comprising:

[0038] Step 101: Select an epitaxial wafer having formed thereon a substrate, a buffer layer, a GaN channel layer, an AlGaN barrier layer and a p-GaN cap layer.

[0039] Step 102: performing mesa isolation on the epitaxial wafer on which the substrate, buffer layer, GaN channel layer, AlGaN barrier layer and p-GaN cap layer have been formed.

[0040] Step 103: Performing surface treatment on the device with completed mesa isolation.

[0041] Step 104: using a mask material, the p-GaN cap layer is etched to expose contact regions of the source and drain electrodes.

[0042] Step 105: Performing surface treatment on the device without removing or damaging the gate mask material.

[0043] Step 106: depositing a passivation layer on the basis of the gate mask material by PVD or CVD.

[0044] Step 107: Remove the mask material in the gate region by lift-off.

[0045] Step 108: Using electron beam evaporation, thermal evaporation or magnetron sputtering technology, evaporate n-type ohmic contact metal on the drain electrode and source electrode area windows, and anneal at high temperature to form the source and drain.

[0046] Step 109: using electron beam evaporation, thermal evaporation or magnetron sputtering technology to evaporate gate contact metal on the gate electrode region window to obtain a prepared pseudo self-aligned p-type gallium nitride gate high electron mobility transistor.

[0047] In some embodiments, when performing a surface treatment step on a device that has completed mesa isolation, the present embodiment adopts a variety of treatment methods, including but not limited to: using HCl (hydrogen chloride), H 2 SO 4 +H 2 O 2 (mixture of sulfuric acid and hydrogen peroxide), BOE (buffered oxide etchant), aqua regia, TMAH and NH 4 OH, etc.

[0048] The above treatment method is also used when treating the surface damage after etching of pGaN.

[0049] In some embodiments, when an n-type ohmic contact metal is evaporated on the drain electrode and source electrode area windows and annealed at high temperature to form the source and drain electrodes, the n-type ohmic contact metal used is Ti / Al, Ti / Al / Ni / Au or Ti / Al / Ti / Au.

[0050] In some specific examples, such as Figure 2 As shown in the alternative process flow diagram, during the preparation process, this embodiment selects an epitaxial wafer comprising a formed substrate, a buffer layer, a GaN channel layer, an AlGaN barrier layer and a p-GaN cap layer as the basic material. Subsequently, this embodiment uses a mask material to finely etch the p-GaN cap layer to accurately expose the contact area between the source electrode and the drain electrode. Next, this embodiment pre-treats the surface with a gate mask material to ensure the smooth progress of subsequent steps. On this basis, this embodiment uses PVD (physical vapor deposition) or CVD (chemical vapor deposition) technology to accurately deposit a passivation layer to enhance the protection performance of the device. Subsequently, this embodiment uses lift-off technology to cleverly remove the mask material in the gate area to make room for subsequent process steps. Next, this embodiment uses high-precision processes such as electron beam evaporation, thermal evaporation or magnetron sputtering to precisely evaporate n-type ohmic contact metal (such as Ti / Al, Ti / Al / Ni / Au or Ti / Al / Ti / Au) on the windows in the drain electrode and source electrode regions, and forms stable source and drain electrodes through high-temperature annealing. Finally, this embodiment again uses electron beam evaporation, thermal evaporation or magnetron sputtering technology to evaporate gate contact metal on the window in the gate electrode region to complete the key steps of the entire process flow.

[0051] Embodiment 2

[0052] like Figure 3 As shown, this embodiment provides a pseudo self-aligned p-type gallium nitride gate high electron mobility transistor, which includes: a substrate, a buffer layer, a GaN channel layer, an AlGaN barrier layer, a p-GaN cap layer, a passivation layer, a gate, a source and a drain.

[0053] The buffer layer covers the substrate; the GaN channel layer covers the buffer layer; the AlGaN barrier layer covers the GaN channel layer; a source and a drain are provided at both ends of the AlGaN barrier layer; the p-GaN cap layer is located on the AlGaN barrier layer and is not connected to the source and the drain; the passivation layer is located above the AlGaN barrier layer and a portion of the p-GaN cap layer; and the gate is located above the p-GaN cap layer and a portion of the passivation layer.

[0054] Wherein, in some embodiments, Figure 4-Figure 6As shown, the entire structure includes a substrate, a buffer layer, a GaN channel layer (UID-GaN channel layer), an AlGaN barrier layer, a p-GaN cap layer, a passivation layer, a gate, a source, and a drain from bottom to top. The source and drain are provided at both ends of the AlGaN barrier layer. The substrate is placed at the bottom of the entire structure and plays a supporting role. It may be, but not limited to, a silicon substrate, a sapphire substrate, a silicon carbide (SiC) substrate, or a self-supporting gallium nitride substrate. The buffer layer is located on the substrate and may be, but not limited to, a gallium nitride layer doped with iron (Fe) or carbon (C) or an Al(Ga)N / GaN superlattice structure. The GaN channel layer is located above the buffer layer. The AlGaN barrier layer is above the GaN channel layer and generates a two-dimensional electron gas (2DEG) on the side close to the GaN channel layer through piezoelectric polarization and spontaneous polarization effects at the interface between the AlGaN barrier layer and the GaN channel layer. The p-GaN cap layer is located on the AlGaN barrier layer, and the generation of 2DEG at the AlGaN / GaN interface is suppressed through the piezoelectric polarization and spontaneous polarization effect at the GaN / AlGaN interface and the p-type doping of the p-GaN cap layer itself, thereby realizing an enhanced n-FET device, wherein the p-GaN contact can be an ohmic contact, a Schottky contact, a dielectric layer isolation (MIS) and other methods. The passivation layer is located above the AlGaN barrier layer and part of the p-GaN cap layer, and may use but is not limited to silicon nitride (Si 3 N 4 ), aluminum nitride (AlN), aluminum oxide (Al 2 O 3 ), magnesium oxide (MgO) or silicon oxide (SiO 2 ) is used as the insulating layer material. In order to achieve a better stripping effect, the etching mask layer and the passivation layer should have a good chemical etching selectivity ratio to achieve the stripping process of the passivation layer.

[0055] Furthermore, in some embodiments, Figure 7-Figure 13 As shown, there are seven other alternative process flows, as follows:

[0056] Among them, Figure 7 Alternative process flow shown Figure 1 , the specific steps are as follows:

[0057] Step 1: Select an epitaxial wafer having formed a substrate, a buffer layer, a GaN channel layer, an AlGaN barrier layer and a p-GaN cap layer.

[0058] Step 2: Performing mesa isolation on the epitaxial wafer on which the substrate, buffer layer, GaN channel layer, AlGaN barrier layer and p-GaN cap layer have been formed.

[0059] Step 3: Surface treatment of the device with completed mesa isolation.

[0060] Step 4: Use a “T”-shaped or inverted triangle-shaped single-layer mask material to protect the gate area, and etch the p-GaN cap layer to remove the p-GaN cap layer in the non-gate area.

[0061] Step 5: Surface treatment of the device without removing or damaging the gate mask material.

[0062] Step 6: On the basis of the gate mask material, a passivation layer is deposited by PVD or CVD. Due to the narrowness below the mask layer, the passivation layer can be partially deposited on the surface of the p-GaN gate, achieving a better passivation effect.

[0063] Step 7: Remove the mask material in the gate area by lift-off.

[0064] Step 8: Etch the passivation layer to expose the contact areas of the source and drain electrodes.

[0065] Step 9: Using electron beam evaporation, thermal evaporation or magnetron sputtering process, evaporate the gate contact metal on the gate electrode region window to obtain the prepared pseudo self-aligned p-type gallium nitride gate high electron mobility transistor.

[0066] Among them, Figure 8 Alternative process flow shown Figure 2 , the specific steps are as follows:

[0067] Step 1: Select an epitaxial wafer having formed a substrate, a buffer layer, a GaN channel layer, an AlGaN barrier layer and a p-GaN cap layer.

[0068] Step 2: Performing mesa isolation on the epitaxial wafer on which the substrate, buffer layer, GaN channel layer, AlGaN barrier layer and p-GaN cap layer have been formed.

[0069] Step 3: Surface treatment of the device with completed mesa isolation.

[0070] Step 4: Use a mask material to protect the gate area and etch the p-GaN cap layer to remove the p-GaN cap layer in the non-gate area.

[0071] Step 5: Surface treatment of the device without removing or damaging the gate mask material.

[0072] Step 6: On the basis of the gate mask material, a passivation layer is deposited by PVD or CVD.

[0073] Step 7: Remove the mask material in the gate area by lift-off.

[0074] Step 8: Deposit a gate dielectric layer by PVD or CVD to provide the device gate with better passivation and voltage resistance.

[0075] Step 9: Etch the dielectric layer and the passivation layer to expose the contact areas of the source and drain electrodes.

[0076] Step 10: Using electron beam evaporation, thermal evaporation or magnetron sputtering process, evaporate the gate contact metal on the gate electrode region window to obtain a prepared pseudo self-aligned p-type gallium nitride gate high electron mobility transistor.

[0077] Among them, Fig. 9 Alternative process flow shown Figure 3 , the specific steps are as follows:

[0078] Step 1: Select an epitaxial wafer having formed a substrate, a buffer layer, a GaN channel layer, an AlGaN barrier layer and a p-GaN cap layer.

[0079] Step 2: Performing mesa isolation on the epitaxial wafer on which the substrate, buffer layer, GaN channel layer, AlGaN barrier layer and p-GaN cap layer have been formed.

[0080] Step 3: Surface treatment of the device with completed mesa isolation.

[0081] Step 4: Use a “T”-shaped or inverted triangle-shaped single-layer mask material to protect the gate area, and etch the p-GaN cap layer to remove the p-GaN cap layer in the non-gate area.

[0082] Step 5: Surface treatment of the device without removing or damaging the gate mask material.

[0083] Step 6: On the basis of the gate mask material, a passivation layer is deposited by PVD or CVD. Due to the narrowness below the mask layer, the passivation layer can be partially deposited on the surface of the p-GaN gate, achieving a better passivation effect.

[0084] Step 7: Remove the mask material in the gate area by lift-off.

[0085] Step 8: Deposit a gate dielectric layer by PVD or CVD to provide the device gate with better passivation and voltage resistance.

[0086] Step 9: Etch the dielectric layer and the passivation layer to expose the contact areas of the source and drain electrodes.

[0087] Step 10: Using electron beam evaporation, thermal evaporation or magnetron sputtering process, evaporate the gate contact metal on the gate electrode region window to obtain a prepared pseudo self-aligned p-type gallium nitride gate high electron mobility transistor.

[0088] Among them, Fig.10 Alternative process flow shown Figure 4 , the specific steps are as follows:

[0089] Step 1: Select an epitaxial wafer having formed a substrate, a buffer layer, a GaN channel layer, an AlGaN barrier layer and a p-GaN cap layer.

[0090] Step 2: Performing mesa isolation on the epitaxial wafer on which the substrate, buffer layer, GaN channel layer, AlGaN barrier layer and p-GaN cap layer have been formed.

[0091] Step 3: Surface treatment of the device with completed mesa isolation.

[0092] Step 4: Use a "T"-shaped double-layer mask material that is wide at the top and narrow at the bottom to protect the gate area, and etch the p-GaN cap layer to remove the p-GaN cap layer in the non-gate area.

[0093] Step 5: Surface treatment of the device without removing or damaging the gate mask material.

[0094] Step 6: On the basis of the gate mask material, a passivation layer is deposited by PVD or CVD. Because the mask layer below is narrow, the passivation layer can be partially deposited on the surface of the p-GaN gate, achieving a better passivation effect.

[0095] Step 7: Remove the mask material in the gate area by lift-off.

[0096] Step 8: Etch the passivation layer to expose the contact areas of the source and drain electrodes.

[0097] Step 9: Using electron beam evaporation, thermal evaporation or magnetron sputtering process, evaporate the gate contact metal on the gate electrode region window to obtain the prepared pseudo self-aligned p-type gallium nitride gate high electron mobility transistor.

[0098] Among them, Fig.11 Alternative process flow shown Figure 5 , the specific steps are as follows:

[0099] Step 1: Select an epitaxial wafer having formed a substrate, a buffer layer, a GaN channel layer, an AlGaN barrier layer and a p-GaN cap layer.

[0100] Step 2: Performing mesa isolation on the epitaxial wafer on which the substrate, buffer layer, GaN channel layer, AlGaN barrier layer and p-GaN cap layer have been formed.

[0101] Step 3: Surface treatment of the device with completed mesa isolation.

[0102] Step 4: Use a "T"-shaped double-layer mask material that is wide at the top and narrow at the bottom to protect the gate area, and etch the p-GaN cap layer to remove the p-GaN cap layer in the non-gate area.

[0103] Step 5: Remove the upper etching mask layer.

[0104] Step 6: Surface treatment of the device is performed without removing or damaging the gate mask material.

[0105] Step 7: On the basis of the gate mask material, a passivation layer is deposited by PVD or CVD. Since the mask layer below is narrower than the p-GaN gate, the passivation layer can be partially deposited on the surface of the p-GaN gate, achieving a better passivation effect.

[0106] Step 8: Remove the mask material in the gate area by lift-off.

[0107] Step 9: Etch the passivation layer to expose the contact areas of the source and drain electrodes.

[0108] Step 10: Using electron beam evaporation, thermal evaporation or magnetron sputtering process, evaporate the gate contact metal on the gate electrode region window to obtain a prepared pseudo self-aligned p-type gallium nitride gate high electron mobility transistor.

[0109] Among them, Fig.12 Alternative process flow shown Figure 6 , the specific steps are as follows:

[0110] Step 1: Select an epitaxial wafer having formed a substrate, a buffer layer, a GaN channel layer, an AlGaN barrier layer and a p-GaN cap layer.

[0111] Step 2: Performing mesa isolation on the epitaxial wafer on which the substrate, buffer layer, GaN channel layer, AlGaN barrier layer and p-GaN cap layer have been formed.

[0112] Step 3: Surface treatment of the device with completed mesa isolation.

[0113] Step 4: Use a "T"-shaped double-layer mask material that is wide at the top and narrow at the bottom to protect the gate area, and etch the p-GaN cap layer to remove the p-GaN cap layer in the non-gate area.

[0114] Step 5: Surface treatment of the device without removing or damaging the gate mask material.

[0115] Step 6: On the basis of the gate mask material, a passivation layer is deposited by PVD or CVD. Since the mask layer below is narrower than the p-GaN gate, the passivation layer can be partially deposited on the surface of the p-GaN gate, achieving a better passivation effect.

[0116] Step 7: Remove the mask material in the gate area by lift-off.

[0117] Step 8: Deposit a gate dielectric layer by PVD or CVD to provide the device gate with better passivation and voltage resistance.

[0118] Step 9: Etch the dielectric layer and the passivation layer to expose the contact areas of the source and drain electrodes.

[0119] Step 10: Using electron beam evaporation, thermal evaporation or magnetron sputtering process, evaporate the gate contact metal on the gate electrode region window to obtain a prepared pseudo self-aligned p-type gallium nitride gate high electron mobility transistor.

[0120] Among them, Fig.13 Alternative process flow shown Figure 7 , the specific steps are as follows:

[0121] Step 1: Select an epitaxial wafer having formed a substrate, a buffer layer, a GaN channel layer, an AlGaN barrier layer and a p-GaN cap layer.

[0122] Step 2: Performing mesa isolation on the epitaxial wafer on which the substrate, buffer layer, GaN channel layer, AlGaN barrier layer and p-GaN cap layer have been formed.

[0123] Step 3: Surface treatment of the device with completed mesa isolation.

[0124] Step 4: Use a "T"-shaped double-layer mask material that is wide at the top and narrow at the bottom to protect the gate area, and etch the p-GaN cap layer to remove the p-GaN cap layer in the non-gate area.

[0125] Step 5: Remove the upper etching mask layer.

[0126] Step 6: Surface treatment of the device is performed without removing or damaging the gate mask material.

[0127] Step 7: On the basis of the gate mask material, a passivation layer is deposited by PVD or CVD. Since the mask layer below is narrower than the p-GaN gate, the passivation layer can be partially deposited on the surface of the p-GaN gate, achieving a better passivation effect.

[0128] Step 8: Remove the mask material in the gate area by lift-off.

[0129] Step 9: Deposit a gate dielectric layer by PVD or CVD to provide the device gate with better passivation and voltage resistance.

[0130] Step 10: Etch the passivation layer to expose the contact areas of the source and drain electrodes.

[0131] Step 11: Using electron beam evaporation, thermal evaporation or magnetron sputtering process, evaporate the gate contact metal on the gate electrode region window to obtain a prepared pseudo self-aligned p-type gallium nitride gate high electron mobility transistor.

[0132] In summary, this application has the following technical effects:

[0133] Based on the conventional p-GaN gate HEMT, after etching pGaN, the present application directly epitaxially grows the passivation layer without removing the etching mask layer. After the passivation layer is grown, the epitaxially grown passivation layer is selectively stripped through the mask material to expose the pGaN cap layer, thereby realizing pseudo self-alignment of the gate. Since the gate of the pseudo self-alignment process can be deposited after the ohmic contact, it is compatible with the high-temperature annealing process of interface state repair and ohmic contact, so it has very good current density and dynamic characteristics, and can greatly reduce the process complexity.

[0134] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0135] This article uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. At the same time, for those skilled in the art, according to the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. A method for preparing a pseudo self-aligned p-type gallium nitride gate high electron mobility transistor, characterized in that: include: Select an epitaxial wafer having formed a substrate, a buffer layer, a GaN channel layer, an AlGaN barrier layer and a p-GaN cap layer; Performing mesa isolation on the epitaxial wafer having formed the substrate, the buffer layer, the GaN channel layer, the AlGaN barrier layer and the p-GaN cap layer; Performing surface treatment on the device with completed mesa isolation; Using a mask material, the p-GaN cap layer is etched to expose the contact areas of the source and drain electrodes; Surface treatment of the device without removing or damaging the gate mask material; On the basis of the gate mask material, a passivation layer is deposited by PVD or CVD; Removing the mask material in the gate area by lift-off; Using electron beam evaporation, thermal evaporation or magnetron sputtering process, evaporate n-type ohmic contact metal on the drain electrode and source electrode area windows, and anneal at high temperature to form source and drain electrodes; The gate contact metal is evaporated on the gate electrode region window by electron beam evaporation, thermal evaporation or magnetron sputtering process to obtain a prepared pseudo self-aligned p-type gallium nitride gate high electron mobility transistor.

2. The method for preparing a pseudo self-aligned p-type gallium nitride gate high electron mobility transistor according to claim 1, characterized in that: The surface treatment is one of acid treatment, alkali treatment or acid-alkali treatment in turn.

3. The method for preparing a pseudo self-aligned p-type gallium nitride gate high electron mobility transistor according to claim 8, characterized in that: The n-type ohmic contact metal is Ti / Al, Ti / Al / Ni / Au or Ti / Al / Ti / Au.

4. A pseudo self-aligned p-type gallium nitride gate high electron mobility transistor, characterized in that: The pseudo self-aligned p-type gallium nitride gate high electron mobility transistor comprises: a substrate, a buffer layer, a GaN channel layer, an AlGaN barrier layer, a p-GaN cap layer, a passivation layer, a gate, a source electrode and a drain electrode; The buffer layer covers the substrate; the GaN channel layer covers the buffer layer; the AlGaN barrier layer covers the GaN channel layer; a source and a drain are provided at both ends of the AlGaN barrier layer; the p-GaN cap layer is located on the AlGaN barrier layer and is not connected to the source and the drain; the passivation layer is located above the AlGaN barrier layer and a portion of the p-GaN cap layer; and the gate is located above the p-GaN cap layer and a portion of the passivation layer.

5. The pseudo self-aligned p-type gallium nitride gate high electron mobility transistor according to claim 4, characterized in that: The substrate is one of a silicon substrate, a sapphire substrate, a silicon carbide substrate or a self-supporting gallium nitride substrate.

6. The pseudo self-aligned p-type gallium nitride gate high electron mobility transistor according to claim 4, characterized in that: The buffer layer is composed of a gallium nitride layer doped with iron or carbon or an AlN / GaN super lattice structure.

7. The pseudo self-aligned p-type gallium nitride gate high electron mobility transistor according to claim 4, characterized in that: At the interface between the AlGaN barrier layer and the GaN channel layer, a two-dimensional electron gas is generated on the side close to the GaN channel layer through piezoelectric polarization and spontaneous polarization effects.

8. The pseudo self-aligned p-type gallium nitride gate high electron mobility transistor according to claim 4, characterized in that: The p-GaN cap layer is used to suppress the generation of 2DEG at the AlGaN / GaN interface through the piezoelectric polarization and spontaneous polarization effect at the GaN / AlGaN interface and the p-type doping of the p-GaN cap layer itself.

9. The pseudo self-aligned p-type gallium nitride gate high electron mobility transistor according to claim 5, characterized in that: The contact between the p-GaN cap layer and the AlGaN barrier layer includes ohmic contact, Schottky contact and dielectric layer isolation.

10. The pseudo self-aligned p-type gallium nitride gate high electron mobility transistor according to claim 4, characterized in that: The material of the passivation layer is composed of one of silicon nitride, aluminum nitride, aluminum oxide, magnesium oxide or silicon oxide.

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