Preparation method of semiconductor device

Abstract

The invention provides a preparation method of a semiconductor device, and the preparation method comprises the steps: after removing a patterned first photoresist layer used for carrying out the ion implantation of a gate structure, cleaning a semiconductor structure through employing an acid pickling process and an alkali cleaning process, so as to remove a natural oxidation layer on the surface of the semiconductor structure, according to the invention, the back surface of the semiconductor structure is cleaned by using the deionized water, so that the back dielectric layer on the back surface of the substrate can be prevented from being in contact with the hydrofluoric acid solution; therefore, the condition that the current-layer wafer forms more exposure dead pixels in the following photoetching process is avoided, the overlay precision of subsequent metal zero-layer through hole etching is improved, the yield and reliability of the device are improved, and meanwhile, the condition that the back dielectric layer on the back surface of the substrate is stripped and then falls off to pollute and / or smash the front surface of the lower-layer wafer is also avoided.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a method for preparing a semiconductor device. Background Art

[0002] In the metal zero layer preparation process in the middle section of the field effect transistor, it was found that the wafer suffered from a large number of exposure bad spots in the metal zero layer lithography process. The exposure bad spots would seriously affect the overlay of the metal zero layer, resulting in a large error in the overlay deviation, thereby causing the etching window of the metal zero layer through hole to become smaller and the risk of etching through hole errors to be higher.

[0003] During the yield diagnosis, the HVS (High Voltage Stress) failure caused by the overlay offset of the metal zero layer was also detected. The large overlay offset error found by the measurement and the electron microscope image with more exposure bad spots were exactly matched, and both were in-plane MAP (graphs). This confirmed that the exposure bad spots suffered by the wafer in the metal zero layer lithography process will have a serious impact on the overlay of the metal zero layer through hole. The inventor found that the total number of exposure bad spots on the wafer in the metal zero layer lithography process was as high as 1564 or more for three consecutive months, which had a significant adverse impact on the yield and reliability of field effect transistor devices. Summary of the invention

[0004] The present application provides a method for preparing a semiconductor device, which can solve the problem that the exposure bad spots suffered by the wafer in the metal zero layer lithography process affect the overlay of the metal zero layer through hole and thus affect the yield and reliability of the device.

[0005] The present invention provides a method for manufacturing a semiconductor device, comprising:

[0006] A substrate is provided, wherein a gate structure and a first hard mask layer are formed on the front side of the substrate, and the first hard mask layer covers the gate structure and the front side of the substrate; an active region and a drain region are formed in the substrate, and the source region and the drain region are respectively located on both sides of the gate structure; and a back dielectric layer is formed on the back side of the semiconductor structure;

[0007] coating a first photoresist layer on the first hard mask layer;

[0008] By means of a photolithography process, a gate ionization window pattern is defined on the first photoresist layer to form a patterned first photoresist layer;

[0009] Using the patterned first photoresist layer as a mask, etching the first hard mask layer to the top of the gate structure;

[0010] performing an ion implantation process on the gate structure;

[0011] removing the patterned first photoresist layer;

[0012] removing the first hard mask layer;

[0013] Cleaning the semiconductor structure after removing the first hard mask layer by a wet cleaning process to remove the natural oxide layer on the surface of the semiconductor structure, wherein the wet cleaning process includes: an acid cleaning process and an alkali cleaning process, wherein in the acid cleaning process, a hydrofluoric acid solution is used to clean the front side of the semiconductor structure and deionized water is used to clean the back side of the semiconductor structure;

[0014] An interlayer dielectric layer is formed, wherein the interlayer dielectric layer covers the gate structure and the front surface of the substrate.

[0015] Optionally, in the method for preparing the semiconductor device, the step of using a wet cleaning process to clean the semiconductor structure after removing the first hard mask layer to remove the natural oxide layer on the surface of the semiconductor structure includes:

[0016] Performing an acid pickling process, using a hydrofluoric acid solution to clean the front side of the semiconductor structure for 150 seconds, and using deionized water to clean the back side of the semiconductor structure for 150 seconds;

[0017] An alkali cleaning process is performed to clean the front side of the semiconductor structure with ammonia water and purge the back side of the semiconductor structure with nitrogen gas.

[0018] Optionally, in the method for preparing the semiconductor device, the step of performing the alkali washing process includes:

[0019] The front side of the semiconductor structure is cleaned with ammonia water for the first time, and the back side of the semiconductor structure is purged with nitrogen gas for 70 seconds;

[0020] drying the semiconductor structure using isopropyl alcohol;

[0021] The front side of the semiconductor structure is cleaned with ammonia water for the second time, and the back side of the semiconductor structure is purged with nitrogen gas for 40 seconds;

[0022] drying the semiconductor structure using isopropyl alcohol;

[0023] The front side of the semiconductor structure is cleaned with ammonia water for the third time, and the back side of the semiconductor structure is purged with nitrogen gas for 40 seconds;

[0024] The semiconductor structure was dried using isopropyl alcohol.

[0025] Optionally, in the method for preparing the semiconductor device, in the pickling process, the ratio of HF to water in the hydrofluoric acid solution is 1:200.

[0026] Optionally, in the method for preparing the semiconductor device, after forming the interlayer dielectric layer, the method for preparing the semiconductor device further comprises:

[0027] forming a second hard mask layer, wherein the second hard mask layer covers the interlayer dielectric layer;

[0028] coating a second photoresist layer on the second hard mask layer;

[0029] By means of a photolithography process, a through-hole pattern is defined on the second photoresist layer to form a patterned second photoresist layer;

[0030] Using the patterned second photoresist layer as a mask, etching the second hard mask layer to the top of the gate structure, and etching the second hard mask layer and the interlayer dielectric layer to the surfaces of the source region and the drain region to form a plurality of through holes;

[0031] Filling a metal material in the through hole to form a metal zero layer;

[0032] removing the patterned second photoresist layer;

[0033] The second hard mask layer is removed.

[0034] Optionally, in the method for preparing the semiconductor device, hot sulfuric acid is used to remove the patterned first photoresist layer.

[0035] Optionally, in the method for preparing the semiconductor device, the material of the first hard mask layer is silicon nitride.

[0036] Optionally, in the method for preparing the semiconductor device, the material of the back dielectric layer is silicon nitride.

[0037] Optionally, in the method for preparing the semiconductor device, the material of the second hard mask layer is silicon nitride.

[0038] The technical solution of this application has at least the following advantages:

[0039] After removing the patterned first photoresist layer used for ion implantation into the gate structure, the present application uses a wet cleaning process to clean and remove the semiconductor structure after the first hard mask layer is removed, so as to remove the natural oxide layer on the surface of the semiconductor structure, wherein the wet cleaning process includes: an acid cleaning process and an alkaline cleaning process, wherein in the acid cleaning process, a hydrofluoric acid solution is used to clean the front side of the semiconductor structure and deionized water is used to clean the back side of the semiconductor structure. By using deionized water to clean the back side of the semiconductor structure, the present application can avoid the back dielectric layer on the back side of the substrate from contacting the hydrofluoric acid solution, thereby avoiding the situation where the surface of the back dielectric layer is washed with pits and unevenness, thereby avoiding the situation where the current layer wafer has exposed bad spots in the subsequent photolithography process, improving the overlay accuracy of subsequent metal zero layer through-hole etching, and improving the yield and reliability of the device.

[0040] Furthermore, in the pickling process and alkali cleaning process of the present application, multiple semiconductor structures (wafers) are stacked and maintained at a certain interval, and the pickling process and alkali cleaning process are carried out together in a process chamber. In the pickling process, a hydrofluoric acid solution is used to clean the front side of the semiconductor structure and deionized water is used to clean the back side of the semiconductor structure. This can prevent the back dielectric layer on the back side of the substrate from contacting the hydrofluoric acid solution, thereby preventing the back dielectric layer on the back side of the substrate from peeling off and falling off to contaminate and / or damage the front side of the wafer below.

[0041] In summary, the present application uses deionized water to clean the back side of the semiconductor structure, which can not only clean and remove impurities (such as high molecular polymers, etc.) on the back side of the wafer, but also will not damage the back dielectric layer, thereby improving the exposure bad spots of the current wafer and reducing the contamination and / or damage defects on the front side of the lower wafer caused by the corrosion and falling of the back dielectric layer of the upper wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0043] Figure 1 is a flow chart of a method for preparing a semiconductor device according to an embodiment of the present invention;

[0044] Figure 2-Figure 10 is a schematic diagram of a semiconductor structure in each process step of preparing a semiconductor device according to an embodiment of the present invention;

[0045] The reference numerals are described as follows:

[0046] 10-substrate, 11-source region, 12-drain region, 21-gate oxide layer, 22-gate, 23-sidewall, 31-first hard mask layer, 40-back dielectric layer, 51-first photoresist layer, 52-patterned first photoresist layer, 53-gate ionization window, 60-interlayer dielectric layer, 71-metal zero layer one, 72-metal zero layer two, 73-metal zero layer three. DETAILED DESCRIPTION

[0047] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0048] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0049] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0050] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0051] The present application provides a method for preparing a semiconductor device, referring to Figure 1 , Figure 1 1 is a flow chart of a method for preparing a semiconductor device according to an embodiment of the present invention, wherein the method for preparing a semiconductor device comprises:

[0052] First, perform step S1: refer to Figure 2 , Figure 2It is a schematic diagram of a semiconductor structure after a back dielectric layer and a first hard mask layer are formed in an embodiment of the present application, and a substrate 10 is provided, a gate structure and a first hard mask layer 31 are formed on the front side of the substrate 10, and the first hard mask layer 31 covers the gate structure and the front side of the substrate 10; an active region 11 and a drain region 12 are formed in the substrate 10, and the source region 11 and the drain region 12 are respectively located on both sides of the gate structure, and a back dielectric layer 40 is formed on the back side of the semiconductor structure.

[0053] In step S1, the source region 11 and the drain region 12 are formed by a conventional device source and drain region ion implantation process. Specifically, in the process of forming the source region 11 and the drain region 12, it is usually necessary to use a photoresist layer as a mask, and then open the barrier layer at the top of the source region 11 and the drain region 12 through processes such as photolithography and etching, and then perform ion implantation processes on the substrate on both sides of the gate structure to form the source region 11 and the drain region 12, respectively, and finally remove the photoresist layer and the barrier layer.

[0054] In this embodiment, the gate structure at least includes: a gate oxide layer 21 , a gate 22 and a sidewall 23 . The gate oxide layer 21 is located on the front side of the substrate 10 , the gate 22 covers the gate oxide layer 21 , and the sidewall 23 is located on both sides of the gate 22 .

[0055] In this embodiment, the sidewall spacer 23 is a combination of a silicon oxide layer and a silicon nitride layer.

[0056] Preferably, the first hard mask layer 31 is made of silicon nitride.

[0057] In this embodiment, the material of the back dielectric layer 40 is silicon nitride.

[0058] Then, execute step S2: refer to Figure 3 , Figure 3 It is a schematic diagram of a semiconductor structure after a first photoresist layer is coated on the first hard mask layer according to an embodiment of the present application, and a first photoresist layer 51 is coated on the first hard mask layer 31 .

[0059] Next, execute step S3: refer to Figure 4 , Figure 4 It is a schematic diagram of a semiconductor structure after a patterned first photoresist layer is formed in an embodiment of the present application. Through a photolithography process, a gate ionization window 53 pattern is defined on the first photoresist layer 51 to form a patterned first photoresist layer 52.

[0060] Further, step S4 is performed: refer to Figure 5 , Figure 5It is a schematic diagram of the semiconductor structure after etching the first hard mask layer to the top of the gate structure according to an embodiment of the present application. The first hard mask layer 31 is etched to the top of the gate 22 using the patterned first photoresist layer 52 as a mask.

[0061] Next, execute step S5: refer to Figure 6 , Figure 6 Schematic diagram of a semiconductor structure in which an ion implantation process is performed on the gate according to an embodiment of the present application, wherein an ion implantation process is performed on the gate 22 .

[0062] Further, step S6 is performed: removing the patterned first photoresist layer 52 .

[0063] In this embodiment, hot sulfuric acid is used to remove the patterned first photoresist layer 52 .

[0064] Next, step S7 is performed: removing the first hard mask layer 31 .

[0065] In this embodiment, the first hard mask layer 31 may be removed by using a dry etching process or a wet etching process.

[0066] Further, step S8 is performed: refer to Figure 7 and Figure 8 , Figure 7 is a schematic diagram of a semiconductor structure for performing an acid pickling process according to an embodiment of the present application, Figure 8 It is a schematic diagram of a semiconductor structure that performs an alkaline washing process in an embodiment of the present application, wherein a wet cleaning process is used to clean and remove the semiconductor structure after the first hard mask layer is removed to remove the natural oxide layer on the surface of the semiconductor structure, wherein the wet cleaning process includes: an acid washing process and an alkaline washing process.

[0067] Preferably, the step of using a wet cleaning process to clean the semiconductor structure after removing the first hard mask layer to remove the natural oxide layer on the surface of the semiconductor structure may specifically include:

[0068] Step S8.1: Reference Figure 7 , performing an acid pickling process, using a hydrofluoric acid solution to clean the front side of the semiconductor structure, the cleaning time lasts for 150 seconds, and using deionized water to clean the back dielectric layer 40 on the back side of the semiconductor structure, the cleaning time lasts for 150 seconds;

[0069] Step S8.2: Reference Figure 8 , performing an alkaline cleaning process, using ammonia water to clean the front side of the semiconductor structure, and using nitrogen gas to purge the back dielectric layer 40 on the back side of the semiconductor structure.

[0070] Preferably, in the pickling process, the ratio of HF to water in the hydrofluoric acid solution is 1:200.

[0071] Among them, pickling with hydrofluoric acid can remove the natural oxide layer on the front side of the semiconductor structure; further, using deionized water to clean the back side of the semiconductor structure can not only clean and remove impurities (such as high molecular polymers, etc.) on the back side of the wafer, but also will not damage the back dielectric layer. In the pickling process, the hydrofluoric acid solution for cleaning the front side of the semiconductor structure will not flow to the back side of the wafer. When the workbench rotates at a high speed, the hydrofluoric acid solution for cleaning the front side of the wafer will fly out from the front edge of the wafer and fall into the collection device.

[0072] Preferably, the steps of performing the alkali washing process may specifically include:

[0073] Step S8.21: Cleaning the front side of the semiconductor structure with ammonia water for the first time, and simultaneously purging the back dielectric layer 40 on the back side of the semiconductor structure with nitrogen gas for 70 seconds;

[0074] Step S8.22: Drying the semiconductor structure using isopropyl alcohol;

[0075] Step S8.23: Cleaning the front surface of the semiconductor structure with ammonia water for a second time, and simultaneously purging the back dielectric layer 40 on the back surface of the semiconductor structure with nitrogen gas for 40 seconds;

[0076] Step S8.24: Drying the semiconductor structure using isopropyl alcohol;

[0077] Step S8.25: Cleaning the front side of the semiconductor structure with ammonia water for the third time, and simultaneously purging the back dielectric layer 40 on the back side of the semiconductor structure with nitrogen gas for 40 seconds;

[0078] Step S8.26: Dry the semiconductor structure using isopropyl alcohol.

[0079] Among them, using ammonia water to clean the front of the semiconductor structure and using nitrogen gas to purge the back dielectric layer 40 on the back of the semiconductor structure can further remove impurities on the front of the semiconductor structure. The cleaning principle of using ammonia water to clean the front of the semiconductor structure and using nitrogen gas to purge the back dielectric layer 40 on the back of the semiconductor structure can be the Bernoulli principle. In the process of using nitrogen gas to purge the back dielectric layer 40 on the back of the semiconductor structure, the ammonia water cleaning the front of the wafer will not flow to the back of the wafer. When the workbench rotates at a high speed, the ammonia water cleaning the front of the wafer flies out from the edge of the front of the wafer and falls into the collection device.

[0080] In the wet cleaning process of the present application, multiple semiconductor structures (wafers) are stacked and maintained at a certain interval, and are subjected to an acid pickling process and an alkaline pickling process in a process chamber together. The semiconductor structure after removing the first hard mask layer is cleaned by the acid pickling process and the alkaline pickling process to remove the natural oxide layer on the surface of the semiconductor structure. In the acid pickling process, a hydrofluoric acid solution is used to clean the front of the semiconductor structure and deionized water is used to clean the back of the semiconductor structure. The present application uses deionized water to clean the back of the semiconductor structure, thereby avoiding the back dielectric layer on the back of the substrate from contacting the hydrofluoric acid solution, thereby avoiding the situation where the surface of the back dielectric layer is washed with pits and unevenness, thereby avoiding the situation where the wafer has exposure bad spots in the subsequent photolithography process, improving the overlay accuracy of subsequent metal zero layer through-hole etching, and improving the yield and reliability of the device.

[0081] Furthermore, in the pickling process, using a hydrofluoric acid solution to clean the front side of the semiconductor structure and using deionized water to clean the back side of the semiconductor structure can prevent the back dielectric layer on the back side of the substrate from contacting the hydrofluoric acid solution, thereby preventing the back dielectric layer on the back side of the substrate from peeling off and then falling off to contaminate and / or damage the front side of the lower wafer, that is, preventing the front sides of multiple lower wafers in the stacked wafers from being contaminated and / or damaged by the back dielectric layer that falls from the upper wafer, further improving the yield and reliability of the device.

[0082] Finally, execute step S9: reference Fig. 9 , Fig. 9 1 is a schematic diagram of a semiconductor structure in which an interlayer dielectric layer is formed according to an embodiment of the present application, wherein an interlayer dielectric layer 60 is formed, and the interlayer dielectric layer 60 covers the gate structure and the front surface of the substrate 10 .

[0083] For further reference, Fig.10 , Fig.10 is a schematic diagram of a semiconductor structure for forming a metal zero layer in an embodiment of the present application. After forming the interlayer dielectric layer 60, the method for preparing the semiconductor device may further include:

[0084] Step S10: forming a second hard mask layer (not shown), wherein the second hard mask layer covers the interlayer dielectric layer;

[0085] Step S11: coating a second photoresist layer (not shown) on the second hard mask layer;

[0086] Step S12: defining a through-hole pattern on the second photoresist layer by a photolithography process to form a patterned second photoresist layer (not shown);

[0087] Step S13: using the patterned second photoresist layer as a mask, etching the second hard mask layer to the top of the gate structure, and etching the second hard mask layer and the interlayer dielectric layer to the surfaces of the source region and the drain region to form a plurality of through holes (not shown);

[0088] Step S14: Reference Fig.10 , filling the through hole with metal material to form a metal zero layer 1 71, a metal zero layer 2 72 and a metal zero layer 3 73; wherein the metal zero layer 1 71 penetrates the interlayer dielectric layer 60 and contacts the source region 11, the metal zero layer 2 72 penetrates the interlayer dielectric layer 60 and contacts the drain region 12, and the metal zero layer 3 73 penetrates the interlayer dielectric layer 60 and contacts the gate 22;

[0089] Step S15: removing the patterned second photoresist layer (not shown);

[0090] Step S16: removing the second hard mask layer (not shown).

[0091] In this embodiment, the material of the second hard mask layer may be silicon nitride.

[0092] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: Providing a substrate, a gate structure and a first hard mask layer are formed on the front side of the substrate, and the first hard mask layer covers the gate structure and the front side of the substrate; An active region and a drain region are formed in the substrate, the source region and the drain region are respectively located on two sides of the gate structure, and a back dielectric layer is formed on the back of the semiconductor structure; coating a first photoresist layer on the first hard mask layer; By means of a photolithography process, a gate ionization window pattern is defined on the first photoresist layer to form a patterned first photoresist layer; Using the patterned first photoresist layer as a mask, etching the first hard mask layer to the top of the gate structure; performing an ion implantation process on the gate structure; removing the patterned first photoresist layer; removing the first hard mask layer; Cleaning the semiconductor structure after removing the first hard mask layer by a wet cleaning process to remove the natural oxide layer on the surface of the semiconductor structure, wherein the wet cleaning process includes: an acid cleaning process and an alkali cleaning process, wherein in the acid cleaning process, a hydrofluoric acid solution is used to clean the front side of the semiconductor structure and deionized water is used to clean the back side of the semiconductor structure; An interlayer dielectric layer is formed, wherein the interlayer dielectric layer covers the gate structure and the front surface of the substrate.

2. The method for preparing a semiconductor device according to claim 1, wherein: The step of using a wet cleaning process to clean the semiconductor structure after removing the first hard mask layer to remove the natural oxide layer on the surface of the semiconductor structure includes: Performing an acid pickling process, using a hydrofluoric acid solution to clean the front side of the semiconductor structure for 150 seconds, and using deionized water to clean the back side of the semiconductor structure for 150 seconds; An alkali cleaning process is performed to clean the front side of the semiconductor structure with ammonia water and purge the back side of the semiconductor structure with nitrogen gas.

3. The method for preparing a semiconductor device according to claim 2, characterized in that: The steps of performing the alkali washing process include: The front side of the semiconductor structure is cleaned with ammonia water for the first time, and the back side of the semiconductor structure is purged with nitrogen gas for 70 seconds; drying the semiconductor structure using isopropyl alcohol; The front side of the semiconductor structure is cleaned with ammonia water for the second time, and the back side of the semiconductor structure is purged with nitrogen gas for 40 seconds; drying the semiconductor structure using isopropyl alcohol; The front side of the semiconductor structure is cleaned with ammonia water for the third time, and the back side of the semiconductor structure is purged with nitrogen gas for 40 seconds; The semiconductor structure was dried using isopropyl alcohol.

4. The method for preparing a semiconductor device according to claim 1, wherein: In the pickling process, the ratio of HF to water in the hydrofluoric acid solution is 1:

200.

5. The method for preparing a semiconductor device according to claim 1, characterized in that: After forming the interlayer dielectric layer, the method for preparing the semiconductor device further includes: forming a second hard mask layer, wherein the second hard mask layer covers the interlayer dielectric layer; coating a second photoresist layer on the second hard mask layer; By means of a photolithography process, a through-hole pattern is defined on the second photoresist layer to form a patterned second photoresist layer; Using the patterned second photoresist layer as a mask, etching the second hard mask layer to the top of the gate structure, and etching the second hard mask layer and the interlayer dielectric layer to the surfaces of the source region and the drain region to form a plurality of through holes; Filling a metal material in the through hole to form a metal zero layer; removing the patterned second photoresist layer; The second hard mask layer is removed.

6. The method for preparing a semiconductor device according to claim 1, wherein: The patterned first photoresist layer is removed using hot sulfuric acid.

7. The method for preparing a semiconductor device according to claim 1, characterized in that: The material of the first hard mask layer is silicon nitride.

8. The method for preparing a semiconductor device according to claim 1, characterized in that: The material of the back dielectric layer is silicon nitride.

9. The method for preparing a semiconductor device according to claim 5, characterized in that: The material of the second hard mask layer is silicon nitride.

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