Multilayer ceramic capacitor

Abstract

The invention provides a multilayer ceramic capacitor capable of suppressing vibration of a dielectric caused by a piezoelectric phenomenon generated when the multilayer ceramic capacitor is mounted on a wiring substrate and reducing harsh vibration sound. A laminated ceramic capacitor (1) has a laminated body (2) in which dielectric layers (5) and internal electrode layers (6) are alternately laminated, and external electrodes (4) which are respectively disposed on end surfaces on both sides of the laminated body (2) in a longitudinal direction (L) orthogonal to the lamination direction (T) and which are connected to the internal electrode layers (6), the surface of each external electrode (4) in plan view from the longitudinal direction (L) being larger than the surface of the dielectric layer (5) in plan view from the longitudinal direction (L), and the surface of the external electrode (4) being larger than the surface of the internal electrode layer (6) in plan view from the lamination direction (T). A frame region (9) having a width of 1 [mu] m or more and 100 [mu] m or less from the outer peripheral edge is covered with an insulating layer (8).

Description

Technical Field

[0001] The present invention relates to a multilayer ceramic capacitor capable of suppressing the generation of vibration sound caused by a piezoelectric phenomenon during mounting. Background Art

[0002] In the past, electronic components such as multilayer ceramic capacitors have been widely used in mobile terminal devices such as mobile phones and various electronic devices such as personal computers. Multilayer ceramic capacitors are composed of a rectangular stacked body in which dielectric layers and internal electrode layers are alternately stacked, and external electrodes formed at opposite ends of the stacked body.

[0003] The dielectric layer usually uses a dielectric ceramic of a perovskite structure such as barium titanate, so if a DC voltage is applied while an AC voltage is applied, vibration occurs due to the piezoelectric phenomenon. Therefore, if a multilayer ceramic capacitor is mounted on a wiring substrate, for example, an AC voltage in the audible frequency band of 20 Hz to 20 kHz is applied to the external electrodes, the multilayer ceramic capacitor undergoes expansion and contraction vibration, the surrounding air vibrates to generate sound, and the wiring substrate also resonates and vibrates, causing the sound to be amplified and become harsh.

[0004] Therefore, there is a demand for the development of a multilayer ceramic capacitor that can suppress the vibration of the dielectric caused by the piezoelectric phenomenon generated when the capacitor is mounted on a wiring board and reduce the harsh vibration sound.

[0005] Prior Art Literature

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent Application Publication No. 2000-182888 Summary of the invention

[0008] Problem that the invention aims to solve

[0009] An object of the present invention is to provide a multilayer ceramic capacitor capable of suppressing vibration of a dielectric material caused by a piezoelectric phenomenon generated when the capacitor is mounted on a wiring board and reducing harsh vibration sound.

[0010] Technical solutions to solve problems

[0011] The inventors of the present invention have found that vibration sound caused by a piezoelectric phenomenon generated during mounting can be suppressed by arranging an insulator at a predetermined position of an external electrode of a multilayer ceramic capacitor, thereby completing the present invention.

[0012] That is, the present invention is a laminated ceramic capacitor comprising: a laminated body in which dielectric layers and internal electrode layers are alternately laminated; and external electrodes are respectively arranged on end faces of both sides of the laminated body in a longitudinal direction orthogonal to the lamination direction and connected to the internal electrode layers, wherein:

[0013] The surface of the external electrode when viewed in plan from the longitudinal direction is covered with an insulating layer except for a frame region having a width of 1 μm to 100 μm from the outer peripheral edge.

[0014] Effects of the Invention

[0015] According to the present invention, it is possible to provide a multilayer ceramic capacitor capable of suppressing vibration of a dielectric material caused by a piezoelectric phenomenon generated when the capacitor is mounted on a wiring board and reducing harsh vibration sound. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is an appearance diagram of a multilayer ceramic capacitor.

[0017] Figure 2 yes Figure 1 AA line cross-sectional view of the multilayer ceramic capacitor shown.

[0018] Figure 3 It is an exploded perspective view schematically showing an example of the inner layer portion.

[0019] Figure 4 FIG. 1 is an external view showing an example of a mounted state of a multilayer ceramic capacitor according to the present invention.

[0020] Figure 5 FIG. 1 is an external view showing an example of a mounted state of a conventional multilayer ceramic capacitor.

[0021] Figure 6 This is a diagram showing the effect of reducing the vibration noise of the multilayer ceramic capacitor according to the present invention. DETAILED DESCRIPTION

[0022] The following describes a multilayer ceramic capacitor according to an embodiment of the present invention, but the present invention is not limited thereto. In addition, the drawings are used to illustrate the contents of the invention, and are sometimes schematically simplified, and the ratio of the dimensions of the drawn components or components is sometimes inconsistent with the ratio of these dimensions described in the specification. In addition, there are cases where the components described in the specification are omitted in the drawings, or the number of components is omitted and drawn.

[0023] (Multilayer Ceramic Capacitors)

[0024] exist Figure 1 to Figure 3 , the shape and structure of the multilayer ceramic capacitor 1 are shown. Figure 11 is an external view of the multilayer ceramic capacitor 1 . Figure 2 is Figure 1 FIG. 1 is a cross-sectional view (LT cross-sectional view) of the multilayer ceramic capacitor 1 taken along line AA in the center portion in the width direction W shown. Figure 3 : is a schematic diagram showing the structure of the inner layer portion 3. In addition, the direction in which the dielectric layer and the internal electrode layer are stacked is set as the stacking direction T, and the structure of the laminated ceramic capacitor 1 is described using the length direction L orthogonal to the stacking direction T, and further using the width direction W orthogonal to the stacking direction T and the length direction L. In addition, in the embodiment, the width direction W, the length direction L, and the stacking direction T are orthogonal to each other, but they do not necessarily have to be in a mutually orthogonal relationship, and may also be in a mutually intersecting relationship.

[0025] The multilayer ceramic capacitor 1 includes a multilayer body 2 having a rectangular parallelepiped shape. The multilayer body 2 includes an inner layer portion 3, and has a pair of first main surfaces TS1 and second main surfaces TS2 facing each other in a stacking direction T, a pair of first end surfaces LS1 and second end surfaces LS2 facing each other in a length direction L orthogonal to the stacking direction T, and a pair of first side surfaces WS1 and second side surfaces WS2 facing each other in a width direction W orthogonal to both the stacking direction T and the length direction L.

[0026] The dimensions of the multilayer ceramic capacitor 1 are not particularly limited. For example, the dimension in the stacking direction T can be about 0.1 mm to 2.5 mm, the dimension in the length direction L can be about 0.1 mm to 3.2 mm, and the dimension in the width direction W can be about 0.1 mm to 2.5 mm.

[0027] The inner layer portion 3 includes a portion where a plurality of dielectric layers 5 and a plurality of internal electrode layers 6 are stacked. The internal electrode layer 6 is composed of a first internal electrode layer 6a and a second internal electrode layer 6b. The first internal electrode layer 6a and the second internal electrode layer 6b are disposed on the dielectric layers 5a and 5b, respectively.

[0028] The internal electrode layer 6 extends in the longitudinal direction L and has a rectangular shape when viewed from the stacking direction T. The first internal electrode layer 6 a is led out to the first end surface LS1 of the stacked body 2 , and the second internal electrode layer 6 b is led out to the second end surface LS2 of the stacked body 2 .

[0029] The dielectric layer 5 is made of a dielectric material. For example, the dielectric material may be a dielectric ceramic containing BaTiO3, CaTiO3, SrTiO3, or CaZrO3. In addition, the dielectric material may be a material in which a secondary component such as a Mn compound, a Fe compound, a Cr compound, a Co compound, or a Ni compound is added to these main components.

[0030] The thickness of the dielectric layer 5 is not particularly limited, and can be set to about 0.3 μm to 2.0 μm, for example, in an effective region formed by the capacitor formed by the first internal electrode layer 6 a and the second internal electrode layer 6 b .

[0031] The number of dielectric layers 5 is not particularly limited, and can be, for example, 1 to 6000 layers in an effective region formed by the capacitor formed by the first internal electrode layer 6a and the second internal electrode layer 6b.

[0032] On the upper and lower sides of the inner layer portion 3, an outer layer portion 7 consisting only of a dielectric layer 5 without forming an internal electrode layer 6 is provided. The thickness of the outer layer portion 7 is not limited, and can be set to 15 μm to 150 μm, for example. In addition, the thickness of the dielectric layer in the outer layer portion 7 can be greater than the thickness of the dielectric layer in the effective area of ​​the capacitor formed by the internal electrode layer 6. In addition, the material of the dielectric layer in the outer layer portion can also be different from the material of the dielectric layer in the inner layer portion.

[0033] Figure 3 The diagram shows the inner layer portion 3 exploded for each dielectric layer 5 in the stacking direction T.

[0034] The internal electrode layer 6 is formed by sintering a conductive paste containing metal powder, an organic solvent, a binder, and a dispersant, which is a conductor, on the dielectric layer. The internal electrode layer 6 and the dielectric layer 5 are alternately stacked to form the inner layer portion 3. The internal electrode layer 6 is composed of a first internal electrode layer 6a and a second internal electrode layer 6b, and the first internal electrode layer 6a and the second internal electrode layer 6b are respectively arranged on the dielectric layers 5a and 5b.

[0035] For example, metals such as Ni, Cu, Ag, Pd, Ag-Pd alloy, and Au can be used for the internal electrode layer 6. These metals may be compounds containing these metal elements or alloys with other metals.

[0036] The thickness of the internal electrode layer 6 is not particularly limited, and can be, for example, about 0.3 μm to 1.5 μm.

[0037] A first external electrode 4 a and a second external electrode 4 b are formed on the first end surface LS1 and the second end surface LS2 of the stacked body 2 , respectively.

[0038] The first external electrode 4 a includes a first foundation electrode layer 41 a and a first plating layer 42 a disposed on the first foundation electrode layer 41 a .

[0039] The second external electrode 4b includes a second foundation electrode layer 41b and a second plating layer 42b disposed on the second foundation electrode layer 41b.

[0040] The first base electrode layer 41a is arranged on the first end surface LS1. The first base electrode layer 41a is connected to the first internal electrode layer 6a. In the present embodiment, the first base electrode layer 41a is formed by extending from the first end surface LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0041] The second base electrode layer 41b is arranged on the second end surface LS2. The second base electrode layer 41b is connected to the second internal electrode layer 6b. In the present embodiment, the second base electrode layer 41b is formed by extending from the second end surface LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0042] The first base electrode layer 41a and the second base electrode layer 41b include at least one selected from a sintered layer, a conductive resin layer, a thin film layer, etc. The first base electrode layer 41a and the second base electrode layer 41b of the present embodiment are sintered layers. The sintered layer preferably includes a metal component, and either a glass component or a ceramic component, or both. The metal component, for example, includes at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The glass component, for example, includes at least one selected from B, Si, Ba, Mg, Al, Li, etc. The ceramic component can use the same ceramic material as the dielectric layer 5, or a ceramic material different from the dielectric layer 5. The ceramic component, for example, includes at least one selected from BaTiO3, CaTiO3, (Ba, Ca)TiO3, SrTiO3, CaZrO3, etc.

[0043] The sintered layer is obtained by, for example, applying a conductive paste containing glass and metal to the laminate and sintering it. The sintered layer can be obtained by simultaneously sintering a laminated small piece having an internal electrode layer and a dielectric layer and a conductive paste applied to the laminated small piece, or by applying a conductive paste to the laminate and sintering it after the laminated small piece having an internal electrode layer and a dielectric layer is sintered to obtain a laminate. In addition, when the laminated small piece having an internal electrode layer and a dielectric layer and the conductive paste applied to the laminated small piece are sintered simultaneously, the sintered layer is preferably formed by sintering a conductive paste to which a ceramic material is added instead of a glass component. In this case, as the added ceramic material, it is particularly preferred to use a ceramic material of the same kind as the dielectric layer. The sintered layer can also be multilayer.

[0044] The thickness of the first foundation electrode layer 41 a located at the first end surface LS1 in the longitudinal direction L is preferably about 3 μm or more and 160 μm or less in the central portion in the stacking direction T and the width direction W of the first foundation electrode layer 41 a .

[0045] The thickness of the second foundation electrode layer 41 b located at the second end surface LS2 in the longitudinal direction L is preferably about 3 μm or more and 160 μm or less in the central portion in the stacking direction T and the width direction W of the second foundation electrode layer 41 b .

[0046] When the first base electrode layer 41a is also provided on a portion of at least one surface of the first main surface TS1 or the second main surface TS2, the thickness of the first base electrode layer 41a provided on the portion in the stacking direction T is preferably greater than 3 μm and less than 40 μm in the central portion of the length direction L and the width direction W of the first base electrode layer 41a provided on the portion.

[0047] When the first base electrode layer 41a is also provided on a portion of at least one surface of the first side surface WS1 or the second side surface WS2, the thickness of the first base electrode layer 41a provided on the portion in the width direction W is preferably greater than 3 μm and less than 40 μm in the central portion in the length direction L and the stacking direction T of the first base electrode layer 41a provided on the portion.

[0048] When the second base electrode layer 41b is also provided on a portion of at least one surface of the first main surface TS1 or the second main surface TS2, the thickness of the second base electrode layer 41b provided on the portion in the stacking direction T is preferably greater than 3 μm and less than 40 μm in the central portion of the length direction L and the width direction W of the second base electrode layer provided on the portion.

[0049] When the second base electrode layer 41b is also provided on a portion of at least one surface of the first side surface WS1 or the second side surface WS2, the thickness of the second base electrode layer 41b provided on the portion in the width direction W is preferably greater than 3 μm and less than 40 μm in the central portion in the length direction L and the stacking direction T of the second base electrode layer 41b provided on the portion.

[0050] Alternatively, a structure in which the first and second base electrode layers 41 a and 41 b are not provided and the first and second plated layers 42 a and 42 b described below are directly disposed on the laminate 2 may be adopted.

[0051] The first base electrode layer 41a and the second base electrode layer 41b are not limited to baked layers, but may be thin film layers. The thin film layers are formed by thin film forming methods such as sputtering or evaporation. The thin film layers are layers of 1 μm or less in which metal particles are deposited.

[0052] The first plating layer 42a is arranged to cover the first base electrode layer 41a.

[0053] The second plating layer 42b is arranged to cover the second base electrode layer 41b.

[0054] The first plating layer 42a and the second plating layer 42b may include, for example, at least one selected from Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc. The first plating layer 42a and the second plating layer 42b may each be formed of a plurality of layers.

[0055] The first plating layer 42a and the second plating layer 42b are preferably a two-layer structure in which Sn plating layers 422a and 422b are formed on Ni plating layers 421a and 421b, respectively. In this case, the Ni plating layers 421a and 421b prevent the first base electrode layer 41a and the second base electrode layer 41b from being corroded by the solder when the multilayer ceramic capacitor 1 is mounted. In addition, the Sn plating layer improves the wettability of the solder when the multilayer ceramic capacitor 1 is mounted. As a result, the mounting of the multilayer ceramic capacitor 1 is facilitated. In the case where the first plating layer 42a and the second plating layer 42b are respectively set as a two-layer structure of a Ni plating layer and a Sn plating layer, the thickness of each of the Ni plating layer and the Sn plating layer is preferably greater than 2μm and less than 15μm.

[0056] The surfaces of the first external electrode 4 a and the second external electrode 4 b when viewed in plan from the longitudinal direction L are covered with the insulating layer 8 except for a frame region 9 having a width of 1 μm to 100 μm from the outer periphery.

[0057] When the external electrode is composed of a base electrode layer and a plating layer, the insulating layer can be configured in a given range on the surface of the plating layer. However, when the insulating layer is configured in a given range on the surface of the base electrode layer, the plating layer is formed on the surface of the base electrode layer except for the range where the insulating layer is configured.

[0058] Furthermore, when the plating layer includes multiple layers, an insulating layer can be arranged in a given range on the surface of the plating layer that becomes the outermost layer. However, when an insulating layer is arranged on the surface of a plating layer of any layer other than the outermost layer, the plating layer arranged on the plating layer on which the insulating layer is arranged is set to have a structure in which the plating layers are stacked on a portion excluding the range in which the insulating layer is arranged, and the insulating layer is arranged on the surface of an external electrode that may contact a solder fillet.

[0059] exist Figure 2In the illustrated embodiment, on the first base electrode layer 41a and the second base electrode layer 41b which respectively constitute the first external electrode 4a and the second external electrode 4b, with respect to the surface when viewed from the length direction L, an insulating layer 8 is formed in an area other than a frame area 9 having a width of 1 μm to 100 μm from the outer peripheral edge, and Ni plating layers 421a, 421b and Sn plating layers 422a, 422b are formed on the surfaces of the first base electrode layer 41a and the second base electrode layer 41b except for the area where the insulating layer 8 is arranged.

[0060] The laminated ceramic capacitor 1 is coated with solder on the surface of the first external electrode 4a and the second external electrode 4b below the insulating layer 8, and connected to the connection pads 51a and 51b. By providing the frame area 9, a solder fillet can be formed within a range of a certain height from the bottom of the outer periphery, so that it can be reliably connected to the wiring substrate.

[0061] The material of the insulating layer 8 is not particularly limited as long as it has insulating properties, but synthetic resin is preferred because it can easily form an insulating layer on the surface of the external electrode. As the synthetic resin, thermosetting resins such as epoxy resins, polyimide resins, and phenolic resins, and thermoplastic resins such as polyethylene resins and polyamide resins can be used.

[0062] When viewed from the longitudinal direction L, by configuring the insulating layer 8 on the surface of the first external electrode 4a and the second external electrode 4b corresponding to the region where the internal electrode layer 6 is stacked, it is possible to prevent the solder fillets 52a and 52b from wetting and climbing to the height where the internal electrode layer 6 is configured during mounting. This can effectively suppress the generation of vibration sound caused by the piezoelectric phenomenon.

[0063] The insulating layer 8 is formed in such a shape that the thickness in the longitudinal direction L is 200 μm or less and the thickness is greatest at the approximate center when viewed in the longitudinal direction L. This prevents the multilayer ceramic capacitor from becoming larger in size, and when mounted on a wiring board, the central portion of the surface of the insulating layer protrudes outward relative to the bottom portion, thereby reliably preventing wetting and climbing of the solder fillet.

[0064] The multilayer ceramic capacitor 1 is mounted by applying solder to the surfaces of the first external electrode 4a and the second external electrode 4b and connecting them to the lands 51a and 51b. However, the conventional multilayer ceramic capacitor 1 is Figure 5 As shown, the height of the wetting climb of the solder fillets 52a and 52b formed during mounting is high. If it reaches the height where the internal electrode layer 6 is arranged, a piezoelectric phenomenon of the dielectric will occur, and the multilayer ceramic capacitor 1 is likely to cause expansion and contraction vibration.

[0065] exist Figure 4, an example of mounting the multilayer ceramic capacitor 1 according to the present embodiment is shown. The multilayer ceramic capacitor 1 is provided with an insulating layer 8 in a given range on the surface of the first external electrode 4a and the second external electrode 4b, so that the height of the wetting climb of the solder legs 52a and 52b is suppressed to be low, and the generation of vibration sound caused by the piezoelectric phenomenon can be suppressed.

[0066] (Confirmation test)

[0067] A test to confirm the effect of suppressing vibration noise was performed on the multilayer ceramic capacitor according to the present invention.

[0068] In the confirmation test, the sound pressure (dB) of the vibration sound generated when DC 3V and AC 1V were applied was measured for an embodiment of the present invention in which an insulating layer was configured in a given range on the surface of the external electrode, and a comparative example in which a conventional multilayer ceramic capacitor without an insulating layer was used as a sample.

[0069] like Figure 6 As shown, in the multilayer ceramic capacitor (Example) of the present invention, it was confirmed that the vibration of the dielectric caused by the piezoelectric phenomenon generated when mounted on a wiring board can be suppressed, and the harsh vibration sound can be reduced.

[0070] The embodiments of the present invention have been described above, but the present invention is not limited to the embodiments and can be implemented in various ways within the scope of the present invention. For example, the embodiments show an example in which the insulating layer 8 is provided on both the first external electrode 4a and the second external electrode 4b, but the same effect can be expected when the insulating layer 8 is provided on either the first external electrode 4a or the second external electrode 4b.

[0071] The present invention is as follows.

[0072] <1>

[0073] A laminated ceramic capacitor comprises: a laminated body in which dielectric layers and internal electrode layers are alternately laminated; and external electrodes are respectively arranged on end faces of both sides of the laminated body in a longitudinal direction perpendicular to the lamination direction and connected to the internal electrode layers, wherein:

[0074] The surface of the external electrode when viewed in plan from the longitudinal direction is covered with an insulating layer except for a frame region having a width of 1 μm to 100 μm from the outer peripheral edge.

[0075] <2>

[0076] according to <1> The multilayer ceramic capacitor, wherein:

[0077] The surface of the external electrode corresponding to a region where the internal electrode layers are stacked when viewed in plan from the longitudinal direction is covered with the insulating layer.

[0078] <3>

[0079] according to <1> or <2> The multilayer ceramic capacitor, wherein:

[0080] The insulating layer has a thickness in the longitudinal direction of 200 μm or less and is thickest at a substantially center thereof when viewed in the longitudinal direction.

[0081] <4>

[0082] A mounting structure of a multilayer ceramic capacitor having <1> to <3> The multilayer ceramic capacitor, the connection pad disposed on a wiring substrate, and the solder connecting the external electrode of the multilayer ceramic capacitor and the connection pad as described in any one of the preceding claims, wherein:

[0083] The solder is arranged below the insulating layer.

[0084] Description of Reference Numerals

[0085] 1: Multilayer ceramic capacitor;

[0086] 2: laminate;

[0087] 3: Inner layer;

[0088] 4: External electrode;

[0089] 4a: 1st external electrode;

[0090] 4b: second external electrode;

[0091] 5: dielectric layer;

[0092] 5a: dielectric layer;

[0093] 5b: dielectric layer;

[0094] 6: Internal electrode layer;

[0095] 6a: 1st internal electrode layer;

[0096] 6b: second internal electrode layer;

[0097] 7: outer layer;

[0098] 8: Insulation layer;

[0099] 9: frame area;

[0100] 41a: first base electrode layer;

[0101] 41b: second base electrode layer;

[0102] 42a: first plating layer;

[0103] 42b: second plating layer;

[0104] 421a: Ni plating layer;

[0105] 421b: Ni plating layer;

[0106] 422a: Sn plating layer;

[0107] 422b: Sn plating layer;

[0108] 50: Wiring substrate;

[0109] 51a: connection plate;

[0110] 51b: connection plate;

[0111] 52a: welding foot;

[0112] 52b: welding foot;

[0113] TS1: 1st main surface;

[0114] TS2: 2nd main surface;

[0115] WS1: side 1;

[0116] WS2: side 2;

[0117] LS1: 1st end face;

[0118] LS2: Second end face.

Claims

1. A laminated ceramic capacitor comprising: a laminated body in which dielectric layers and internal electrode layers are alternately laminated; and external electrodes are respectively arranged on end faces of both sides of the laminated body in a longitudinal direction perpendicular to the lamination direction and connected to the internal electrode layers, wherein: The surface of the external electrode when viewed in plan from the longitudinal direction is covered with an insulating layer except for a frame region having a width of 1 μm to 100 μm from the outer peripheral edge.

2. The multilayer ceramic capacitor according to claim 1, wherein The surface of the external electrode corresponding to a region where the internal electrode layers are stacked when viewed in plan from the longitudinal direction is covered with the insulating layer.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein: The insulating layer has a thickness in the longitudinal direction of 200 μm or less and is thickest at a substantially center thereof when viewed in the longitudinal direction.

4. A mounting structure of a multilayer ceramic capacitor, comprising the multilayer ceramic capacitor according to any one of claims 1 to 3, a connection pad arranged on a wiring substrate, and solder connecting the external electrode of the multilayer ceramic capacitor and the connection pad, wherein: The solder is arranged below the insulating layer.

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