Carry stacked CMOS current type coding summing circuit

Abstract

The invention discloses a carry-stacked CMOS (complementary metal oxide semiconductor) current-mode coding summing circuit, which comprises an n-value carry-stacked current-mode circuit, the circuit comprises two outputs, n-1 internal threshold comparators and n-1 internal carry, the value of each internal carry is determined by a corresponding internal threshold comparator, the threshold value of the internal comparator is related to a system value, and the n-value carry-stacked current-mode circuit comprises two outputs, n-1 internal threshold comparators and n-1 internal carry. The threshold of the threshold comparator corresponding to the xth internal carry is x * n-0. 5; the output carry C is the sum of the n internal carry, and the output standard is the product of the total input minus the number of system and the output carry S = In-n * C. According to the invention, a plurality of internal carry bits are calculated through a plurality of comparators, an output carry bit is formed by superposing an internal carry bit result, an output standard is calculated through an input value and the output carry bit, power consumption is reduced in coding summation application, a critical path is shortened, and meanwhile, the method can be applied to summation of multiple operands.

Description

Technical Field

[0001] The invention belongs to the technical field of circuit electronics, and in particular relates to a carry stacking CMOS current-type coding summation circuit. Background Art

[0002] With the development of integrated circuits, the size of integrated circuit processes has been continuously reduced, and the number of transistors per unit area has increased exponentially. The researchers' attention has also shifted from area overhead to performance and power consumption issues. In order to achieve higher efficiency, multi-value circuits have been introduced, but voltage-type circuits have many restrictions and are not suitable for the development of multi-value circuits. Current-type signals are more stable. At the same time, compared with voltage-type circuit signals, current signals are easier to implement addition operations through Kirchhoff's law. Therefore, they have more advantages in operations such as encoding and summation, and are more convenient in multi-value logic design. Therefore, they have become a field of extensive concern for researchers. Another major feature of current-type signals is that the dependence between power consumption and device technology is low. Since its internal logic is mostly composed of current-type signals, the current required internally is mostly constant, so the impact of different device processes on the power consumption of current-type circuits is relatively small. While facilitating design, a series of problems caused by the compromise between controlling power consumption and device technology in cost will also be solved to a certain extent.

[0003] At present, in voltage-type circuits, multiplication operations are usually implemented using the shift-and-add method. Therefore, the speed of adding multiple operands directly affects the computing speed of the chip. How to implement the sum of multiple operands with high speed, high efficiency and low power consumption has always been the direction of research by many researchers. In the design of large-scale integrated circuits, the area and power consumption of the chip have always been important considerations. The traditional method of adding multiple numbers in pairs requires a large number of adders and complex connections when the number of operands is large, resulting in excessive hardware overhead and low efficiency. The research on multi-operand addition aims to design a more efficient circuit structure, reduce the occupation of hardware resources, and reduce the cost and power consumption of chip computing design. In the processing of digital signals such as audio and video, it is often necessary to perform fast arithmetic operations on a large amount of data. For example, the filtering of audio signals, the encoding and decoding of video images, etc., all involve a large number of addition operations. The multi-operand adder can add multiple operands in one operation cycle, which improves the efficiency and speed of digital signal processing and meets the real-time requirements of digital signal processing. CMOS technology is one of the mainstream technologies of integrated circuits at present. The integration of current-mode circuits and CMOS technology can give full play to the advantages of both. The current-mode circuits manufactured using CMOS technology can achieve lower power consumption and higher integration while maintaining better performance and stability. However, in the current-mode circuits under CMOS technology, although there are other ways to realize the operation function, such as analog multiplier circuits composed according to the characteristics of transistors, they still face problems such as limited input value range and complex serial coding. Therefore, in the current-mode circuits, how to realize the addition of multiple operands and signal coding faster and more conveniently is still a direction that logic computing design researchers need to explore, and it also plays an important role in the development of current-mode circuits. Summary of the invention

[0004] In order to make up for the deficiencies of the prior art, the present invention aims to provide a carry stacking CMOS current-type coding summation circuit, which increases the carry range of the summation circuit, improves the data utilization rate of the CMOS current-type circuit, and realizes summation coding at high speed and low power consumption.

[0005] The technical problem solved by the present invention can be achieved by the following technical solutions:

[0006] The present invention discloses a carry stacking CMOS current-mode coding summing circuit, comprising an n-value carry stacking current-mode circuit, wherein the n-value carry stacking current-mode circuit comprises 2 outputs, n-1 internal threshold comparators and n-1 internal carries: the value of each internal carry is determined by a corresponding internal threshold comparator, the threshold value of the internal comparator is related to the base value, and the threshold value of the threshold comparator corresponding to the x-th internal carry is x×n-0.5; the output carry C is the sum of n internal carries, and the output base is the total input minus the product of the base number and the output carry: S=In-n×C; wherein In is the input, the value of In of a single unit is {0, 1, 2, ..., n×n-1}, and the value ranges of the output carry C and the output base S are both {0, 1, 2, ..., n-1}.

[0007] Furthermore, the total input of the n-value carry stacking current type circuit converges on the same NMOS node, and multiple identical total input currents are obtained through multiple NMOS current mirrors, which are connected with multiple different threshold currents composed of PMOS to form multiple internal comparators, and the output of the internal comparator is used to control the subsequent stage switch to obtain the internal carry of the corresponding part;

[0008] The internal carry is input to the connection of a NOS tube whose gate is connected to the drain. By adopting the same width-to-length ratio as the base ratio, a current of a base multiple of the output carry is copied to form a stacked partial circuit, which is connected to the current mirror gate that copies the total input to obtain subtraction, and then the output base is obtained by copying the result after subtraction.

[0009] Furthermore, the n-value carry stacking current-type circuit can pre-set the base and determine the level according to the target code; it can also pre-set the level and determine the base according to the target code.

[0010] Furthermore, the process of determining the base selection according to the target encoding is as follows:

[0011] S1. Determine the number of output digits and the number of internal carries of a single carry stack circuit unit according to the target base and system input content. The number of output digits is the total number of modules required. The primary module outputs two digits of the base and carry, and the secondary module outputs three digits. The number of internal carries of a single carry stack circuit unit is the base number minus one.

[0012] S2. Design a single carry stack circuit unit according to the target base, the internal carry of the single carry stack current type circuit unit is obtained by an internal comparator composed of multiple current mirrors, and the threshold values ​​of the multiple internal comparators are related to the base value; the comparator threshold for generating the first internal carry is n×(n-1)-0.5, that is, the width-to-length ratio of the current mirror PMOS tube flowing through the current mirror is n×(n-1)-0.5 times that of the reference current flowing through the current mirror PMOS tube; the second internal carry comparator threshold is generated as n×(n-2)-0.5, that is, the width-to-length ratio of the PMOS transistor flowing through the current mirror is n×(n-2)-0.5 times that of the reference current flowing through the current mirror PMOS tube, and so on; the output of the corresponding internal carry comparator is used as the switch of the subsequent internal carry, the internal carry is added to obtain the output base, and the base multiple of the output base is subtracted from the output end to obtain the output base;

[0013] S3. Determine the hierarchy according to the number of output bits and connect the circuit units in series to achieve the required encoding.

[0014] Furthermore, in step S3, when the total value of the system input is greater than or equal to the square of the base number, it will be composed of three or more units; if the total input is infinite and the base number is n, the hierarchical connection method is: the total input of each unit is n×n-1, and the base output of each n+1 carry stacking circuit unit in the first layer is connected to an additional carry stacking circuit unit to obtain an output base and an output carry, wherein the base is used as the total output base of the n+1 carry stacking circuit units; the carry outputs of the n+1 carry stacking circuit units are connected to the total input of the first unit in the second layer to obtain the output carry and output base of the first carry stacking circuit unit in the second layer; the carry outputs of the additional carry stacking circuit units in the first layer are connected to the inputs of the additional carry stacking circuit units in the second layer for every n+1 carry outputs, and the operation is repeated until only one base output of the first layer is left, at which point the input and output base and output carry of all the second layer units are obtained; and the entire connection method is obtained by analogy, presenting a diamond distribution in the overall logic.

[0015] Furthermore, the process of determining the level according to the target encoding is:

[0016] R1. Calculate the total input of a single carry stacking circuit unit according to the level and the total input of the system, calculate the base of the single carry stacking circuit unit according to the root of the total input, and determine the number of internal carries according to the base; the internal carry is obtained by an internal comparator composed of multiple current mirrors, and the threshold values ​​of the multiple internal comparators are related to the base value. The comparator threshold for generating the first internal carry is n×(n-1)-0.5, that is, the width-to-length ratio of the current mirror PMOS tube flowing through the current mirror is n×(n-1)-0.5 times that of the current mirror PMOS tube flowing through the reference current; the second internal carry comparator threshold is generated as n×(n-2)-0.5, that is, the width-to-length ratio of the current mirror PMOS tube flowing through the current mirror is n×(n-2)-0.5 times that of the current mirror PMOS tube flowing through the reference current, and so on. The output of the corresponding internal carry comparator is used as the switch of the subsequent internal carry, and the internal carries are added to obtain the output base, and the base multiple of the output base is subtracted from the output end to obtain the output base;

[0017] R2. Connect the individual units in series to achieve the required encoding.

[0018] Furthermore, in step R2, when the target number of bits is determined, if the base number is n, the hierarchical connection method is: the total input of each unit is n×n-1, and the base output of every n+1 carry stacking circuit units in the first layer is connected to an additional carry stacking circuit unit to obtain an output base and output carry, wherein the base is used as the total output base of the n+1 carry stacking circuit units, and the carry outputs of the n+1 carry stacking circuit units are connected to the total input of the first unit in the second layer to obtain the output carry and output base of the first carry stacking circuit unit in the second layer; the carry outputs of the additional carry stacking circuit units in the first layer are connected to the inputs of the additional carry stacking circuit units in the second layer for every n+1 carry outputs, and the operation is repeated until only one base output of the first layer is left, at which point the input and output base and output carry of all the second layer units are obtained, and the entire connection method is obtained by analogy.

[0019] Furthermore, in the n-value carry stacked current-type circuit, the value range of each internal carry is {0, 1}, and the value range of the output carry obtained by adding the internal carries is {0, 1, 2, ... n-2, n-1}, which is consistent with the value range of the output base; the output base is generated by subtracting the total input from a multiple of the output carry, and when the internal carries are not all 0, the output base of the design unit lags behind the output carry by one gate level in delay; when the internal carries are all 0, that is, the output carry is 0, it does not affect the generation of the output base, and the output base of the design unit will also be reduced by one gate level in delay.

[0020] Compared with the prior art, the present invention has the following advantages:

[0021] (1) The bit stacking CMOS current-mode coded summation circuit unit of the present invention proposes a new logic theory about carry and a design structure of carry stacking, which reduces power consumption and shortens the critical path in coded summation applications, and can be applied to multi-operand summation. The carry logic theory involved is: in an n-ary circuit, the value of the output carry is consistent with the output base, which is 0 to n; the carry stacking circuit involved is: multiple comparators are used to calculate multiple internal carries, and the output carry is formed by superimposing the internal carry results to form an output carry, and then the output base is calculated by the input value and the output carry.

[0022] (2) The present invention receives and replicates signals through a current mirror composed of NMOS tubes with a larger width-to-length ratio, thereby reducing errors in the signal reception process, and then replicates and outputs through a current mirror composed of smaller PMOS tubes to reduce errors at the next stage of signal reception. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a circuit diagram of a quaternary carry stacking CMOS current-mode coding summation circuit according to Embodiment 1 of the present invention;

[0024] Figure 2 A circuit diagram of a ternary carry stacked CMOS current-mode coded summation circuit according to Embodiment 2 of the present invention;

[0025] Figure 3 This is a series connection model diagram of a quaternary carry stacked CMOS current-mode coded summation circuit according to Embodiment 3 of the present invention. DETAILED DESCRIPTION

[0026] In order to enable those skilled in the art to more clearly understand the technical solution of the present application, a carry stacking CMOS current-mode coded summation circuit of the present invention is further described below in conjunction with the accompanying drawings.

[0027] The present invention proposes a new logic theory of carry and a design method for carry stacking. The carry logic theory is: in an n-base circuit, the value of the output carry is also 0 to n; then a design method for a carry stacking circuit is proposed based on the carry theory, multiple internal carries are calculated by multiple comparators, the output carry is formed by superimposing the internal carry results to form a total carry, and then the output carry is calculated by the input value and the output total carry. The specific content is detailed as follows:

[0028] A carry stacking CMOS current-mode coded summing circuit comprises an n-value carry stacking current-mode circuit, wherein the n-value carry stacking current-mode circuit comprises 2 outputs, n-1 internal threshold comparators and n-1 internal carries: the value of each internal carry is determined by a corresponding internal threshold comparator, the threshold value of the internal comparator is related to the base value, and the threshold value of the threshold comparator corresponding to the x-th internal carry is x×n-0.5; the output carry C is the sum of the n internal carries, and the output base is the product of the total input minus the base number and the output carry: S=In-n×C; wherein In is the input, the value of In of a single unit is {0, 1, 2, ..., n×n-1}, and the value ranges of the output carry C and the output base S are both {0, 1, 2, ..., n-1}.

[0029] The total input of the n-value carry stacking current type circuit converges on the same NMOS node, and multiple identical total input currents are obtained through multiple NMOS current mirrors, which are connected with multiple different threshold currents composed of PMOS to form multiple internal comparators. The output of the internal comparator controls the subsequent switches to obtain the corresponding internal carry. The internal carry is input to the NOS tube connection connected to the gate and the drain, and a current with a multiple of the output carry is copied by using the same width-to-length ratio as the base ratio to form a stacking part circuit, which is connected to the current mirror gate that copies the total input to obtain subtraction, and then the output base is obtained by copying the result after subtraction.

[0030] The n-value carry stacking current type circuit of the present application can pre-set the base and determine the level according to the target code; it can also pre-set the level and determine the base according to the target code.

[0031] The process of determining the base selection according to the target encoding is:

[0032] (1) The number of output bits and the number of internal carries of a single carry stacking circuit unit are determined according to the target base and the system input content. The number of output bits is the total number of modules required. The first-level module outputs two digits of the base and the carry, and the second-level module outputs three digits. The number of internal carries of a single carry stacking circuit unit is the base number minus one.

[0033] (2) A single carry stack circuit unit is designed according to the target base. The internal carry of the single carry stack current type circuit unit is obtained by an internal comparator composed of multiple current mirrors. The threshold values ​​of the multiple internal comparators are related to the base value. The comparator threshold for generating the first internal carry is n×(n-1)-0.5, that is, the width-to-length ratio of the current mirror PMOS tube through which the current flows is n×(n-1)-0.5 times that of the current mirror PMOS tube through which the reference current flows. The comparator threshold for generating the second internal carry is n×(n-2)-0.5, that is, the width-to-length ratio of the PMOS transistor through which the current mirror flows is n×(n-2)-0.5 times that of the current mirror PMOS tube through which the reference current flows, and so on. The output of the corresponding internal carry comparator is used as the switch of the subsequent internal carry. The internal carries are added to obtain the output base, and the base multiple of the output base is subtracted from the output end to obtain the output base.

[0034] (3) Determine the hierarchy based on the number of output bits and connect the circuit units in series to achieve the required coding.

[0035] When the total value of the system input is greater than or equal to the square of the base number, it will be composed of three or more units; if the total input is infinite and the base number is n, the hierarchical connection method is: the total input of each unit is n×n-1, and the base output of each n+1 carry stacking circuit unit in the first layer is connected to an additional carry stacking circuit unit to obtain an output base and an output carry, where the base is used as the total output base of the n+1 carry stacking circuit units; the carry output of the n+1 carry stacking circuit units is connected to the total input of the first unit in the second layer to obtain the output carry and output base of the first carry stacking circuit unit in the second layer; the carry output of the additional carry stacking circuit unit in the first layer is connected to the input of the additional carry stacking circuit unit in the second layer for every n+1 carry outputs, and the operation is repeated until only one base output of the first layer is left, at which point the input and output base and output carry of all the second layer units are obtained; and the entire connection method is obtained by analogy, presenting a diamond distribution in the overall logic.

[0036] The process of determining the level according to the target coding is as follows:

[0037] (1) Calculate the total input of a single carry stacking circuit unit according to the level and the total input of the system, calculate the base of the single carry stacking circuit unit according to the root of the total input, and determine the number of internal carries according to the base; the internal carry is obtained by an internal comparator composed of multiple current mirrors, and the threshold values ​​of the multiple internal comparators are related to the base value. The comparator threshold for generating the first internal carry is n×(n-1)-0.5, that is, the width-to-length ratio of the current mirror PMOS tube flowing through the current mirror is n×(n-1)-0.5 times that of the current mirror PMOS tube flowing through the reference current; generate the second internal carry comparator threshold as n×(n-2)-0.5, that is, the width-to-length ratio of the current mirror PMOS tube flowing through the current mirror is n×(n-2)-0.5 times that of the current mirror PMOS tube flowing through the reference current, and so on. The output of the corresponding internal carry comparator is used as the switch of the subsequent internal carry, and the internal carries are added to obtain the output base, and the base multiple of the output base is subtracted from the output end to obtain the output base;

[0038] (2) Connect the individual units in series to achieve the required coding.

[0039] When the target number of bits is determined, if the base number is n, the hierarchical connection method is: the total input of each unit is n×n-1, and the base output of every n+1 carry stacking circuit units in the first layer is connected to an additional carry stacking circuit unit to obtain an output base and output carry, wherein the base is used as the total output base of the n+1 carry stacking circuit units, and the carry outputs of the n+1 carry stacking circuit units are connected to the total input of the first unit in the second layer to obtain the output carry and output base of the first carry stacking circuit unit in the second layer; the carry outputs of the additional carry stacking circuit units in the first layer are connected to the inputs of the additional carry stacking circuit units in the second layer for every n+1 carry outputs, and the operation is repeated until only one base output of the first layer is left, at which point the input and output base and output carry of all the second layer units are obtained, and the entire connection method is obtained by analogy.

[0040] In the above-mentioned n-value carry stacking current type circuit, the value range of each internal carry is {0, 1}, and the value range of the output carry obtained by adding the internal carries is {0, 1, 2, ... n-2, n-1}, which is consistent with the value range of the output standard. The output standard is generated by summing the output carries and then copying them in multiples, subtracting the total input, and lagging behind the output carry. The lag time is the copying and subtraction of the current mirror. It can also be used for cascading to achieve multi-bit multi-operand summation. In the cascade connection, it is necessary to add a current mirror with a smaller width-to-length ratio as a signal follower. The ratio of the width-to-length ratio of the signal follower to the input end also determines the cascade error. The larger the ratio, the smaller the error, and vice versa. The established logic can be realized without additionally connecting a signal follower. Therefore, the present invention can effectively improve the data utilization rate of the logic unit. In the logic, no matter how many bits or values ​​the target code is, the single unit design method is always the same. While improving the performance of the coding summation circuit, it standardizes the design process of multi-value coding to a certain extent.

[0041] Example 1

[0042] like Figure 1 As shown, a four-value carry stacked CMOS current-type coded summation circuit based on the carry stacked CMOS current-type coded summation circuit of the present invention includes 12 PMOS tubes (recorded as P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12) and 7 NMOS tubes (recorded as N1, N2, N3, N4, N5, N6, N7), and the calculation is divided into two stages: carry evaluation and local evaluation. The input signal is connected to the drain of N1 and connected to the gate. The current mirror formed by the connection of N2, N3, and N4 is copied into multiple identical currents, which are compared with different thresholds respectively. When the input current is greater than the corresponding threshold current, the corresponding PMOS tube is turned on, and the corresponding internal carry value is logic 1. Otherwise, the corresponding internal carry value is logic 0. All internal carries are superimposed to obtain an output carry. The output bit is obtained by subtracting the current of the base multiple of the output carry at the drain of N6 and then copying the result through the current mirror.

[0043] Example 2

[0044] like Figure 2As shown, a three-value carry stacking CMOS current-type coding summation circuit based on the carry stacking CMOS current-type coding summation circuit of the present invention includes 9 PMOS tubes (recorded as P1, P2, P3, P4, P5, P6, P7, P8, P9) and 5 NMOS tubes (recorded as N1, N2, N3, N4, N5), which is the same as the four-value circuit carry stacking CMOS current-type coding summation circuit, and is divided into two stages: the carry output end and the base output end. The specific working principle is as follows: when the input signal arrives, the multi-channel current copied by the current mirror is compared with different thresholds respectively. When it is greater than the corresponding threshold, the PMOS tube corresponding to it is turned on to obtain the corresponding internal carry, and the internal carry is superimposed to obtain the total carry. The output base is obtained by subtracting the copied current of the total carry multiple at the drain stage of N5. Similarly, carry stacking CMOS current-type coding summation circuits of other bases can also be obtained by this method.

[0045] Example 3

[0046] like Figure 3 As shown, a four-bit carry stacking circuit series circuit based on a four-value circuit carry stacking CMOS current-type coding summation circuit. Each module in the figure represents a carry stacking CMOS current-type coding summation circuit, which is composed of four embodiments 1. Figure 1 The same carry stacking current type CMOS coding summation circuit unit shown is combined, with four input signals A, B, C, D and output signals S0, S1, S2, S3, C; A0, B0, C0, D0 of the four input signals are connected to the first carry stacking current type CMOS coding summation circuit unit, A1, B1, C1, D1 are connected to the second carry stacking current type CMOS coding summation circuit unit, A2, B2, C2, D2 are connected to the third carry stacking current type CMOS coding summation circuit unit, and A3, B3, C3, D3 are connected to the fourth carry stacking current type CMOS coding summation circuit unit. The calculation cycle of the cascade circuit of the carry stacking circuit is the sum of the calculation cycles of the four carry stacking current type CMOS coding summation circuit units. The output carry value range of the fourth carry stacking current type CMOS coding summation circuit unit is {0,1,2,3}, which can be expanded to more bits.

[0047] The multi-value carry stacking CMOS current-mode coding summation circuit designed by the present invention increases the carry range of the summation circuit, improves the data utilization rate of the CMOS current-mode circuit, and realizes summation coding at high speed and low power consumption. The proposed four-bit carry stacking circuit cascade circuit achieves low latency and low power consumption, simplifies the design structure, and reduces the design complexity of the multi-bit multi-operand summation circuit design.

[0048] The coding performance of the quaternary carry stacking circuit is compared with that of the traditional full adder under the power supply voltage of 3.3V and 27℃. The measured values ​​are shown in Table 1.

[0049] Table 114-bit and 15-bit binary sum coding simulation results

[0050]

[0051] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A carry stacking CMOS current-mode coded summation circuit, characterized in that: The invention comprises an n-value carry stacked current type circuit, which comprises 2 outputs, n-1 internal threshold comparators and n-1 internal carries; the value of each internal carry is determined by a corresponding internal threshold comparator, the threshold value of the internal comparator is related to the base value, and the threshold value of the threshold comparator corresponding to the x-th internal carry is x×n-0.5; the output carry C is the sum of the n internal carries, and the output base S is the product of the total input minus the base number and the output carry: S=In-n×C; wherein, In is the input, the value of In of a single unit is {0,1,2,…,p×n-1}, and the value ranges of the output carry C and the output base S are both {0,1,2,…,n-1}.

2. A carry stacking CMOS current-mode coding summation circuit according to claim 1, characterized in that: The total input of the n-value carry stacking current type circuit is gathered at the same NMOS node, and multiple identical total input currents are obtained through multiple NMOS current mirrors, which are connected with multiple different threshold currents composed of PMOS to form multiple internal comparators, and the output of the internal comparator is used to control the subsequent stage switch to obtain the internal carry of the corresponding part; The internal carry is input to the connection of an NMOS tube whose gate is connected to the drain. By adopting the same width-to-length ratio as the base ratio, a current of a base multiple of the output carry is copied to form a stacked partial circuit, which is connected to the current mirror gate that copies the total input to obtain subtraction, and then the output base is obtained by copying the result after subtraction.

3. A carry stacking CMOS current-mode coded summation circuit according to claim 2, characterized in that: The n-value carry stacking current type circuit can preset the base and determine the level according to the target code; it can also preset the level and determine the base according to the target code.

4. A carry stacking CMOS current-mode coding summation circuit according to claim 3, characterized in that: The process of determining the base selection according to the target encoding is: S1. Determine the number of output digits and the number of internal carries of a single carry stack circuit unit according to the target base and system input content. The number of output digits is the total number of modules required. The primary module outputs two digits of the base and carry, and the secondary module outputs three digits. The number of internal carries of a single carry stack circuit unit is the base number minus one. S2. Design a single carry stack circuit unit according to the target base, the internal carry of the single carry stack current type circuit unit is obtained by an internal comparator composed of multiple current mirrors, and the threshold values ​​of the multiple internal comparators are related to the base value; the comparator threshold for generating the first internal carry is n×(n-1)-0.5, that is, the width-to-length ratio of the current mirror PMOS tube flowing through the current mirror is n×(n-1)-0.5 times that of the reference current flowing through the current mirror PMOS tube; the second internal carry comparator threshold is generated as n×(n-2)-0.5, that is, the width-to-length ratio of the PMOS transistor flowing through the current mirror is n×(n-2)-0.5 times that of the reference current flowing through the current mirror PMOS tube, and so on; the output of the corresponding internal carry comparator is used as the switch of the subsequent internal carry, the internal carry is added to obtain the output base, and the base multiple of the output base is subtracted from the output end to obtain the output base; S3. Determine the hierarchy according to the number of output bits and connect the circuit units in series to achieve the required encoding.

5. A carry stacking CMOS current-mode coding summation circuit according to claim 4, characterized in that: In the step S3, when the total value of the system input is greater than or equal to the square of the base number, it will be composed of three or more units; if the total input is infinite and the base number is n, the hierarchical connection method is: the total input of each unit is n×n-1, and the base output of each n+1 carry stacking circuit unit of the first layer is connected to an additional carry stacking circuit unit to obtain an output base and an output carry, wherein the base is used as the total output base of the n+1 carry stacking circuit units; the carry output of the n+1 carry stacking circuit units is connected to the total input of the first unit of the second layer to obtain the output carry and output base of the first carry stacking circuit unit of the second layer; Connect the carry outputs of the extra carry stacking circuit units in the first layer to the inputs of the extra carry stacking circuit units in the second layer for every n+1, and repeat the operation until only one bit of the first layer's base output is left. At this point, the input and output base and output carry of all the second layer units are obtained; and the entire connection method is obtained by analogy, presenting a diamond distribution in the overall logic.

6. The carry stacking CMOS current-mode coding summation circuit according to claim 3, characterized in that: The process of determining the level according to the target code is as follows: R1. Calculate the total input of a single carry stack circuit unit according to the level and the total input of the system, take the root of the total input, calculate the base of a single carry stack circuit unit, and determine the number of internal carries according to the base; The internal carry is obtained by an internal comparator composed of multiple current mirrors. The threshold values ​​of the multiple internal comparators are related to the base value. The comparator threshold for generating the first internal carry is n×(n-1)-0.5, that is, the width-to-length ratio of the current mirror PMOS tube through which the reference current flows is n×(n-1)-0.5 times that of the current mirror PMOS tube through which the reference current flows; the comparator threshold for generating the second internal carry is n×(n-2)-0.5, that is, the width-to-length ratio of the current mirror PMOS tube through which the reference current flows is n×(n-2)-0.5 times that of the current mirror PMOS tube through which the reference current flows, and so on. The output of the corresponding internal carry comparator is used as a switch for the subsequent internal carry. The internal carries are added to obtain the output base, and the base multiple of the output base is subtracted from the output end to obtain the output base. R2. Connect the individual units in series to achieve the required encoding.

7. A carry stacking CMOS current-mode coding summation circuit according to claim 6, characterized in that: In step R2, when the target number of bits is determined, if the base number is n, the hierarchical connection method is as follows: the total input of each unit is n×n-1, and the local output of each n+1 carry stacking circuit unit of the first layer is connected to an additional carry stacking circuit unit to obtain an output local and an output carry, wherein the local is used as the total output local of the n+1 carry stacking circuit units, and the carry output of the n+1 carry stacking circuit units is connected to the total input of the first unit of the second layer to obtain the output carry and the output local of the first carry stacking circuit unit of the second layer; Connect the carry outputs of the extra carry stacking circuit units in the first layer to the inputs of the extra carry stacking circuit units in the second layer every n+1, and repeat the operation until only one bit of the first layer's standard output is left. At this point, the input and output standard and output carry of all the second layer units are obtained, and so on to obtain the entire connection method.

8. A carry stacking CMOS current-mode coding summation circuit according to any one of claims 1 to 7, characterized in that: In the n-value carry stacked current-mode circuit, the value range of each internal carry is {0,1}, and the value range of the output carry obtained by adding the internal carries is {0,1,2,…n-2,n-1}, which is consistent with the value range of the output standard; the output standard is generated by subtracting the total input from the multiple of the output carry, and when the internal carries are not all 0, the output standard of the design unit lags behind the output carry by one gate level in delay; When the internal carry bits are all 0, that is, the output carry bit is 0, it will not affect the generation of the output bit, and the output bit of the design unit will also be reduced by one gate level in delay.

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