PCIe bandwidth allocation device and electronic equipment

Abstract

The invention discloses a PCIe bandwidth allocation device and electronic equipment. A card type judgment module in the allocation device is connected with a PCIe slot and a switching circuit; the switching circuit is connected with the N memories; and a PCIe card is inserted into the PCIe slot. The card type judgment module generates a second signal according to a first signal from the PCIe card and sends the second signal to the switching circuit, the first signal indicates that the card type judgment module determines the type of the PCIe card, and the second signal indicates that the switching circuit determines the type of the PCIe card. And the switching circuit selects a target path according to the type of the PCIe card, so that the memory corresponding to the target path configures the bus mode of the PCIe to be the bandwidth allocation mode corresponding to the type of the PCIe card. Therefore, under the condition that the hardware structure of the board card does not need to be changed, a set of system of the electronic equipment can adapt to different types of PCIe cards and distribute corresponding bandwidths for the PCIe cards.

Description

Technical Field

[0001] The present application relates to the technical field of electronic equipment, and in particular to a PCIe bandwidth allocation device and electronic equipment. Background Art

[0002] Big data, artificial intelligence, cloud computing, etc. all require electronic devices to support high-speed data interaction. Among them, the high-speed serial computer expansion bus standard PCI-Express (peripheral component interconnect express, PCIe) supports high-speed serial point-to-point dual-channel high-bandwidth transmission. The connected PCIe devices are allocated exclusive channel bandwidth and do not share bus bandwidth. Therefore, the application of PCIe is becoming more and more extensive. PCIe cards rely on their high-speed transmission speed to become the mainstream solution for electronic device buses. Among them, electronic devices can be hosts, servers, or network switches, etc., and PCIe devices connected to electronic devices can be PCIe cards. PCIe cards have different specifications and functions.

[0003] PCIe cards have various specifications, which can be divided into x16, x8, x4 and other standard cards according to bandwidth. In order to use x16 bandwidth more efficiently, for example, a x16 slot is used to allocate two x8 PCIe cards at the same time. If a system of an electronic device is adapted to these two different specifications of PCIe cards at the same time, the CPU needs to automatically identify and allocate PCIe resources.

[0004] In the related art, when the CPU allocates PCIe bandwidth, it is necessary to modify the board structure on the board end to match different PCIe cards. Summary of the invention

[0005] In an exemplary embodiment of the present application, a PCIe bandwidth allocation device and an electronic device are provided to enable a system of the electronic device to adapt to different types of PCIe cards without changing the hardware structure of the board of the electronic device, thereby allocating bandwidth to different types of PCIe cards.

[0006] According to a first aspect of an exemplary embodiment, a PCIe bandwidth allocation device is provided, comprising a switching circuit and a card type determination module; the card type determination module is connected to a PCIe slot and the switching circuit; the switching circuit is connected to N memories; a PCIe card is inserted into the PCIe slot;

[0007] The card type determination module is used to: generate a second signal according to the received first signal, and send the second signal to the switching circuit; wherein the first signal is generated after the PCIe card is inserted into the PCIe slot, the first signal instructs the card type determination module to determine the type of the PCIe card, and the second signal instructs the switching circuit to determine the type of the PCIe card;

[0008] The switching circuit is used to select a target path from N paths according to the type of the PCIe card, so that the target memory corresponding to the target path configures the PCIe bus mode to the bandwidth allocation mode corresponding to the type of the PCIe card; wherein the target path is the path between the switching circuit and the target memory.

[0009] In the embodiment of the present application, by introducing a switching circuit, the card type judgment module and the PCIe slot are respectively connected to the switching circuit, and the switching circuit is connected to N memories. In this way, after the card type judgment module receives the first signal, the type of the PCIe card can be determined, and a second signal is generated according to the received first signal, and the second signal is sent to the switching circuit. The switching circuit can determine the type of the PCIe card according to the second signal, and select the target path from the N paths according to the type of the PCIe card. Since the target path is the path between the switching circuit and the target memory, the target path can configure the bus mode of the PCIe to be the bandwidth allocation mode corresponding to the type of the PCIe card. Therefore, in the embodiment of the present application, without changing the hardware structure of the board card of the electronic device, a set of systems of the electronic device can be adapted to different types of PCIe cards, and bandwidth is allocated to different types of PCIe cards.

[0010] In an optional implementation, the switching circuit includes N switching chips, and each switching chip and the corresponding memory form a path.

[0011] In the above embodiment, the path formed by each switching chip and the corresponding memory can enable the PCIe bandwidth allocation device to adapt to different types of PCIe cards through different paths.

[0012] In an optional embodiment, the type of the PCIe card is a first type or a second type; the first type and the second type are different; the switching circuit includes a first switching chip and a second switching chip; the first switching chip and the second switching chip are connected; the first pin of the first switching chip and the first pin of the second switching chip are respectively connected to the first memory to form a first path; the second pin of the first switching chip and the second pin of the second switching chip are respectively connected to the second memory to form a second path; the first switching chip is used to: when the type of the PCIe card is the first type, the first path is turned on so that the first memory configures the PCIe bus mode to the first bandwidth allocation mode corresponding to the first type; the second switching chip is used to: when the type of the PCIe card is the second type, the second path is turned on so that the second memory configures the PCIe bus mode to the second bandwidth allocation mode corresponding to the second type.

[0013] In the above embodiment, the switching circuit is designed to be composed of a first switching chip and a second switching chip. The first switching chip and the second switching chip are respectively connected to the first memory and the second memory through different pins to respectively form a first path and a second path. In this way, the first switching chip and the second switching chip can select different paths to be turned on when the types of PCIe cards are different, and the memory under the corresponding path configures the bus mode of PCIe to the bandwidth allocation mode corresponding to the type of PCIe card. The structure of the switching circuit is simple, and the process implemented by it is also simple, without changing the hardware structure of the board.

[0014] In an optional embodiment, the first switching chip and the second switching chip are respectively connected to the card type judgment module through the switch control module; the switch control module is used for: when the second signal is at a low level, the third pin of the first switching chip is at a high level, and the third pin of the second switching chip is at a high level, so as to control the first path to be turned on; when the second signal is at a high level, the third pin of the first switching chip is at a low level, and the third pin of the second switching chip is at a low level, so as to control the second path to be turned on.

[0015] In the above embodiment, a switch control module is connected between the switching circuit and the card type determination module, and the switch control module can control the first path and the second path to be connected according to the level of the second signal output from the card type determination module to the switching circuit. In this process, the switching between the two paths is simple and accurate.

[0016] In an optional embodiment, the switch control module includes a MOS tube; the first end of the switch tube is grounded; the second end of the switch tube is respectively connected to the third pin of the first switching chip and the third pin of the second switching chip; and the control end of the switch tube is connected to the card type switching module.

[0017] In the above embodiment, the switch control module can be a switch tube, which can not only realize the card type judgment module to convert the output voltage into the voltage required by the first switching chip and the second switching chip, but also realize the control of switching between the first path and the second path through the switch control function.

[0018] In an optional embodiment, the allocation device also includes a link extender; the link extender is connected to the first memory through a first path and to the second memory through a second path; the link extender is used to: read the PCIe bus mode configured by the first memory or the second memory, so that the PCIe bus allocates bandwidth in a corresponding mode.

[0019] In the above embodiment, a link extender is introduced to read the bus mode of the PCIe configured by the memory, so that the requirement of a long link can be met.

[0020] In an optional embodiment, the allocation device also includes a central processing unit; the central processing unit is connected to the card type judgment module and the link extender respectively; the central processing unit is used to: generate a fourth signal based on the third signal from the card type judgment module, and send the fourth signal to the link extender; wherein the third signal instructs the central processing unit to determine the type of the PCIe card, and the fourth signal instructs the link extender to determine the type of the PCIe card.

[0021] In the above embodiment, the central processor is linked between the card type determination module and the link extender, so that not only can the type of the PCIe card be determined by the third signal from the card type determination module, but also a fourth signal can be generated according to the third signal, so that the link extender can also determine the type of the PCIe card after receiving the fourth signal. In the whole process, both the central processor and the link extender can determine the type of the PCIe card.

[0022] In an optional implementation, the first type is x16 type, and the second type is x8x8 type; the first type is x8x8 type, and the second type is x16 type.

[0023] In the above embodiment, the different types of PCIe cards that are adapted are x16 type or x8x8 type. The x8x8 type here can be two x8 PCIe cards with the same function or different functions. Flexible bandwidth configuration for PCIe cards with different functions is achieved.

[0024] In an optional implementation, the first type is the x16 type, and the first bandwidth allocation mode is the x16 bandwidth allocation mode; or, the first type is the x8x8 type, and the first bandwidth allocation mode is the x8x8 bandwidth allocation mode; or, the second type is the x16 type, and the second bandwidth allocation mode is the x16 bandwidth allocation mode; or, the second type is the x8x8 type, and the second bandwidth allocation mode is the x8x8 bandwidth allocation mode.

[0025] In the above embodiment, corresponding bandwidth allocation modes are configured for different types of PCIe cards, so that the corresponding PCIe cards can use their extended functions in the bandwidth allocation modes adapted to them.

[0026] In an optional implementation, the card type determination module is a programmable logic device or a processor.

[0027] In the above embodiment, the card type determination module is not limited to one option, and a CPLD or a processor can be selected, so that the design of the bandwidth allocation device is more flexible.

[0028] According to a second aspect of an exemplary implementation, an electronic device is provided, comprising a PCIe slot, a circuit board, and the PCIe bandwidth allocation device according to the first aspect; the PCIe bandwidth allocation device is disposed on the circuit board.

[0029] In the embodiment of the present application, a PCIe bandwidth allocation device is disposed on a circuit board, and constitutes an electronic device together with a PCIe slot. The arrangement is simple and convenient, and no other solidified hardware-level improvements are required. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0031] Figure 1 A schematic diagram showing an original structure of a board in the related art is exemplified;

[0032] Figure 2 A schematic diagram showing an improvement to the hardware structure of a board in the related art is exemplified;

[0033] Figure 3 A schematic diagram showing another improvement to the hardware structure of a board in the related art is exemplified;

[0034] Figure 4a The following is a schematic diagram showing the structure of a PCIe bandwidth allocation device provided in an embodiment of the present application;

[0035] Figure 4b The following is a schematic diagram showing the structure of another PCIe bandwidth allocation device provided in an embodiment of the present application;

[0036] Figure 5 The structure diagram of a switching circuit provided by an embodiment of the present application is exemplarily shown;

[0037] Figure 6 A schematic diagram of the structure of another PCIe bandwidth allocation device provided in an embodiment of the present application is exemplified. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.

[0039] For ease of understanding, the terms involved in the embodiments of the present application are explained below:

[0040] (1) PCIe card is an expansion card with a PCIe interface. The PCIe interface is used as an expansion port in motherboard-level connections. Specifically, a PCIe-based expansion card can be inserted into a PCIe slot in the motherboard of electronic devices such as a host, server, and network switch. In the embodiments of the present application, the specifications of a PCIe card may also be referred to as the type of PCIe card; PCIe cards may be divided into graphics processing units (GPUs) or graphics cards, etc., according to their functions.

[0041] (2) Complex Programmable Logic Device (CPLD) is composed of three parts: logic block, programmable interconnect channel and I / O block. It is a high-density, high-speed and low-power programmable logic device.

[0042] (3) The Central Processing Unit (CPU) is the computing and control core of the computer system and the final execution unit for information processing and program execution.

[0043] (4) Read-Only Memory (ROM) works in a non-destructive read mode and can only read information but not write it. It stores programs that do not need to be changed, such as microprograms, fixed subroutines, and letter symbols. In the embodiment of the present application, both the first memory and the second memory can be read-only memories.

[0044] (5) A Metal Oxide Semiconductor Field Effect Transistor (MOS) includes a source, a gate and a drain.

[0045] (6) General-Purpose Input / Output (GPIO), whose pins can be freely used by the user through program control. Among them, the PIN pin can be used as a general-purpose input GPI, a general-purpose output GPO, or a general-purpose input and output GPIO according to practical considerations.

[0046] (7) Bill of Materials (BOM) is a technical document that describes the composition of a product. It describes the physical composition of the materials and is generally divided and described in layers according to their functions. In the capital processing industry, it shows the structural relationship between the final assembly, subassembly, components, parts, and even raw materials of the product, as well as the required quantity. In the embodiment of the present application, the BOM of the board refers to the hardware that constitutes the board.

[0047] (8) Non-Volatile Memory Express (NVMe) is a logical device interface specification. In the embodiments of the present application, the NVMe backplane refers to a backplane that complies with the interface specification.

[0048] Take the server as an example. In the related art, if a server can match PCIe cards of different specifications at the same time, it is necessary to modify the BOM of the board on the server card to match different PCIe cards. Next, combined with Table 1, a specific example is used to illustrate the method of modifying the board structure in the prior art. The device in Table 1 refers to the PCIe device, that is, the PCIe card.

[0049] Table 1 is a schematic diagram of a CPU PCIe allocation rule in the related art.

[0050]

[0051]

[0052] As shown in Table 1, a riser slot may refer to a PCIE adapter card or a PCIE expansion card, for example, a card that converts a PCIe interface in the form of a cable connector into a slot function. Lane reversal may refer to a PCIe channel flip, for example, lanes 0 to 15 on the CPU side are connected to lanes 15 to 0 on the PCIe card side.

[0053] In the related art, the CPU allocates PCI bandwidth according to the levels of four GPIO pins. Lane represents a channel, and the signals of each of the four channels are output through a GPIO pin of the CPU. Optionally, the signal indicated by ID[3:0] is a BIFURCATION signal, which can be represented by BIF ID0, BIF ID1, BIF ID2, and BIFID3.

[0054] From Table 1, we can see that when the PCIe card type is x16, BIF ID[3:0]=0110b; when the device is x8x8, BIF ID[3:0]=1010b; at this time, the levels of BIF ID2 and BIF ID3 are different. Therefore, if the CPU wants to adapt to these two specifications of PCIe cards, it is necessary to make different hardware allocations for BIF ID3 and BIF ID2, and then distinguish the BOM of the board. In order to distinguish different bandwidths, it is necessary to distinguish R104, R105, R106, and R107. Figure 1 The figure is a schematic diagram of the original structure of a board in the related art.

[0055] For example, Figure 2The following is a schematic diagram of an improvement to the hardware structure of a board in the related art. Figure 2 It can be seen that by removing R104 and R107 in the original structure of the board, BIF ID[3:0]=0110b, the improved structure can be applied to achieve the distinction of the BOM of the board, and then adapt to the x16 type PCIe card.

[0056] For example, Figure 3 The following is a schematic diagram of an improvement to the hardware structure of a board in the related art. Figure 3 It can be seen that by removing R105 and R106 in the original structure of the board, BIF ID[3:0]=1010b, the improved structure can be applied to achieve the distinction of the BOM of the board, and then adapt to the x8x8 type PCIe card.

[0057] To this end, an embodiment of the present application provides a PCIe bandwidth allocation device, which includes a switching circuit (connected to N memories) and a card type judgment module. After the PCIe card is inserted into the PCIe slot, a first signal is generated, and the card type judgment module can judge the type of the PCIe card according to the first signal, and generate a second signal according to the first signal, and send the second signal to the switching circuit. The switching circuit can determine the type of the PCIe card according to the second signal. The switching circuit can select a target path between the switching circuit and the target memory (one of the N memories) according to the type of the PCIe card, so that the target memory can configure the PCIe bus mode to the bandwidth allocation mode corresponding to the type of the PCIe card. Therefore, without changing the hardware structure of the board, the electronic device can be adapted to different PCIe cards, and then the corresponding bandwidth is allocated to provide the corresponding PCIe card with resources of the corresponding bandwidth.

[0058] To further illustrate the technical solution provided by the embodiment of the present application, this is described in detail below in conjunction with the accompanying drawings and specific implementation methods. Although the embodiment of the present application provides the method operation steps shown in the following embodiments or drawings, more or fewer operation steps may be included in the method based on routine or no creative labor. In the steps where there is no necessary causal relationship logically, the execution order of these steps is not limited to the execution order provided in the embodiment of the present application.

[0059] In actual application, N memories and their corresponding N switching chips constitute N paths, and in the embodiment of the present application, N is 2 for illustration. For example, if N is 2, the N memories are a first memory and a second memory, the first memory and the first switching chip constitute a first path, and the second memory and the second switching chip constitute a second path.

[0060] refer to Figure 4aA structural schematic diagram of a PCIe bandwidth allocation device is shown, wherein n is an integer greater than 4, n-3=N, and the target memory is one of N memories. Figure 4b This is a schematic diagram of the structure of another PCIe bandwidth allocation device provided in an embodiment of the present application, wherein N=2 is used to illustrate the technical solution provided in the embodiment of the present application.

[0061] The PCIe bandwidth allocation device includes a switching circuit 11 and a card type determination module 12, wherein the card type determination module 12 is connected to the PCIe slot 13 and the switching circuit 11, and the switching circuit 11 is connected to the first memory 14 and the second memory 15. The card type determination module 12 can be in different forms such as CPLD or processor, as long as it can realize the corresponding function. This is just an example and does not form a specific limitation. Taking CPLD as an example, the four output pins (PRSNT_N1, PRSNT_N2, PRSNT_N3 and PRSNT_N4) of the PCIe slot are respectively connected to the four GPIO pins of the CPLD.

[0062] In the actual application process, after the PCIe card is inserted into the PCIe slot, a first signal is generated, and the PCIe slot sends the first signal to the card type judgment module 12 through the path between the PCIe slot and the card type judgment module 12. The card type judgment module 12 can determine the type of the PCIe card through the first signal, and generate a second signal according to the first signal, and send the second signal to the switching circuit 11. The switching circuit 11 determines the type of the PCIe card according to the second signal. The switching circuit 11 then selects the first path between the switching circuit 11 and the first memory or the second path between the switching circuit 11 and the memory according to the type of the PCIe card. In this way, if the first path is selected, the bus mode of the PCIe configured by the first memory is the bandwidth allocation model corresponding to the type of the PCIe card; if the second path is selected, the bus mode of the PCIe configured by the second memory is the bandwidth allocation model corresponding to the type of the PCIe card.

[0063] Exemplarily, the type of the PCIe card may be a first type or a second type, and the first type and the second type are different. The different types of PCIe cards that are adapted are x16 type or x8x8 type. The x8x8 type here may be two x8 PCIe cards with the same function or different functions. Flexible bandwidth configuration for PCIe cards with different functions is achieved. Both x16 type PCIe cards or x8x8 type PCIe cards can use x16 gold fingers and PCIe slots.

[0064] In a possible implementation, the first type is an x16 type, and the second type is an x8x8 type. The first bandwidth allocation mode corresponding to the first type is an x16 bandwidth allocation mode, and the second bandwidth allocation mode corresponding to the second type is an x8x8 bandwidth allocation mode.

[0065] In another possible implementation, the first type is an x8x8 type, and the second type is an x16 type. The first bandwidth allocation mode corresponding to the first type is an x8x8 bandwidth allocation mode, and the second bandwidth allocation mode corresponding to the second type is an x16 bandwidth allocation mode.

[0066] Therefore, in the embodiment of the present application, corresponding bandwidth allocation modes are configured for different types of PCIe cards, so that the corresponding PCIe cards can use their extended functions in the bandwidth allocation mode adapted to them.

[0067] In the above embodiment, the card type determination module 12 receives the first signal generated after the PCIe card is inserted into the PCIe slot. Optionally, the first signal can be represented by the 0th and 1st bits of the in-position signal PRSNT, so the card type determination module 12 can determine the type of the PCIe card according to the levels of PRSNT0 and PRSNT1. In a specific example, the judgment rule of the card type determination module 12 can be that if the levels of PRSNT0 and PRSNT1 are 00, the card type determination module 12 can judge the PCIe card position x16 type card accordingly; if the levels of PRSNT0 and PRSNT1 are 01, the card type determination module 12 can judge the PCIe card as an x8x8 type card accordingly.

[0068] In addition, after receiving the first signal, the card type determination module 12 generates a second signal and sends the second signal to the switching circuit 11. Optionally, the second signal may be the third bit of the BIFURCATION signal, that is, BIF ID3. In a specific example, if the level of BIF ID3 is 0, the switching circuit 11 may determine that the type of the PCIe card is x16; if the level of BIFID3 is 1, the switching circuit 11 may determine that the type of the PCIe card is x8x8.

[0069] Next, the structure of the switching circuit 11 will be described. Figure 5 A schematic diagram of a switching circuit provided in an embodiment of the present application, wherein the first memory 14 is illustrated by U3, the second memory 15 is illustrated by U8, the first switching chip is illustrated by U10, and the second switching chip is illustrated by U11.

[0070] See also Figure 5The switching circuit 11 includes a first switching chip U10 and a second switching chip U11, and the first switching chip U10 is connected to the second switching chip U11. The first pin B1 of the first switching chip U10 and the first pin B1 of the second switching chip U11 are respectively connected to the first memory U3 to form a first path; the second pin B0 of the first switching chip U10 and the second pin B0 of the second switching chip U11 are respectively connected to the second memory U8 to form a second path.

[0071] In a specific example, the first pin B1 of the first switching chip U10 is connected to the SCL pin of the first memory U3, and the first pin B1 of the second switching chip U11 is connected to the SDA pin of the first memory U3. The second pin B0 of the first switching chip U10 is connected to the SCL pin of the second memory U8, and the second pin B0 of the second switching chip U11 is connected to the SDA pin of the second memory U8. Among them, the selection of the first switching chip U10 and the second switching chip U11, and the connection methods with the first memory U3 and the second memory U8 are all examples and do not constitute specific limitations.

[0072] In the embodiment of the present application, when the type of the PCIe card is the first type, the first switching chip U10 controls the first path to be turned on, so that the bus mode of the PCIe configured by the first memory U3 is the first bandwidth allocation mode corresponding to the first type. When the type of the PCIe card is the second type, the second switching chip U11 controls the second path to be turned on, so that the bus mode of the PCIe configured by the second memory U8 is the second bandwidth allocation mode corresponding to the second type.

[0073] Optionally, the first switching chip U10 and the second switching chip U11 are respectively connected to the card type determination module 12 through a switch control module. When the second signal is at a low level, the third pin S of the first switching chip U10 is at a high level, the third pin S of the second switching chip U11 is at a high level, and the switch control module controls the first path to be turned on; when the second signal is at a high level, the third pin S of the first switching chip U10 is at a low level, the third pin S of the second switching chip is at a low level, and the second path is controlled to be turned on.

[0074] That is, when the level of BIF ID3 is 0, the first memory is turned on and the bus mode of PCIe configured by the first memory is x16 mode. When the level of BIF ID3 is 1, the second memory is turned on and the bus mode of PCIe configured by the second memory is x8x8 mode.

[0075] Optionally, the switch control module includes a switch tube; the first end of the switch tube is grounded; the second end of the switch tube is respectively connected to the third pin of the first switching chip and the third pin of the second switching chip; and the control end of the switch tube is connected to the card type switching module 12.

[0076] For example, if the switch tube is a MOS tube, the control end is the gate G, the first end is the source S, and the second end is the drain D; if the switch tube is a triode, the control end is the base, the first end is the emitter, and the second end is the collector.

[0077] Among them, the switch tube can not only realize the card type judgment module to convert the output voltage into the voltage required by the first switching chip U10 and the second switching chip U11 (convert the 3.3V voltage of BIF ID3 output by the CPLD into the 1.8V required by the first switching chip U10 and the second switching chip U11), but also realize the control of switching between the first channel and the second channel through the switch control function.

[0078] In order to meet the requirement of long links, a link extender Retimer may also be provided in the bandwidth allocation device. Figure 6 A schematic diagram of the structure of another PCIe bandwidth allocation device provided in an embodiment of the present application. Figure 6 The link extender 16 is connected to the first memory U10 through the first path and to the second memory U11 through the second path. The link extender 16 can read the PCIe bus mode configured by the first memory U3 or the second memory U8 to allocate bandwidth to the PCIe bus in the corresponding mode.

[0079] The addition of the link extender 16 can meet the requirement of a long link, and the link extender 16 can also load different firewall configurations according to different types of PICe cards.

[0080] Still see Figure 5 , CPLD outputs BIF ID3 to transistor Q8, and the drain D pin of transistor Q8 is connected to the third pin (PIN6) of the first switching chip U10 and the third pin (PIN6) of the second switching chip. 2 C3 is connected to the first switching chip U10 and the second switching chip U11 respectively. If the PIN6 pins of the first switching chip U10 and the second switching chip U11 are both high level, the pin A (PIN4) of the first switching chip U10 is output to the first pin B1, otherwise it is output to the second pin B0. The first switching chip U10 and the second switching chip U11 are connected to the first memory U3 and the second memory U8 respectively. 2 C's SDA signal is switched, and the second switching chip U11 switches I 2 C's SCL is switched to realize the function of the link extender 16Retimer communicating with the first memory U3 or the second memory U8 according to the different levels of BIF ID3.

[0081] Optionally, the allocation device further includes a central processor 17. The central processor 17 is connected to the card type determination module 12 and the link extender 16 respectively. The central processor 17 receives the third signal from the card type determination module 12, determines the type of the PCIe card according to the third signal, generates a fourth signal according to the third signal, and sends the fourth signal to the link extender 16. The link extender 16 determines the type of the PCIe card according to the fourth signal.

[0082] The third signal can be represented by the second and third bits of the BIFURCATION signal. For the convenience of description, it is represented by BIF ID2 and BIF ID3. In a specific example, if the levels of BIF ID2 and BIF ID3 are 10, the switching circuit 11 can determine that the type of the PCIe card is x16; if the levels of BIF ID2 and BIF ID3 are 01, the switching circuit 11 can determine that the type of the PCIe card is x8x8.

[0083] Therefore, the embodiment of the present application can realize the same PCIe bandwidth from the PCIe card to the link extender 16, and from the link extender 16 to the CPU 17. For example, if the PCIe bus from the PCIe card to the link extender 16 has a bandwidth of x8x8, then the bandwidth from the CPU 17 to the link extender 16 is also x8x8; if the PCIe bus from the PCIe card to the link extender 16 has a bandwidth of x16, then the bandwidth from the CPU 17 to the link extender 16 is also x16.

[0084] In the embodiment of the present application, by introducing the switching circuit 11, the card type judgment module 12 and the PCIe slot are respectively connected to the switching circuit 11, and the switching circuit 11 is connected to the first memory and the second memory. In this way, after the card type judgment module 12 receives the first signal, the type of the PCIe card can be determined, and the second signal is generated according to the received first signal, and the second signal is sent to the switching circuit 11. The switching circuit 11 can determine the type of the PCIe card according to the second signal, and select the first path or the second path according to the type of the PCIe card. Since the first path is the path between the switching circuit 11 and the first memory, and the second path is the path between the switching circuit 11 and the second memory, the first memory or the second memory can configure the bus mode of PCIe to the bandwidth allocation mode corresponding to the type of PCIe card. Therefore, in the embodiment of the present application, without changing the hardware structure of the board card of the electronic device, a set of systems of the electronic device can adapt to different types of PCIe cards, and then allocate bandwidth for different types of PCIe cards.

[0085] The embodiment of the present application also provides an electronic device, the electronic device comprising a PCIe slot, a circuit board and the PCIe bandwidth allocation device of the above embodiment. The PCIe bandwidth allocation device is arranged on the circuit board. The PCIe slot cooperates with the PCIe bandwidth allocation device to complete the above bandwidth allocation process, and the details can be referred to the above embodiment, which will not be repeated here.

[0086] In the embodiment of the present application, the x16 slot can be compatible with both standard PCIe cards such as x16 and non-standard PCIe cards such as x8x8 without changing the hardware structure of the board. The type of PCIe card is automatically identified, and the configuration of the link extender 16 can be flexibly selected according to the type of PCIe card and the automatic bandwidth allocation of the CPU 17 can be realized.

[0087] In actual application, the x16 gold finger and PCIe slot can adapt to x16 type PCIe card, x8x8 type PCIe card, x4x4x4x4 type, x8x4x4 type PCIe card, etc. In addition, it can also be x32 gold finger, etc. The above embodiment is only an example and does not form a specific limitation.

[0088] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0089] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0090] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0091] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0092] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A PCIe bandwidth allocation device, characterized in that: It includes a switching circuit and a card type judgment module; the card type judgment module is connected to the PCIe slot and the switching circuit; the switching circuit is connected to N memories; N is an integer greater than 1; The card type determination module is used to: generate a second signal according to the received first signal, and send the second signal to the switching circuit; wherein the first signal is generated after the PCIe card is inserted into the PCIe slot, the first signal instructs the card type determination module to determine the type of the PCIe card, and the second signal instructs the switching circuit to determine the type of the PCIe card; The switching circuit is used to: select a target path from N paths according to the type of the PCIe card, so that the target memory corresponding to the target path configures the PCIe bus mode to the bandwidth allocation mode corresponding to the type of the PCIe card; wherein the target path is the path between the switching circuit and the target memory.

2. The PCIe bandwidth allocation device according to claim 1, characterized in that: The switching circuit includes N switching chips, and each switching chip and the corresponding memory form a path.

3. The PCIe bandwidth allocation device according to claim 1 or 2, characterized in that: The type of the PCIe card is a first type or a second type; the first type and the second type are different; The switching circuit includes a first switching chip and a second switching chip; the first switching chip and the second switching chip are connected; The first pin of the first switching chip and the first pin of the second switching chip are respectively connected to the first memory to form a first path; The second pin of the first switching chip and the second pin of the second switching chip are respectively connected to the second memory to form a second path; The first switching chip is used to: when the type of the PCIe card is the first type, the first path is turned on, so that the first memory configures the bus mode of the PCIe to be the first bandwidth allocation mode corresponding to the first type; The second switching chip is used for: when the type of the PCIe card is the second type, the second path is turned on, so that the second memory configures the bus mode of the PCIe to the second bandwidth allocation mode corresponding to the second type.

4. The PCIe bandwidth allocation device according to claim 3, characterized in that: The first switching chip and the second switching chip are respectively connected to the card type determination module through a switch control module; The switch control module is used for: when the second signal is at a low level, the third pin of the first switch chip is at a high level, and the third pin of the second switch chip is at a high level, so as to control the first path to be turned on; When the second signal is at a high level, the third pin of the first switching chip is at a low level, and the third pin of the second switching chip is at a low level, so that the second path is controlled to be turned on.

5. The PCIe bandwidth allocation device according to claim 4, characterized in that: The switch control module includes a switch tube; The first end of the switch tube is grounded; The second end of the switch tube is connected to the third pin of the first switching chip and the third pin of the second switching chip respectively; The control end of the switch tube is connected to the card type switching module.

6. The PCIe bandwidth allocation device according to any one of claims 1-2 and 4-5, characterized in that: The distribution device also includes a link extender; The link extender is connected to the first memory through the first path and connected to the second memory through the second path respectively; The link extender is used to read the PCIe bus mode configured by the first memory or the second memory, so that the PCIe bus allocates bandwidth in a corresponding mode.

7. The PCIe bandwidth allocation device according to claim 6, characterized in that: The dispensing device also includes a central processing unit; The central processing unit is connected to the card type determination module and the link extender respectively; The central processor is used to: generate a fourth signal according to the third signal from the card type judgment module, and send the fourth signal to the link extender; wherein the third signal instructs the central processor to determine the type of the PCIe card, and the fourth signal instructs the link extender to determine the type of the PCIe card.

8. The PCIe bandwidth allocation device according to any one of claims 1-2 and 4-5, characterized in that: The first type is x16 type, and the second type is x8x8 type; the first type is x8x8 type, and the second type is x16 type.

9. The PCIe bandwidth allocation device according to claim 8, characterized in that: The first type is an x16 type, and the first bandwidth allocation mode is an x16 bandwidth allocation mode; or The first type is an x8x8 type, and the first bandwidth allocation mode is an x8x8 bandwidth allocation mode; or The second type is an x16 type, and the second bandwidth allocation mode is an x16 bandwidth allocation mode; or The second type is an x8x8 type, and the second bandwidth allocation mode is an x8x8 bandwidth allocation mode.

10. The PCIe bandwidth allocation device according to any one of claims 1-2 and 4-5, characterized in that: The card type determination module is a programmable logic device or a processor.

11. An electronic device, characterized in that: It comprises a PCIe slot, a circuit board and a PCIe bandwidth allocation device as claimed in any one of claims 1 to 10; the PCIe bandwidth allocation device is arranged on the circuit board.

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