Preparation method of semiconductor structure and semiconductor structure

Abstract

The invention relates to a preparation method of a semiconductor structure and the semiconductor structure, and the method comprises the steps: providing an initial plastic package structure which comprises a first carrier plate, a first bonding layer, a first line layer, a first chip and a plastic package layer which are sequentially stacked in a first direction; a part of the first connecting piece of the first circuit layer is electrically connected with the second connecting piece of the first chip; the first chip comprises a second connecting piece and a semiconductor layer wrapping the second connecting piece; removing a part of the plastic packaging layer and a part of the semiconductor layer along the first direction until the second connecting piece is exposed; after a second circuit layer is formed on the plastic packaging layer, a second carrier plate is formed on the second circuit layer, and the second circuit layer is electrically connected with the second connecting piece; the first carrier plate and the first bonding layer are removed, the first circuit layer is exposed, and the first circuit layer is used for being electrically connected with at least one second chip, so that the bearing pressure of a single circuit is reduced, and the yield of semiconductor packaging products is improved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a method for preparing a semiconductor structure and a semiconductor structure. Background Art

[0002] Fan-out packaging technology is a packaging method commonly used in integrated circuit design. It connects multiple transistors or other electronic components together to form a small circuit module and encapsulates it in a package, thereby achieving functional integration and greatly reducing the volume of the package.

[0003] However, as the integration of the package increases, the bearing pressure of a single circuit in the package increases significantly. Therefore, how to reduce the bearing pressure of a single circuit in the package becomes one of the technical problems that need to be solved urgently. Summary of the invention

[0004] Based on this, it is necessary to provide a method for preparing a semiconductor structure and a semiconductor structure to address the problem of high single-line bearing pressure in fan-out package integration in the prior art, which can at least improve the yield and reliability of the semiconductor structure.

[0005] In order to achieve the above objectives, on the one hand, the present application provides a method for preparing a semiconductor structure, comprising:

[0006] An initial plastic encapsulation structure is provided, the initial plastic encapsulation structure comprising a first carrier, a first bonding layer, a first circuit layer, a first chip and a plastic encapsulation layer stacked in sequence along a first direction; wherein the first direction is a direction perpendicular to a top surface of the first carrier; a portion of first connectors of the first circuit layer are electrically connected to second connectors of the first chip; the first chip comprises the second connector and a semiconductor layer wrapping the second connector;

[0007] removing a portion of the plastic encapsulation layer and a portion of the semiconductor layer along the first direction until the second connecting member is exposed;

[0008] After forming a second circuit layer on the plastic packaging layer, forming a second carrier on the second circuit layer, the second circuit layer is electrically connected to the second connecting member;

[0009] The first carrier board and the first bonding layer are removed to expose the first circuit layer, where the first circuit layer is used to be electrically connected to at least one second chip.

[0010] In one embodiment, removing part of the plastic encapsulation layer and part of the semiconductor layer along the first direction until the second connector is exposed includes:

[0011] Using a grinding process to remove the plastic encapsulation layer and the semiconductor layer along the first direction until the second connector of the first chip is exposed;

[0012] A portion of the semiconductor layer is removed along the first direction so that the second connector partially protrudes from the remaining semiconductor layer, thereby removing the circuit material remaining on the semiconductor layer; wherein the circuit material is the same as the material of the second connector.

[0013] In one embodiment, the preparation method further includes forming a plurality of metal pillars on the first circuit layer, wherein the metal pillars are connected to the remaining first connectors of the first circuit layer; and removing a portion of the plastic encapsulation layer and a portion of the semiconductor layer along the first direction until the second connectors are exposed, comprising:

[0014] removing part of the plastic encapsulation layer and part of the semiconductor layer along the first direction, and making the remaining plastic encapsulation layer cover the metal column when the remaining semiconductor layer exposes the second connector at a first target height;

[0015] forming a dielectric layer at least on the remaining semiconductor layer and the second connecting member exposed to a first target height;

[0016] Part of the dielectric layer and the remaining plastic encapsulation layer are removed along the first direction until the second connector and the metal column are exposed; and the surface of the remaining dielectric layer is flush with the surface of the remaining plastic encapsulation layer.

[0017] In one embodiment, removing part of the plastic encapsulation layer and part of the semiconductor layer along the first direction, and making the remaining plastic encapsulation layer cover the metal column when the remaining semiconductor layer exposes the second connector at the first target height, comprises:

[0018] Using a grinding process to remove part of the plastic encapsulation layer and part of the semiconductor layer along the first direction, so that the remaining semiconductor layer and the remaining plastic encapsulation layer cover the second connecting member and the metal column respectively;

[0019] A portion of the semiconductor layer is removed along the first direction to expose the second connecting member at the first target height.

[0020] In one embodiment, the first target height is 10 micrometers to 15 micrometers.

[0021] In one embodiment, providing an initial plastic packaging structure includes:

[0022] Providing a substrate, wherein the substrate comprises a first carrier and the first bonding layer located on the first carrier;

[0023] forming a first circuit layer on the first bonding layer; wherein the first circuit layer includes a plurality of the first connecting members;

[0024] forming a first chip on the first circuit layer, wherein the second connecting member of the first chip is electrically connected to a part of the first connecting member;

[0025] The plastic packaging layer is formed on the first circuit layer and the first chip.

[0026] In one embodiment, forming the second circuit layer includes:

[0027] A plurality of third connecting members are formed on the plastic encapsulation layer; wherein the third connecting members are at least electrically connected to the second connecting members;

[0028] forming a solder pad at an end of the third connecting member facing away from the first carrier board;

[0029] A soldering point is formed on the soldering pad; a side of the soldering point facing away from the first carrier board is used for fixing with the second carrier board.

[0030] In one embodiment, forming the second carrier includes:

[0031] forming a protective layer on the solder joint;

[0032] The side of the protective layer facing away from the first carrier board is fixed to the second carrier board.

[0033] In the second aspect, the present application also provides a semiconductor structure, including: a second carrier, a plastic encapsulation layer, a first chip, a first circuit layer and a second circuit layer; the plastic encapsulation layer is located on the second carrier, and the plastic encapsulation layer includes at least one first chip; wherein the first chip includes a second connector and a semiconductor layer wrapping the second connector; the second connector is electrically connected to the second circuit layer; the first circuit layer is located on the first chip and the plastic encapsulation layer; some of the first connectors of the first circuit layer are electrically connected to the second connector; the first circuit layer is used to be electrically connected to at least one second chip; the second circuit layer is located on the plastic encapsulation layer, and the second circuit layer is electrically connected to the second connector; the second carrier is located on the second circuit layer.

[0034] In one embodiment, the height of the second connecting member protruding from the semiconductor layer is a first target height; and the semiconductor structure further comprises:

[0035] The dielectric layer is located between the second carrier and the semiconductor layer, surrounding the second connector at the first target height; the surface of the dielectric layer close to the second carrier is flush with the surface of the plastic layer close to the second carrier.

[0036] The semiconductor structure preparation method and semiconductor structure of the present application have the following beneficial effects:

[0037] The preparation method of the semiconductor structure and the semiconductor structure of the present application include: providing an initial plastic encapsulation structure, the initial plastic encapsulation structure includes a first carrier, a first bonding layer, a first circuit layer, a first chip and a plastic encapsulation layer stacked in sequence along a first direction; wherein the first direction is a direction perpendicular to the top surface of the first carrier; part of the first connector of the first circuit layer is electrically connected to the second connector of the first chip; the first chip includes a second connector and a semiconductor layer wrapping the second connector; removing part of the plastic encapsulation layer and part of the semiconductor layer along the first direction until the second connector is exposed; wherein the second connector protrudes from the remaining semiconductor layer; forming a second carrier on the plastic encapsulation layer, the second carrier being electrically connected to the second connector; removing the first carrier and the first bonding layer to expose the first circuit layer, the first circuit layer being used to be electrically connected to at least one second chip. The present application provides an initial plastic encapsulation structure, which includes a first circuit layer and a first chip, and part of the first connector of the first circuit layer is electrically connected to the second connector of the first chip, the first circuit layer is electrically connected to at least one second chip, and the second connector of the first chip is also electrically connected to the second circuit layer, and the first chip is directly connected to the second circuit layer and the second chip respectively by using the first chip, thereby increasing the number of circuits and reducing the bearing pressure of a single circuit. In addition, in an embodiment of the present application, after removing part of the plastic encapsulation layer and part of the semiconductor layer and exposing the second connector of the first chip, a second circuit layer electrically connected to the second connector is formed on the plastic encapsulation layer, a second carrier is formed on the second circuit layer, and then the first carrier and the first bonding layer are removed by debonding to expose the first circuit layer, and then the second chip is formed on the first circuit layer, that is, the second chip is formed after the step of removing the first carrier and the first bonding layer by debonding. Compared with the step of removing the first carrier and the first bonding layer by debonding after the second chip is formed, the present embodiment avoids the adverse effects of the debonding process on the second chip, and effectively improves the yield and reliability of the semiconductor structure.

[0038] Furthermore, the present application can arrange the second connector to partially protrude from the remaining semiconductor layer to form a groove, so that the dielectric layer covering the top surface of the second connector can be filled in the groove, thereby preventing the circuit material from diffusing into the remaining semiconductor layer during the process of planarizing the top surface of the dielectric layer. Therefore, when the second connector is electrically connected to the second circuit layer, it will not cause electrical connection between devices, circuit materials, etc. in the semiconductor layer, thereby avoiding the formation of a short circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0040] Figure 1 is a flow chart of a method for preparing a semiconductor structure provided in an embodiment;

[0041] Figure 2a-2j is a schematic cross-sectional view of a semiconductor structure provided in an embodiment;

[0042] Figure 3 is a flow chart of step S102 in a method for preparing a semiconductor structure provided in an embodiment;

[0043] Figure 4a-4h is a schematic cross-sectional view of a structure obtained in step S102 in a method for preparing a semiconductor structure provided in an embodiment;

[0044] Figure 5 is a flow chart of step S104 in a method for preparing a semiconductor structure provided in an embodiment;

[0045] Figure 6a-6e is a schematic cross-sectional view of a structure obtained in step S104 in a method for preparing a semiconductor structure provided in an embodiment;

[0046] Figure 7 is a flow chart of step S106 in a method for preparing a semiconductor structure provided in an embodiment;

[0047] Figure 8a-8c is a schematic cross-sectional view of a structure obtained in step S106 in a method for preparing a semiconductor structure provided in an embodiment;

[0048] Fig. 9 is a flow chart of step S104 in a method for preparing a semiconductor structure provided in an embodiment;

[0049] Figure 10a-Figure 10c is a schematic cross-sectional view of a structure obtained in step S108 in a method for preparing a semiconductor structure provided in an embodiment;

[0050] Reference numerals and descriptions:

[0051] 101, first carrier; 102, protective layer; 103, second carrier; 20, first bonding layer; 40, first chip; 401, adhesive layer; 402, semiconductor layer; 403, internal connector; 404, second connector; 301, first dielectric layer; 302, metal pillar; 303, first connector; 501, first plastic layer; 502, second plastic layer; 503, plastic layer; 60, first redistribution layer; 601, second dielectric layer; 602, first metal layer; 603, pad; 701, second chip; 702, glue layer; 80, second redistribution layer; 801, third dielectric layer; 802, second metal layer; 803, solder joint; 804, third connector; 805, fourth dielectric layer; 90, dielectric layer. DETAILED DESCRIPTION

[0052] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0053] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0054] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0055] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0056] When used herein, the singular forms "a", "an" and " / the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of features, integers, steps, operations, elements and / or components can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0057] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic diagrams of ideal embodiments (and intermediate structures) of the present application, so that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the present application.

[0058] In one embodiment, please refer to Figure 1 , the present application provides a method for preparing a semiconductor structure, including: step S102-step S108.

[0059] Step S102: providing an initial plastic encapsulation structure, the initial plastic encapsulation structure comprising a first carrier, a first bonding layer, a first circuit layer, a first chip and a plastic encapsulation layer stacked in sequence along a first direction; wherein the first direction is a direction perpendicular to the top surface of the first carrier; a portion of the first connectors of the first circuit layer are electrically connected to the second connectors of the first chip; the first chip comprises a second connector and a semiconductor layer wrapping the second connector.

[0060] As an example, the material of the first carrier may include one of glass, metal, semiconductor, polymer and ceramic; in other embodiments, the present application does not limit the material and shape of the first carrier, and the first carrier is used to support the subsequently formed film layer.

[0061] As an example, the material of the first bonding layer may include a double-sided adhesive tape or an adhesive layer. The present application does not limit the material of the first bonding layer, as long as it can meet the requirement of bonding the first carrier board and the first circuit layer.

[0062] As an example, the first circuit layer may include a circuit layer, for example, a stack of a dielectric layer and a metal layer, or may include multiple circuit layers, for example, multiple dielectric layers and metal layers. In other embodiments, the present application does not impose any specific restrictions on the number of layers of the first circuit layer, and the first circuit layer is used to connect chips or other circuit layers on both sides of the first circuit layer along the first direction.

[0063] As an example, the first chip may include a bridge chip, a system on chip (SOC), a high bandwidth memory (HBM), etc. In other embodiments, the present application does not specifically limit the type of the first chip, and the first chip is used to implement a certain function.

[0064] As an example, the material of the plastic encapsulation layer may include one or a combination of a polyimide layer (PI), a silicone layer, and an epoxy resin layer. The present application does not impose any specific restrictions on the material of the first plastic encapsulation layer.

[0065] As an example, the material of the first connector and the second connector may include one or more metal materials such as cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), tantalum titanium (TaTi), tungsten nitride (WN), copper (Cu) and aluminum (Al).

[0066] As an example, the material of the semiconductor layer may include one or more of silicon (Si) material, silicon germanium (SiGe) material, silicon germanium carbon (SiGeC) material, silicon carbide (SiC) material, gallium arsenide (GaAs) material, indium arsenide (InAs) material, indium phosphide (InP) material or other III / V semiconductor materials or II / VI semiconductor materials. The second connector is located in the semiconductor layer, and one end of the second connector is exposed to the semiconductor layer, and the surface of the semiconductor layer that exposes one end of the second connector is the active surface of the first chip.

[0067] Step S104: removing a portion of the plastic encapsulation layer and a portion of the semiconductor layer along the first direction until the second connector is exposed.

[0068] As an example, one or more of grinding, dry etching, and wet etching may be used to remove part of the plastic encapsulation layer and part of the semiconductor layer. The end of the second connector facing away from the first carrier protrudes out of the remaining semiconductor layer.

[0069] Step S106: After forming a second circuit layer on the plastic packaging layer, a second carrier is formed on the second circuit layer, and the second circuit layer is electrically connected to the second connecting member.

[0070] As an example, the second carrier may be a single-layer structure including a carrier, or may be a multi-layer structure including different film layers.

[0071] Step S108: removing the first carrier and the first bonding layer to expose the first circuit layer, where the first circuit layer is used to be electrically connected to at least one second chip.

[0072] As an example, the first bonding layer can be made less sticky by exposure, thereby removing the first carrier and the first bonding layer without damaging other film layers. The present application does not limit the specific method for removing the first carrier and the first bonding layer, which can be selected according to the material of the first bonding layer.

[0073] As an example, the second chip may include a bridge chip, a system on chip (SOC), a high bandwidth memory (HBM), etc. In other embodiments, the present application does not specifically limit the type of the second chip, and the second chip is used to implement a certain function.

[0074] In the above embodiment, the present application provides an initial plastic encapsulation structure, which includes a first circuit layer and a first chip, and part of the first connector of the first circuit layer is electrically connected to the second connector of the first chip, the first circuit layer is electrically connected to at least one second chip, and the second connector of the first chip is also electrically connected to the second circuit layer. The first chip is directly connected to the second carrier and the second chip respectively, thereby increasing the number of circuits and reducing the bearing pressure of a single circuit. At the same time, the present application makes the second connector protrude from the remaining semiconductor layer, so that the circuit material generated in the process of exposing the second connector will not diffuse into the remaining semiconductor layer. Therefore, when the second connector is electrically connected to the second circuit layer, it will not cause electrical connection between devices, circuit materials, second connectors, etc. in the semiconductor layer, thereby avoiding the formation of a short circuit.

[0075] In addition, in some related technologies, please refer to Figure 2a-2jThe method for preparing the semiconductor structure may further include: providing a first carrier 101, forming a first bonding layer 20 on the first carrier 101, bonding the back side (i.e., the side opposite to the active side) of at least one first chip 40 to the first bonding layer 20 using an adhesive layer 401, and forming a first dielectric layer 301 and a plurality of metal pillars 302 on the first bonding layer 20, wherein the first chip 40 includes an internal connector 403 and a semiconductor layer 402 wrapping the internal connector, forming a first plastic encapsulation layer 501 on the first bonding layer 20, the first chip 40, and the metal pillars 302, removing a portion of the first plastic encapsulation layer 501 in a direction perpendicular to the top surface of the first carrier to expose the connection pins and the metal pillars 302 on the active side of the first chip 40, and forming a first redistribution layer 60 on the remaining first plastic encapsulation layer 501, the first redistribution layer 60 including a second dielectric layer 601, a first metal layer 602, The first redistribution layer 60 is connected to the connection pins of the first chip 40 and the metal pillar 302, at least one second chip 701 is formed on the first redistribution layer 60, the pad 603 of the second chip 701 is connected to the pad 603 of the first redistribution layer 60, the pad 603 is wrapped with the glue layer 702, and a second plastic encapsulation layer 502 is formed on the first redistribution layer 60 and the second chip 701, the semiconductor structure is turned over, and the first bonding layer 20 and the first carrier 101 are removed to expose the back side of the first chip 40, a part of the first plastic encapsulation layer 501 and the adhesive layer 401 are removed to expose the metal pillar 302, and a second redistribution layer 80 and a plurality of solder joints 803 are formed on the remaining first plastic encapsulation layer 501, the second redistribution layer 80 includes a third dielectric layer 801 and a second metal layer 802, and the second metal layer 802 is respectively connected to the metal pillar 302 and the plurality of solder joints 803. In the above example, since the performance of the semiconductor device is easily degraded or even scrapped due to high temperature during the process of removing the first bonding layer 20 and forming the solder joint 803, and the production cost of the second chip 701 is relatively high, the process of first forming the second chip 701 and then removing the first bonding layer 20 and forming the solder joint 803 greatly increases the probability of scrapping the second chip 701, resulting in an increase in the preparation cost of the semiconductor structure. In the present application, the second chip 701 is connected to the first circuit layer after removing the first carrier 101 and the first bonding layer 20, which greatly reduces the probability of scrapping the second chip 701 and saves production costs.

[0076] Please refer to Figure 3 In one embodiment, step S102, providing an initial plastic packaging structure, includes: steps S302-S308.

[0077] Step S302: providing a substrate, wherein the substrate comprises a first carrier and a first bonding layer located on the first carrier.

[0078] As an example, see Figure 4aand Figure 4b , step S302 may further include the step of forming a reflective layer (not shown) on the first bonding layer 20; wherein the material of the reflective layer may include one or more metal materials such as cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), tantalum titanium (TaTi), tungsten nitride (WN), copper (Cu) and aluminum (Al). In the above example, by forming the reflective layer on the first bonding layer 20, the reflection can be enhanced when the first bonding layer 20 is removed, thereby improving the efficiency of removing the first bonding layer 20.

[0079] Step S304: forming a first circuit layer on the first bonding layer; wherein the first circuit layer includes a plurality of first connecting members.

[0080] As an example, see Figure 4c and Figure 4d , step S304, forming a first circuit layer on the first bonding layer 20 may include: forming a first dielectric layer 301 on the first bonding layer 20, the first dielectric layer 301 including a plurality of openings exposing the first bonding layer 20, forming a plurality of first connectors 303 on the first bonding layer 20 and the first dielectric layer 301 exposed by the openings, forming a second dielectric layer 601 on the plurality of first connectors 303 and the first dielectric layer 301, the second dielectric layer 601 including a plurality of openings exposing the plurality of first connectors 303; the first dielectric layer 301, the plurality of first connectors 303 and the second dielectric layer 601 are used to jointly constitute a first circuit layer.

[0081] Step S306: forming a first chip on the first circuit layer, and electrically connecting the second connecting component of the first chip to the first connecting component.

[0082] As an example, see Figure 4e-Figure 4g Before the second connector 404 of the first chip 40 is electrically connected to the first connector 303, a step of forming a pad 603 on the first connector 303 exposed by the partial opening is also included. By forming the pad 603 on one end of the second connector 404 exposed on the active surface of the first chip 40, the pad 603 on the first chip 40 is connected to the pad 603 on the first connector 303 by a welding technique such as reflow soldering, so that the second connector 404 of the first chip 40 is electrically connected to the first connector 303.

[0083] Step S308: forming a plastic packaging layer on the first circuit layer and the first chip.

[0084] As an example, please refer to Figure 4g and Figure 4hBefore forming the plastic encapsulation layer 503 on the first circuit layer and the first chip 40, an underfill process can be used to form a glue layer 702 between the active surface of the first chip 40 and the first circuit layer. The glue layer 702 wraps the pads 603, the solder joints 605 on the first chip 40, and the pads 603 on the first connector 303, thereby enhancing the stability of the connection between the first chip 40 and the first circuit layer.

[0085] In one embodiment, the preparation method further includes: forming a plurality of metal pillars on the first circuit layer, the metal pillars being connected to the remaining first connectors of the first circuit layer; and further, the plastic encapsulation layer covers the plurality of metal pillars.

[0086] As an example, please refer to Figure 4h The material of the metal pillar 302 may include one or more metal materials such as cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), tantalum titanium (TaTi), tungsten nitride (WN), copper (Cu) and aluminum (Al).

[0087] In one embodiment, please refer to Figure 5 , step S304, removing part of the plastic encapsulation layer and part of the semiconductor layer along the first direction until the second connector is exposed, including: step S502-step S506.

[0088] Step S502: removing a portion of the plastic encapsulation layer and a portion of the semiconductor layer along a first direction, and making the remaining plastic encapsulation layer cover the metal column when the remaining semiconductor layer exposes the second connector at a first target height.

[0089] In one embodiment, step S502, removing part of the plastic encapsulation layer and part of the semiconductor layer along a first direction, and making the remaining plastic encapsulation layer cover the metal column when the remaining semiconductor layer exposes the second connector at the first target height, includes: using a grinding process to remove part of the plastic encapsulation layer and part of the semiconductor layer along the first direction, so that the remaining semiconductor layer and the remaining plastic encapsulation layer cover the second connector and the metal column, and using a dry etching process to remove part of the semiconductor layer along the first direction to expose the second connector at the first target height.

[0090] Please refer to Figure 6a and Figure 6bAs an example, at the same time, the grinding process removes the same thickness of each region of the plastic encapsulation layer 503 and the semiconductor layer 402 in the first direction. The grinding process is used to remove part of the plastic encapsulation layer 503 and part of the semiconductor layer 402 along the first direction, so that the remaining semiconductor layer 402 and the remaining plastic encapsulation layer 503 cover the second connector 404 and the metal column 302. After the grinding process, the surface of the remaining semiconductor layer 402 away from the first carrier is higher than the surface of the second connector 404 away from the first carrier, and the second target distance B between the surface of the remaining semiconductor layer 402 away from the first carrier and the surface of the second connector 404 away from the first carrier is 5 microns-15 microns.

[0091] As an example, the second target distance B is 5 microns, 8 microns, 10 microns, 12 microns, 13 microns, 14 microns, 15 microns, etc.

[0092] As an example, the dry etching includes at least any one of reactive ion etching (RIE), inductively coupled plasma etching (ICP), or high concentration plasma etching (HDP).

[0093] In one embodiment, the first target height A is 10 micrometers to 15 micrometers.

[0094] As an example, see Figure 6c , the first target height A is 10 microns, 11 microns, 12 microns, 13 microns, 14 microns, and 15 microns.

[0095] In the above embodiment, a grinding process is first used to remove part of the plastic encapsulation layer 503 and part of the semiconductor layer 402 along the first direction, so that the remaining semiconductor layer 402 and the remaining plastic encapsulation layer 503 do not expose the second connector 404 and the metal column 302, and then a dry etching process is used to remove part of the semiconductor layer 402 along the first direction to expose the second connector 404 of the first target height A. On the one hand, compared with directly using dry etching, the time consumption is shorter and the removal efficiency of the plastic encapsulation layer 503 and the semiconductor layer 402 can be improved. On the other hand, the grinding process can avoid the generation of circuit material in the process of removing the semiconductor layer 402 and exposing the second connector 404, resulting in the diffusion of the circuit material into the remaining semiconductor layer 402, causing the circuit material in the semiconductor layer 402 and the devices and circuit structures in the semiconductor layer 402 to form a short-circuit structure in the subsequent process of connecting the second connector 404 and the second circuit layer.

[0096] Step S504: forming a dielectric layer at least on the remaining semiconductor layer and the second connecting member exposed to a first target height.

[0097] As an example, see Figure 6dThe material of the dielectric layer 90 may include, but is not limited to, one or more of a silicon oxide layer (SiO2), a silicon nitride layer (Si3N4), an aluminum oxide (Al2O3) or a silicon oxynitride layer (SiON).

[0098] As an example, the thickness of the dielectric layer 90 in the first direction is greater than the first target height. In addition, the dielectric layer 90 may also cover the remaining plastic encapsulation layer 503 .

[0099] As an example, a spin coating process may be used to form the dielectric layer 90 on the remaining semiconductor layer 402 and the second connector 404 exposed at the first target height.

[0100] Step S506: removing part of the dielectric layer and the remaining plastic encapsulation layer along the first direction until the second connector and the metal pillar are exposed; the surface of the remaining dielectric layer is flush with the surface of the remaining plastic encapsulation layer.

[0101] As an example, see Figure 6e , a grinding process may be used to remove a portion of the dielectric layer 90 and the remaining plastic encapsulation layer 503 along the first direction until the second connector 404 and the metal pillar 302 are exposed.

[0102] In the above embodiment, since the circuit material generated during the grinding process will not diffuse into the dielectric layer 90 and the dielectric layer 90 does not have other circuit structures or components, the dielectric layer 90 is used to cover the remaining semiconductor layer 402 to avoid forming a short circuit structure.

[0103] In one embodiment, please refer to Figure 7 , step S106, forming a second circuit layer on the plastic packaging layer, including: steps S702-S708.

[0104] Step S702: forming a plurality of third connecting members on the plastic packaging layer; wherein the third connecting members are at least electrically connected to the second connecting members.

[0105] As an example, see Figure 8a and Figure 8b The second circuit layer includes a third dielectric layer 801 , a third connecting member 804 and a fourth dielectric layer 805 .

[0106] Step S704: forming a pad at an end of the third connecting member away from the first carrier.

[0107] As an example, please refer to Figure 8b , the pad 603 is electrically connected to the third connecting member 804 .

[0108] Step S706: forming a solder joint on the solder pad, wherein a side of the solder joint facing away from the first carrier is used for fixing to the second carrier.

[0109] As an example, please refer to Figure 8b , a solder joint 803 may be formed on the solder pad 603 by using a reflow soldering process or a wave soldering process.

[0110] In one embodiment, forming the second carrier includes: forming a protection layer on the solder joints, and fixing a surface of the protection layer facing away from the first carrier to the second carrier.

[0111] As an example, see Figure 8c The material of the protection layer 102 may include an adhesive layer having an adhesive property, and the solder joint 803 is fixed to the second carrier board 103 through the adhesive layer.

[0112] In one embodiment, please refer to Fig. 9 , step S304, removing part of the plastic encapsulation layer and part of the semiconductor layer along the first direction until the second connector is exposed, including: step S902-step S904.

[0113] Step S902: removing the plastic encapsulation layer and the semiconductor layer along a first direction by a grinding process until the second connector of the first chip is exposed.

[0114] As an example, the preparation method also includes the step of forming a plurality of metal pillars on the first circuit layer, and connecting the metal pillars to the remaining first connectors of the first circuit layer; step S092 also includes exposing the metal pillars while exposing the second connectors of the first chip.

[0115] Step S904: using a dry etching process to remove part of the semiconductor layer along the first direction so that the second connector protrudes from the remaining semiconductor layer, thereby removing the circuit material remaining in the semiconductor layer; wherein the circuit material is the same as the material of the second connector.

[0116] In the above embodiment, since grinding residues (i.e., circuit materials) of the second connector are generated in the process of exposing the second connector of the first chip, the circuit materials will diffuse into the remaining semiconductor layer. In the process of connecting the second connector and the second circuit layer, the circuit materials in the semiconductor layer and the original components or connecting circuits in the semiconductor layer will be connected together to form a short-circuit structure. Therefore, after the second connector is exposed, dry etching is used to remove part of the semiconductor layer to remove the circuit materials remaining in the semiconductor layer to avoid the formation of a short-circuit structure. In the process of forming the second circuit layer on the plastic packaging layer, the exposed second connector can be wrapped with materials such as the third dielectric layer in the process to improve the flatness of each film layer.

[0117] In one embodiment, please refer to Figure 10a-Figure 10c, step S108, removing the first carrier and the first bonding layer to expose the first circuit layer, the first circuit layer is used to be electrically connected to at least one second chip, and also includes: using an exposure process to remove the first bonding layer 20 and the first carrier 101, forming a pad 603 on the exposed first connector 303, connecting the pad 603 on the active surface of the second chip 701 with the pad 603 on the first connector 303, and wrapping the pad 603 with an adhesive layer 702 to fix the second chip 701.

[0118] In the above-mentioned embodiment of the present application, by providing an initial plastic encapsulation structure, the initial plastic encapsulation structure includes a first circuit layer and a first chip, and part of the first connector of the first circuit layer is electrically connected to the second connector of the first chip, the first circuit layer is electrically connected to at least one second chip, and the second connector of the first chip is also electrically connected to the second circuit layer, and the first chip is directly connected to the second circuit layer and the second chip respectively, so that the number of circuits is increased, thereby reducing the bearing pressure of a single circuit. After removing part of the plastic encapsulation layer and part of the semiconductor layer and exposing the second connector of the first chip, a second circuit layer electrically connected to the second connector is formed on the plastic encapsulation layer, a second carrier is formed on the second circuit layer, and then the first carrier and the first bonding layer are removed by debonding to expose the first circuit layer, and then the second chip is formed on the first circuit layer, that is, the second chip is formed after the step of removing the first carrier and the first bonding layer by debonding. Compared with the step of performing the step of removing the first carrier and the first bonding layer by debonding after the second chip is formed, this embodiment avoids the adverse effects of the debonding process on the second chip, and effectively improves the yield and reliability of the semiconductor structure.

[0119] Furthermore, the present application can arrange the second connector to partially protrude from the remaining semiconductor layer to form a groove, so that the dielectric layer covering the top surface of the second connector can be filled in the groove, thereby preventing the circuit material from diffusing into the remaining semiconductor layer during the process of planarizing the top surface of the dielectric layer. Therefore, when the second connector is electrically connected to the second circuit layer, it will not cause electrical connection between devices, circuit materials, etc. in the semiconductor layer, thereby avoiding the formation of a short circuit.

[0120] It should be understood that although Figure 1 , Figure 3 , Figure 5 , Figure 7 , Fig. 9 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1 , Figure 3 , Figure 5 , Figure 7 , Fig. 9At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0121] Please refer to Fig.10c In one embodiment, the present application further provides a semiconductor structure, comprising: a second carrier 103, a plastic encapsulation layer 503, a first chip 40, a first circuit layer (not shown) and a second circuit layer (not shown); wherein the plastic encapsulation layer 503 is located on the second carrier 103, and the plastic encapsulation layer 503 includes at least one first chip 40; wherein the first chip 40 includes a second connector 404 and a semiconductor layer 402 wrapping the second connector 404; the first circuit layer is located on the first chip 40 and the plastic encapsulation layer 503; part of the first connector 303 of the first circuit layer is electrically connected to the second connector 404; the first circuit layer is used to be electrically connected to at least one second chip 701; the second circuit layer is located on the plastic encapsulation layer 503, and the second circuit layer is electrically connected to the second connector 404; the second carrier 103 is located on the second circuit layer.

[0122] Please refer to Figure 6c-6d In one embodiment, the height of the second connector 404 protruding from the semiconductor layer 402 is a first target height A; the semiconductor structure further includes: a dielectric layer 90, located between the second carrier 103 and the semiconductor layer 402, surrounding the second connector 404 of the first target height A; the surface of the dielectric layer 90 close to the second carrier 103 is flush with the surface of the plastic encapsulation layer 503 close to the second carrier 103.

[0123] In one embodiment, the first target height A is 10 micrometers to 15 micrometers.

[0124] As an example, the first target height A is 10 microns, 11 microns, 12 microns, 13 microns, 14 microns, or 15 microns.

[0125] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0126] The above embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: An initial plastic encapsulation structure is provided, the initial plastic encapsulation structure comprising a first carrier, a first bonding layer, a first circuit layer, a first chip and a plastic encapsulation layer stacked in sequence along a first direction; wherein the first direction is a direction perpendicular to a top surface of the first carrier; a portion of first connectors of the first circuit layer are electrically connected to second connectors of the first chip; the first chip comprises the second connector and a semiconductor layer wrapping the second connector; removing a portion of the plastic encapsulation layer and a portion of the semiconductor layer along the first direction until the second connecting member is exposed; After forming a second circuit layer on the plastic packaging layer, forming a second carrier on the second circuit layer, the second circuit layer is electrically connected to the second connecting member; The first carrier board and the first bonding layer are removed to expose the first circuit layer, where the first circuit layer is used to be electrically connected to at least one second chip.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: Removing a portion of the plastic encapsulation layer and a portion of the semiconductor layer along the first direction until the second connecting member is exposed, comprising: Using a grinding process to remove the plastic encapsulation layer and the semiconductor layer along the first direction until the second connector of the first chip is exposed; A portion of the semiconductor layer is removed along the first direction so that the second connector partially protrudes from the remaining semiconductor layer, thereby removing the circuit material remaining on the semiconductor layer; wherein the circuit material is the same as the material of the second connector.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that: The preparation method further includes forming a plurality of metal pillars on the first circuit layer, wherein the metal pillars are connected to the remaining first connectors of the first circuit layer; The removing part of the plastic encapsulation layer and part of the semiconductor layer along the first direction until the second connecting member is exposed includes: removing part of the plastic encapsulation layer and part of the semiconductor layer along the first direction, and making the remaining plastic encapsulation layer cover the metal column when the remaining semiconductor layer exposes the second connector at a first target height; forming a dielectric layer at least on the remaining semiconductor layer and the second connecting member exposed to a first target height; Part of the dielectric layer and the remaining plastic encapsulation layer are removed along the first direction until the second connector and the metal column are exposed; and the surface of the remaining dielectric layer is flush with the surface of the remaining plastic encapsulation layer.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that: Removing part of the plastic encapsulation layer and part of the semiconductor layer along the first direction, and making the remaining plastic encapsulation layer cover the metal column when the remaining semiconductor layer exposes the second connector at a first target height, comprises: Using a grinding process to remove part of the plastic encapsulation layer and part of the semiconductor layer along the first direction, so that the remaining semiconductor layer and the remaining plastic encapsulation layer cover the second connecting member and the metal column respectively; A portion of the semiconductor layer is removed along the first direction to expose the second connecting member at the first target height.

5. The method for preparing a semiconductor structure according to claim 4, characterized in that: The first target height is 10 micrometers to 15 micrometers.

6. The method for preparing a semiconductor structure according to any one of claims 1 to 4, characterized in that: The initial plastic packaging structure is provided, comprising: Providing a substrate, wherein the substrate comprises a first carrier and the first bonding layer located on the first carrier; forming a first circuit layer on the first bonding layer; wherein the first circuit layer includes a plurality of the first connecting members; forming a first chip on the first circuit layer, wherein the second connecting member of the first chip is electrically connected to a part of the first connecting member; The plastic packaging layer is formed on the first circuit layer and the first chip.

7. The method for preparing a semiconductor structure according to any one of claims 1 to 4, characterized in that: Forming the second circuit layer includes: A plurality of third connecting members are formed on the plastic encapsulation layer; wherein the third connecting members are at least electrically connected to the second connecting members; forming a solder pad at an end of the third connecting member facing away from the first carrier board; A soldering point is formed on the soldering pad; a side of the soldering point facing away from the first carrier is used for fixing with the second carrier.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that: The second carrier board is formed, comprising: forming a protective layer on the solder joint; The side of the protective layer facing away from the first carrier board is fixed to the second carrier board.

9. A semiconductor structure, characterized in that: include: Second carrier board; A plastic encapsulation layer, located on the second carrier, wherein the plastic encapsulation layer includes at least one first chip; wherein the first chip includes a second connector and a semiconductor layer wrapping the second connector; and the second connector is electrically connected to the second circuit layer; A first circuit layer is located on the first chip and the plastic packaging layer; some first connectors of the first circuit layer are electrically connected to the second connectors; and the first circuit layer is used to be electrically connected to at least one second chip; A second circuit layer is located on the plastic packaging layer, and the second circuit layer is electrically connected to the second connecting member; The second carrier board is located on the second circuit layer.

10. The semiconductor structure according to claim 9, characterized in that: The height of the second connecting member protruding from the semiconductor layer is a first target height; The semiconductor structure further comprises: a dielectric layer, located between the second carrier and the semiconductor layer, surrounding the second connector at the first target height; A surface of the dielectric layer close to the second carrier is flush with a surface of the plastic layer close to the second carrier.

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