Folded cascode structure operational amplifier circuit with low power consumption and high slew rate

Abstract

The invention belongs to the field of integrated circuits, and provides a folded cascode structure operational amplifier circuit with low power consumption and high slew rate, which is used for solving the problems of low slew rate, high power consumption and the like in the prior art. The flip voltage follower comprises current sources I0-I4, transistors M1-M14, a resistor R1 and a load capacitor CL, and on the basis of a traditional folded cascode structure, a flip voltage follower differential structure (DFVF) composed of transistors M4, M7 and M8, a flip voltage follower current sensor (FVFCS) composed of transistors M3, M4 and M8, and a source follower composed of a transistor M14 and the current source I4 are introduced. The DFVF is used for improving the discharge current of the load capacitor in the negative conversion stage, and meanwhile, the FVFCS is used for improving the charge current of the load capacitor in the positive conversion stage, so that the slew rate of the operational amplifier circuit is greatly improved, and under the condition, the maximum tail current of differential input can reach more than one hundred times of the current of the middle stage; therefore, the power consumption of the operational amplifier circuit is obviously reduced.

Description

Technical Field

[0001] The invention belongs to the field of integrated circuits, relates to operational amplifier circuits, and specifically provides a folded common-source common-gate structure operational amplifier circuit with low power consumption and large slew rate. Background Art

[0002] In the process of signal processing, the operational amplifier usually collects the signal, and then the ADC (Analog-to-Digital Converter) circuit converts the analog signal into a digital signal for processing; the slew rate refers to the response speed of the operational amplifier to a large step signal, that is, when a large step signal is input to the operational amplifier, the conversion rate of the operational amplifier from the initial state to the final steady state.

[0003] At present, the commonly used folded cascode structure operational amplifier circuits are as follows: Figure 1 As shown, for this type of operational amplifier, the slew rate is calculated as SR = I0 / CL, where I0 is the current of the input stage tail current source and CL is the load capacitance. However, the slew rate is limited by the size of the intermediate stage quiescent current. When the intermediate stage quiescent current is much smaller than the current of the input stage tail current source I0, the slew rate no longer satisfies SR = I0 / CL. Specifically:

[0004] In the positive conversion stage, that is, when VIN+ is much greater than VIN-; assuming that the static current of MOSFET M17 is equal to the static current of MOSFET M18, which is Im, the static current of MOSFET M21 is Im21, and the static current flowing through the MOSFET M6 branch is Im22, and Im21 is equal to Im22; at the moment when the positive conversion starts, the current I0 in the input tail current source almost all flows through MOSFET M16 and enters MOSFET M1. 8. At this time, the drain voltage of the MOSFET M18 rises sharply, causing the MOSFET M20 to be cut off. At the same time, the excessively high drain voltage of the MOSFET M18 causes the MOSFET M16 to enter the linear region, causing the input differential pair to lose its ability to control the current. As a result, the current flowing through the MOSFET M16 is actually generated by the MOSFET M18. At this time, due to the effective channel length adjustment effect, the MOSFET M18 The generated current is greater than its static current Im. For the sake of analysis, it is approximately considered that the current flowing through the metal oxide semiconductor field effect transistor M18 is still Im at this time. Although at the moment when the positive conversion starts, the current in the input tail current source hardly flows through the metal oxide semiconductor field effect transistor M15 and enters the metal oxide semiconductor field effect transistor M17. The metal oxide semiconductor field effect transistor M17 enters the linear region at the beginning, but then the metal oxide semiconductor field effect transistor M16 only divides the current of Im, resulting in a current of I0-Im flowing through the metal oxide semiconductor field effect transistor M17. The transistor M15 enters the MOSFET M17, and the MOSFET M17 enters the saturation region. In this case, the current flowing through the MOSFET M19 is Im-(I0-Im), that is, Im21+Im22. This current enters the branch of the MOSFET M22 and the MOSFET M24 through the current mirror formed by the MOSFET M21 and the MOSFET M22, thereby providing current for charging the load capacitor CL.

[0005] In the negative conversion stage, that is, when VIN+ is much smaller than VIN-; assuming that the static current of MOSFET M17 is equal to the static current of MOSFET M18, which is Im, the static current of MOSFET M21 is Im21, and the static current flowing through the MOSFET M6 branch is Im22, and Im21 is equal to Im22; at the moment when the negative conversion starts, the current in the input tail current source almost all flows through MOSFET M15 into MOSFET M17, and at this time, MOSFET M17 is equal to Im22. The drain voltage of the metal oxide semiconductor field effect transistor M17 rises sharply, causing the metal oxide semiconductor field effect transistor M19 to be turned off, so that no current flows through the metal oxide semiconductor field effect transistor M21. The metal oxide semiconductor field effect transistors M21 and M22 form a current mirror, and the current flowing through the metal oxide semiconductor field effect transistors M22 and M24 is also zero; at the same time, the excessively high drain voltage of the metal oxide semiconductor field effect transistor M17 causes the metal oxide semiconductor field effect transistor M15 to enter the linear region, thereby making the input The input differential pair loses the ability to control the current; thus, the current flowing through the metal oxide semiconductor field effect transistor M1 is actually generated by the metal oxide semiconductor field effect transistor M17. At this time, due to the effective channel length adjustment effect, the current generated by the metal oxide semiconductor field effect transistor M17 is greater than its static current Im. For the convenience of analysis, it is approximately considered that the current flowing through the metal oxide semiconductor field effect transistor M17 is still Im at this time; although at the moment when the negative conversion begins, the current in the input tail current source hardly flows through the metal oxide semiconductor field effect transistor M16 and enters the metal oxide semiconductor field effect transistor M18, the metal oxide semiconductor field effect transistor M18 enters the linear region at the beginning, but then the metal oxide semiconductor field effect transistor M15 only divides the current of Im, resulting in a current of I0-Im flowing through the metal oxide semiconductor field effect transistor M16 and entering the metal oxide semiconductor field effect transistor M18. At this time, the metal oxide semiconductor field effect transistor M18 enters the saturation region; in this case, the current flowing through the metal oxide semiconductor field effect transistor M20 is Im-(I0-Im), that is, Im21+Im22, and this current provides current for the discharge of the load capacitor CL.

[0006] It can be seen from this that when the intermediate stage current is much smaller than the input stage tail current source, its slew rate is limited by the intermediate stage current and thus greatly reduced; therefore, in normal circuit design, in order to ensure that the slew rate can meet the requirements, the intermediate stage current and the tail current of the differential input are generally set at the same level, thereby getting rid of the limitation of the intermediate stage current and making the slew rate satisfy the calculation formula SR=I0 / CL; however, under normal circumstances, the input stage tail current of the operational amplifier is usually very large. If the intermediate stage current and the input stage tail current are set at the same level, it will cause a large amount of static current consumption. Summary of the invention

[0007] The purpose of the present invention is to provide a folded cascode structure operational amplifier circuit with low power consumption and large slew rate, so as to solve the problems of low slew rate and high power consumption in the existing folded cascode structure operational amplifier circuit; the present invention is based on the folded cascode structure design, and uses a flip voltage follower differential structure (DFVF) to increase the load capacitor discharge current in the negative conversion stage, and uses a flip voltage follower current sensor (FVFCS) to increase the load capacitor charging current in the positive conversion stage, thereby greatly improving the slew rate of the operational amplifier circuit. In this case, the tail current of the differential input can reach more than one hundred times the intermediate stage current, thereby significantly reducing the power consumption of the operational amplifier circuit.

[0008] To achieve the above object, the technical solution adopted by the present invention is:

[0009] A low-power, high-slew-rate folded common-source common-gate operational amplifier circuit comprises: current sources I0-I4, transistors M1-M14, a thin-film resistor R1, and a load capacitor CL; wherein:

[0010] The gate of transistor M1 is connected to the non-inverting input terminal VIN+, and the gate of transistor M2 is connected to the inverting input terminal VIN-; the source of transistor M1 and the source of transistor M2 are connected, and the current source I0 is connected between the source of transistor M1 and the positive power rail; the drain of transistor M1, the drain of transistor M3, the source of transistor M5, and the source of transistor M6 are connected;

[0011] The drain of transistor M2, the drain of transistor M4, the source of transistor M7, and the source of transistor M8 are connected, the source of transistor M3 and the source of transistor M4 are connected to the negative power rail, the gate of transistor M3, the gate of transistor M4, and the drain of transistor M8 are connected, and the current source I3 is connected between the drain of transistor M8 and the positive power rail;

[0012] The gate of transistor M5, the gate of transistor M8, and the gate of transistor M9 are connected, the drain of transistor M9 is connected to the gate, the current source I1 is connected between the drain of transistor M9 and the positive power rail, and the thin film resistor R1 is connected between the gate of transistor M9 and the negative power rail; the drain of transistor M5, the gate of transistor M10, the gate of transistor M11, the drain of transistor M12, and the gate of transistor M14 are connected;

[0013] The gate of transistor M12, the gate of transistor M13, and the source of transistor M14 are connected, and the current source I4 is connected between the source of transistor M14 and the negative power rail; the source of transistor M10, the source of transistor M11, and the drain of transistor M14 are all connected to the positive power rail, the drain of transistor M10 and the source of transistor M12 are connected, and the drain of transistor M11 and the source of transistor M13 are connected;

[0014] The gate of transistor M6, the gate of transistor M7, and the drain of transistor M6 are connected to the gate, and the current source I1 is connected between the gate of transistor M6 and the positive power rail; the drain of transistor M7 and the drain of transistor M13 are connected and connected to the output voltage terminal Vout, and the load capacitor CL is connected between the output voltage terminal Vout and the negative power rail.

[0015] Furthermore, the transistor M4, the transistor M7, and the transistor M8 form a flipped voltage follower differential structure (DFVF).

[0016] Furthermore, the transistor M3 , the transistor M4 , and the transistor M8 constitute a flipped voltage follower current sensor (FVFCS).

[0017] Furthermore, the transistor M14 and the current source I4 form a source follower.

[0018] Furthermore, the current sources I0 to I4 are all cascode current sources.

[0019] Furthermore, the transistors M1 to M14 are all metal oxide semiconductor field effect transistors.

[0020] Based on the above technical solution, the beneficial effects of the present invention are:

[0021] The present invention provides a folded common source and common gate structure operational amplifier circuit with low power consumption and large slew rate. On the basis of a traditional folded common source and common gate structure, a flip voltage follower differential structure (DFVF) composed of transistors M4, transistors M7 and transistors M8, a flip voltage follower current sensor (FVFCS) composed of transistors M3, transistors M4 and transistors M8, and a source follower composed of transistor M14 and current source I4 are introduced. The flip voltage follower differential structure (DFVF) is used to increase the discharge current of the load capacitor in the negative conversion stage, and at the same time, the flip voltage follower current sensor (FVFCS) is used to increase the charging current of the load capacitor in the positive conversion stage, thereby greatly improving the slew rate of the operational amplifier circuit. In this case, the maximum differential input tail current can reach more than one hundred times the intermediate stage current, thereby significantly reducing the power consumption of the operational amplifier circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 This is a schematic diagram of the circuit structure of a traditional folded common-source common-gate structure operational amplifier circuit.

[0023] Figure 2 The circuit structure diagram of the folded cascode structure operational amplifier circuit with low power consumption and high slew rate in the present invention.

[0024] Figure 3 It is a schematic diagram of the circuit structure of the common-source and common-gate current source in the present invention.

[0025] Figure 4 The diagram is a schematic diagram of the circuit structure of the differential flip voltage follower structure (DFVF) in the present invention and a schematic diagram of the current-voltage relationship thereof.

[0026] Figure 5 The diagram is a schematic diagram of the circuit structure of the flipped voltage follower current sensor structure (FVFCS) in the present invention and a schematic diagram of the current-voltage relationship thereof.

[0027] Figure 6 The figure is a comparison diagram of the slew rate of the folded cascode structure operational amplifier circuit in the embodiment of the present invention and the comparative example. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solution and beneficial effects of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments.

[0029] This embodiment provides a low-power, high-slew-rate folded cascode operational amplifier circuit, whose circuit structure is as follows: Figure 2 As shown, VIN+ is the non-inverting input terminal of the operational amplifier circuit, VIN- is the inverting input terminal of the operational amplifier circuit, VOUT is the output voltage terminal of the input stage of the operational amplifier circuit, AVDD is the positive power supply, and AVSS is the negative power supply.

[0030] Specifically, the folded common-source common-gate operational amplifier circuit includes: a common-source common-gate current source I0, a common-source common-gate current source I1, a common-source common-gate current source I2, a common-source common-gate current source I3, a common-source common-gate current source I4, a metal oxide semiconductor field effect transistor M1, a metal oxide semiconductor field effect transistor M2, a metal oxide semiconductor field effect transistor M3, a metal oxide semiconductor field effect transistor M4, a metal oxide semiconductor field effect transistor M5, a metal oxide semiconductor field effect transistor M6, a metal oxide semiconductor field effect transistor M7, a metal oxide semiconductor field effect transistor M8, a metal oxide semiconductor field effect transistor M9, a metal oxide semiconductor field effect transistor M10, a metal oxide semiconductor field effect transistor M11, a metal oxide semiconductor field effect transistor M12, a metal oxide semiconductor field effect transistor M13, a metal oxide semiconductor field effect transistor M14, a thin film resistor R1, and a load capacitor CL; wherein:

[0031] The gate of the metal oxide semiconductor field effect transistor M1 is connected to the non-inverting input terminal VIN+, and the gate of the metal oxide semiconductor field effect transistor M2 is connected to the inverting input terminal VIN-;

[0032] The source of the metal oxide semiconductor field effect transistor M1 and the source of the metal oxide semiconductor field effect transistor M2 are connected, and the common source and common gate current source I0 is connected between the source of the metal oxide semiconductor field effect transistor M1 and the positive power rail;

[0033] The drain of the metal oxide semiconductor field effect transistor M1, the drain of the metal oxide semiconductor field effect transistor M3, the source of the metal oxide semiconductor field effect transistor M5, and the source of the metal oxide semiconductor field effect transistor M6 are connected;

[0034] The drain of the metal oxide semiconductor field effect transistor M2, the drain of the metal oxide semiconductor field effect transistor M4, the source of the metal oxide semiconductor field effect transistor M7, and the source of the metal oxide semiconductor field effect transistor M8 are connected;

[0035] The source of the metal oxide semiconductor field effect transistor M3 and the source of the metal oxide semiconductor field effect transistor M4 are both connected to the negative power rail;

[0036] The gate of the metal oxide semiconductor field effect transistor M3, the gate of the metal oxide semiconductor field effect transistor M4, and the drain of the metal oxide semiconductor field effect transistor M8 are connected, and the common source and common gate current source I3 is connected between the drain of the metal oxide semiconductor field effect transistor M8 and the positive power rail;

[0037] The gate of the metal oxide semiconductor field effect transistor M5, the gate of the metal oxide semiconductor field effect transistor M8, and the gate of the metal oxide semiconductor field effect transistor M9 are connected (the connection point is Vcon), the drain of the metal oxide semiconductor field effect transistor M9 is connected to the gate, the common source and common gate current source I1 is connected between the drain of the metal oxide semiconductor field effect transistor M9 and the positive power rail, and the thin film resistor R1 is connected between the gate of the metal oxide semiconductor field effect transistor M9 and the negative power rail;

[0038] The drain of the metal oxide semiconductor field effect transistor M5, the gate of the metal oxide semiconductor field effect transistor M10, the gate of the metal oxide semiconductor field effect transistor M11, the drain of the metal oxide semiconductor field effect transistor M12, and the gate of the metal oxide semiconductor field effect transistor M14 are connected;

[0039] The gate of the metal oxide semiconductor field effect transistor M12, the gate of the metal oxide semiconductor field effect transistor M13, and the source of the metal oxide semiconductor field effect transistor M14 are connected, and the common source and common gate current source I4 is connected between the source of the metal oxide semiconductor field effect transistor M14 and the negative power rail;

[0040] The source of the metal oxide semiconductor field effect transistor M10, the source of the metal oxide semiconductor field effect transistor M11, and the drain of the metal oxide semiconductor field effect transistor M14 are all connected to the positive power rail;

[0041] The drain of the metal oxide semiconductor field effect transistor M10 and the source of the metal oxide semiconductor field effect transistor M12 are connected, and the drain of the metal oxide semiconductor field effect transistor M11 and the source of the metal oxide semiconductor field effect transistor M13 are connected;

[0042] a gate of the metal oxide semiconductor field effect transistor M6, a gate of the metal oxide semiconductor field effect transistor M7, a drain of the metal oxide semiconductor field effect transistor M6 is connected to the gate, and a common source and common gate current source I1 is connected between the gate of the metal oxide semiconductor field effect transistor M6 and a positive power rail;

[0043] The drain of the MOSFET M7 and the drain of the MOSFET M13 are connected to each other and to the output voltage terminal Vout. The load capacitor CL is connected between the output voltage terminal Vout and the negative power rail.

[0044] Furthermore, the circuit structure of the common-source and common-gate current source is as follows: Figure 3As shown, Vb1, Vb2, Vb3, and Vb4 are bias voltage terminals, I is the output current of the common-source and common-gate current source, AVDD is the positive power supply, and AVSS is the negative power supply.

[0045] Furthermore, the metal oxide semiconductor field effect transistor M4, the metal oxide semiconductor field effect transistor M7, and the metal oxide semiconductor field effect transistor M8 constitute a flip voltage follower differential structure (DFVF), and its circuit structure diagram and current-voltage relationship diagram are as shown in FIG. Figure 4 As shown, V1 and V2 are voltage input terminals, Ib is the bias current of the flip voltage follower differential structure, IDM3 is the output current of the flip voltage follower differential structure, AVDD is the positive power supply, and AVSS is the negative power supply; under normal working conditions, the current-voltage relationship of the flip voltage follower differential structure is as follows: Figure 4 shown.

[0046] Furthermore, the metal oxide semiconductor field effect transistor M3, the metal oxide semiconductor field effect transistor M4, and the metal oxide semiconductor field effect transistor M8 constitute a flip voltage follower current sensor (FVFCS), and its circuit structure diagram and current-voltage relationship diagram are shown in FIG. Figure 5 As shown, V1 is the bias voltage terminal, Iin is the current input terminal, Ib is the bias current of the flip voltage follower current sensor, Iout is the output current of the flip voltage follower current sensor, AVDD is the positive power supply, and AVSS is the negative power supply; under normal working conditions, the current-voltage relationship of the flip voltage follower current sensor is as follows Figure 5 shown.

[0047] In terms of working principle:

[0048] like Figure 2 As shown, in the folded common-source common-gate operational amplifier circuit proposed in the present invention, the metal oxide semiconductor field effect transistor M4, the metal oxide semiconductor field effect transistor M7, and the metal oxide semiconductor field effect transistor M8 constitute a flip voltage follower differential structure (DFVF), the metal oxide semiconductor field effect transistor M3, the metal oxide semiconductor field effect transistor M4, and the metal oxide semiconductor field effect transistor M8 constitute a flip voltage follower current sensor (FVFCS), the metal oxide semiconductor field effect transistor M14 and the common-source common-gate current source I4 constitute a source follower, the flip voltage follower differential structure (DFVF) plays a role in improving the slew rate in the negative conversion stage, and the flip voltage follower current sensor (FVFCS) and the source follower play a role in improving the slew rate in the positive conversion stage;

[0049] In the negative conversion stage, that is, when VIN+ is much smaller than VIN-, at this time, the current of the input current source I0 almost flows through the MOSFET M1 into the MOSFET M3, thereby causing the drain potential of the MOSFET M3 to rise rapidly. Since the current of the MOSFET M6 is constant, the gate voltage of the MOSFET M6 increases with the increase of the drain voltage of the MOSFET M3. For the MOSFET M4, the MOSFET M7, and the MOSFET M8, a flip voltage follower differential structure (DFVF) is formed. The gate voltage of the oxide semiconductor field effect transistor M7 increases, and the current of the metal oxide semiconductor field effect transistor M7 increases rapidly. Finally, when the current flowing through the metal oxide semiconductor field effect transistor M4 reaches I0, the metal oxide semiconductor field effect transistor M3 can maintain a current of I0, and the drain voltage of the metal oxide semiconductor field effect transistor M3 reaches a maximum value. At this time, the current in the metal oxide semiconductor field effect transistor M7 also reaches a maximum value, which is approximately I0. The current in the metal oxide semiconductor field effect transistor M7 is all derived from the discharge of the load capacitor. Therefore, when the intermediate stage static current is much smaller than the input stage tail current, the load capacitor discharge current in the negative conversion stage is greatly improved, thereby improving the slew rate in the negative conversion stage;

[0050] In the positive conversion stage, that is, when VIN+ is much greater than VIN-; at this time, the current of the input current source I0 almost flows through the metal oxide semiconductor field effect transistor M2 and enters the metal oxide semiconductor field effect transistor M4; for the metal oxide semiconductor field effect transistor M3, the metal oxide semiconductor field effect transistor M4, and the metal oxide semiconductor field effect transistor M8 constitute a flip voltage follower current sensor (FVFCS), as the input current increases rapidly, the current of the metal oxide semiconductor field effect transistor M3 also increases, and thus the current of the metal oxide semiconductor field effect transistor M10 also increases; at this time, the gate voltage of the metal oxide semiconductor field effect transistor M10 decreases, and through the effect of the source follower composed of the metal oxide semiconductor field effect transistor M14 and the common source and common gate current source I4, the gate voltage of the metal oxide semiconductor field effect transistor M12 and the metal oxide semiconductor field effect transistor M13 decreases accordingly, so that the metal oxide field effect transistor M10 is connected to the metal oxide semiconductor field effect transistor M14. The semiconductor field effect transistor M12 and the metal oxide semiconductor field effect transistor M13 will not limit the current of the metal oxide semiconductor field effect transistor M10 and the metal oxide semiconductor field effect transistor M11. Therefore, the current of the metal oxide semiconductor field effect transistor M11 also increases through the current source formed by the metal oxide semiconductor field effect transistor M10 and the metal oxide semiconductor field effect transistor M11. Finally, the current flowing through the metal oxide semiconductor field effect transistor M3 is equal to the current size I0 in the metal oxide semiconductor field effect transistor M4, and the current flowing through the metal oxide semiconductor field effect transistor M11 is equal to the current size I0 in the metal oxide semiconductor field effect transistor M10. The current in the metal oxide semiconductor field effect transistor M11 is all used to charge the load capacitor. Therefore, when the intermediate stage static current is much smaller than the input stage tail current, the load capacitor charging current in the positive conversion stage is greatly improved, thereby improving the slew rate in the positive conversion stage.

[0051] In summary, Figure 1 The conventional folded cascode structure operational amplifier circuit shown in FIG. 1 is a comparative example. The slew rate comparison results of the folded cascode structure operational amplifier circuit in the present embodiment and the comparative example are shown in FIG. Figure 6 As shown, under the same quiescent current consumption (taking the input stage tail current of 100μA, the intermediate stage current of 3μA, and the total current of 106μA as an example), when the load is 10pf, the slew rate of the traditional folded common source and common gate structure in the negative conversion stage is 0.724V / μs, and the slew rate of the positive conversion stage is 0.693V / μs; the slew rate of the circuit structure proposed in the present invention in the negative conversion stage is 9.745V / μs, and the slew rate of the positive conversion stage is 9.597V / μs; it can be seen that the slew rate in the negative conversion stage is increased by 13.460 times, and the slew rate in the positive conversion stage is increased by 13.848 times.

[0052] In addition, compared with the traditional folded cascode structure under normal circumstances (the traditional folded cascode structure has an input stage tail current of 100μA, an intermediate stage current of 65μA, and a total current of 230μA), when the load is 10pf, the slew rate of the traditional folded cascode structure in the negative conversion stage is 9.855V / μs, and the slew rate of the positive conversion stage is 9.548V / μs. The circuit structure proposed in the present invention reduces power consumption by 52.609% while achieving almost the same slew rate.

[0053] It can be seen that the present invention provides a low-power, high-slew rate folded common-source common-gate operational amplifier circuit, which can achieve a relatively high slew rate under relatively large input differential tail current and extremely small intermediate-stage quiescent current.

[0054] The above description is only a specific implementation mode of the present invention. Any feature disclosed in this specification, unless otherwise stated, can be replaced by other alternative features that are equivalent or have similar purposes; all the disclosed features, or all the steps in the methods or processes, except for mutually exclusive features and / or steps, can be combined in any way.

Claims

1. A low-power, high-slew-rate folded common-source common-gate operational amplifier circuit, comprising: Current sources I0-I4, transistors M1-M14, resistor R1, load capacitor CL; characterized in that: The gate of transistor M1 is connected to the non-inverting input terminal VIN+, and the gate of transistor M2 is connected to the inverting input terminal VIN-; the source of transistor M1 and the source of transistor M2 are connected, and the current source I0 is connected between the source of transistor M1 and the positive power rail; the drain of transistor M1, the drain of transistor M3, the source of transistor M5, and the source of transistor M6 are connected; The drain of transistor M2, the drain of transistor M4, the source of transistor M7, and the source of transistor M8 are connected, the source of transistor M3 and the source of transistor M4 are connected to the negative power rail, the gate of transistor M3, the gate of transistor M4, and the drain of transistor M8 are connected, and the current source I3 is connected between the drain of transistor M8 and the positive power rail; The gate of transistor M5, the gate of transistor M8, and the gate of transistor M9 are connected, the drain of transistor M9 is connected to the gate, the current source I1 is connected between the drain of transistor M9 and the positive power rail, and the resistor R1 is connected between the gate of transistor M9 and the negative power rail; the drain of transistor M5, the gate of transistor M10, the gate of transistor M11, the drain of transistor M12, and the gate of transistor M14 are connected; The gate of transistor M12, the gate of transistor M13, and the source of transistor M14 are connected, and the current source I4 is connected between the source of transistor M14 and the negative power rail; the source of transistor M10, the source of transistor M11, and the drain of transistor M14 are all connected to the positive power rail, the drain of transistor M10 and the source of transistor M12 are connected, and the drain of transistor M11 and the source of transistor M13 are connected; The gate of transistor M6, the gate of transistor M7, and the drain of transistor M6 are connected to the gate, and the current source I1 is connected between the gate of transistor M6 and the positive power rail; the drain of transistor M7 and the drain of transistor M13 are connected and connected to the output voltage terminal Vout, and the load capacitor CL is connected between the output voltage terminal Vout and the negative power rail.

2. The low-power, high-slew-rate folded cascode operational amplifier circuit according to claim 1, characterized in that: The transistor M4 , the transistor M7 , and the transistor M8 form a flip-over voltage follower differential structure (DFVF).

3. The low-power, high-slew-rate folded cascode structure operational amplifier circuit according to claim 1, characterized in that: The transistor M3 , the transistor M4 , and the transistor M8 constitute a flipped voltage follower current sensor (FVFCS).

4. The low-power, high-slew-rate folded cascode operational amplifier circuit according to claim 1, characterized in that: The transistor M14 and the current source I4 form a source follower.

5. The low-power, high-slew-rate folded cascode structure operational amplifier circuit according to claim 1, characterized in that: Current sources I0~I4 all use common-source and common-gate current sources.

6. The low-power, high-slew-rate folded cascode operational amplifier circuit according to claim 1, characterized in that: The transistors M1 to M14 are all metal oxide semiconductor field effect transistors.

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