Frequency dividing circuit
By introducing different delay modules into the frequency division circuit and using the conversion of port level values, the output error signal problem caused by the overlap of clock signals in the frequency division circuit is solved, and the effectiveness of signal delay output and the simplification of the circuit structure are achieved.
Patent Information
- Application Number
- CN202411562394.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-04
- Publication Date
- 2025-02-14
AI Technical Summary
The existing frequency division circuits are prone to output error signals when multiple clock signals overlap, and leak current is prone to occur at the overlap of clock signals, resulting in increased power consumption.
By introducing different delay modules into the frequency division circuit and delaying the output of other modules that have a connection relationship with themselves through the conversion of port level values, thereby avoiding output of wrong signals.
It effectively avoids the output error signal problem caused by the overlap of multiple output signals of the frequency division circuit, and simplifies the component structure inside the circuit and reduces the design cost.
Smart Images
Figure CN119448983A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure generally relates to the field of circuit design technology, and more particularly to a frequency division circuit. Background Art
[0002] In the prior art, as a circuit capable of reducing the frequency of an input signal, a frequency dividing circuit can usually achieve a frequency dividing effect using a timer or a counter. Specifically, the frequency of the output signal can be controlled by setting a timing time in a timer, or the frequency dividing ratio of the input signal can be determined by the number of counts of a counter.
[0003] However, when the duty cycles of multiple clock signals in the circuit are all 50% or the clock signals are four-phase clocks, multiple clock signals may change their logic states at the same time, which leads to the problem of clock signal overlap, causing the circuit to output an erroneous signal, and leakage current is easily generated at the overlap of the clock signals, thereby increasing the power consumption of the circuit. Based on this, a delay unit can be added at the overlap of the clock signals to solve the clock overlap problem, but this method easily leads to an increase in the area and power consumption of the circuit structure.
[0004] Therefore, the existing frequency division circuit still has the problem of clock signal overlap. Summary of the invention
[0005] In view of the above-mentioned defects or deficiencies in the prior art, it is desired to provide a frequency dividing circuit, in which different delay modules in the frequency dividing circuit can delay the output of signals of other modules connected to themselves by transforming the port level values, thereby avoiding the output of erroneous signals due to the overlap of multiple output signals of the frequency dividing circuit.
[0006] The circuit is as follows: According to one aspect of the present application, a frequency division circuit is provided, comprising: a signal input terminal, a first delay module, a second delay module and a third delay module, wherein the signal input terminal is respectively connected to the control input terminals of the first delay module, the second delay module and the third delay module, the data input terminal of the first delay module is connected to the negative output terminal of the second delay module, the positive output terminal of the first delay module is connected to the data input terminal of the second delay module, and the negative output terminal of the first delay module is connected to the data input terminal of the third delay module; A first delay module, configured to respond to a first level state of an output signal of the signal input terminal, set a level value of a positive output terminal of the first delay module to a level value of a negative output terminal of the second delay module, and output a first signal based on the level value of the positive output terminal of the first delay module; A second delay module, configured to respond to the first level state, set a level value of a positive output terminal of the second delay module based on a level value of a data input terminal of the first delay module and a level value of a positive output terminal of the first delay module, and output a second signal based on the level value of the positive output terminal of the second delay module; A third delay module is used to respond to the second level state of the output signal of the signal input terminal, determine the level value of the positive output terminal of the third delay module based on the level value of the negative output terminal of the first delay module, and output a third signal based on the level value of the positive output terminal of the third delay module; wherein the first level state is opposite to the second level state.
[0007] In addition, the frequency division circuit of the present application may also have the following additional technical features: Preferably, the first delay module includes: a first trigger; a control input terminal of the first trigger is connected to the signal input terminal, a data input terminal of the first trigger is connected to the negative output terminal of the second delay module, a positive output terminal of the first trigger is connected to the data input terminal of the second delay module, and a negative output terminal of the first trigger is connected to the data input terminal of the third delay module; The first trigger is used to set the level value of the positive output terminal of the first delay module to the level value of the negative output terminal of the second delay module in response to the first level state of the output signal of the signal input terminal, and output the first signal based on the level value of the positive output terminal of the first delay module.
[0008] Preferably, the first delay module further comprises: a first operator; the input end of the first operator is respectively connected to the positive output end of the first trigger and the positive output end of the third delay module; The first operator is used to determine the level value of the output end of the first operator based on the level value of the positive output end of the first trigger and the level value of the positive output end of the third delay module, and output a fourth signal based on the level value of the output end of the first operator.
[0009] Preferably, the first delay module further includes: a first inverter; an input end of the first inverter is connected to an output end of the first operator; The first inverter is used to determine the level value of the output terminal of the first inverter based on the level value of the output terminal of the first operator, and output the fifth signal based on the level value of the output terminal of the first inverter.
[0010] Preferably, the second delay module includes a second operator and a second trigger; the input end of the second operator is respectively connected to the data input end of the first delay module and the positive output end of the first delay module, and the output end of the second operator is connected to the data input end of the second trigger; the control input end of the second trigger is connected to the signal input end, and the negative output end of the second trigger is connected to the data input end of the first delay module; The second operator is used to determine the level value of the data input terminal of the second trigger based on the level value of the data input terminal of the first delay module and the level value of the positive output terminal of the first delay module; The second trigger is used to set the level value of the positive output terminal of the second trigger to the level value of the data input terminal of the second trigger in response to the first level state, and output a second signal based on the level value of the positive output terminal of the second trigger.
[0011] Preferably, the third delay module includes a second inverter, a third trigger and a third operator; the input end of the second reverse phase is connected to the signal input end, the output end of the second inverter is connected to the control input end of the third trigger, the data input end of the third trigger is connected to the negative output end of the first delay module, and the input end of the third operator is respectively connected to the negative output end of the first delay module and the positive output end of the third trigger; The second inverter is used for receiving a first level state of an output signal of the signal input terminal and inverting the first level state into a second level state; The third trigger is used to, in response to the second level state, set the level value of the positive output terminal of the third trigger to the level value of the negative output terminal of the first delay module; The third operator is used to determine the level value of the output terminal of the third operator based on the level value of the positive output terminal of the third trigger and the level value of the negative output terminal of the first delay module, and output a third signal based on the level value of the output terminal of the third operator.
[0012] Preferably, the frequency division circuit further includes a frequency multiplication module; the input end of the frequency multiplication module is connected to the signal input end, and the output end of the frequency multiplication module is respectively connected to the control input ends of the first delay module, the second delay module and the third delay module; The frequency doubling module is used to receive the output signal of the signal input end, and output the frequency doubling signal of the output signal of the signal input end to the first delay module, the second delay module and the third delay module respectively; wherein the ratio of the frequency of the frequency doubling signal to the frequency of the output signal of the signal input end is a preset integer.
[0013] Preferably, the frequency multiplication module includes a fourth operator, a delay sub-module and a fourth trigger; the input end of the fourth operator is respectively connected to the signal input end, the data input end of the fourth trigger and the negative output end of the fourth trigger, the output end of the fourth operator is connected to the input end of the delay sub-module, and the output end of the delay sub-module is respectively connected to the control input end of the fourth trigger, the first delay module, the second delay module and the third delay module.
[0014] Preferably, the delay submodule comprises N inverters connected in series, wherein N is an odd number greater than 1.
[0015] Preferably, when the frequency of the signal output from the signal input terminal is 50 MHz, the frequencies of the first signal, the second signal and the third signal are 16.667 MHz.
[0016] The frequency division circuit provided in the embodiment of the present application is based on the interconnection between the ports of different delay modules inside the circuit. On the one hand, it can enable each delay module to respond to the level state of the signal input terminal, and affect the signal delay output of other modules connected to itself by changing the level value of its own port, thereby avoiding the output of erroneous signals due to the overlap of multiple output signals of the frequency division circuit; on the other hand, it can simplify the device structure inside the circuit, thereby solving the signal overlap problem in the existing frequency division circuit while reducing the design cost of the frequency division circuit.
[0017] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings: Figure 1 A schematic diagram of a frequency division circuit provided in an embodiment of the present application; Figure 2 Another schematic diagram of a frequency division circuit provided in an embodiment of the present application; Figure 3 Another schematic diagram of a frequency division circuit provided in an embodiment of the present application; Figure 4 Another schematic diagram of a frequency division circuit provided in an embodiment of the present application; Figure 5 Another schematic diagram of a frequency division circuit provided in an embodiment of the present application; Figure 6 Another schematic diagram of a frequency division circuit provided in an embodiment of the present application; Figure 7 Another schematic diagram of a frequency division circuit provided in an embodiment of the present application; Figure 8 Another schematic diagram of a frequency division circuit provided in an embodiment of the present application; Fig. 9 A waveform diagram of a 3 / 2 frequency-divided output signal provided in an embodiment of the present application; Fig.10 Another schematic diagram of a frequency division circuit provided in an embodiment of the present application; Fig.11 A waveform diagram of a three-frequency output signal provided in an embodiment of the present application. DETAILED DESCRIPTION
[0019] The present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the relevant invention, rather than to limit the invention. It is also necessary to explain that, for ease of description, only the parts related to the invention are shown in the accompanying drawings.
[0020] It should be noted that, in the absence of conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments. In addition, the term "and / or" herein is merely a description of the association relationship of associated objects, indicating that three relationships may exist, for example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The terms "first" and "second" in the description and claims of the embodiments of the present application are used to distinguish different objects, rather than to describe a specific order of objects.
[0021] First, the terms involved in this application are explained as follows: (1) Duty cycle: refers to the ratio of the high level duration in a pulse signal to the entire cycle time.
[0022] In the prior art, as a circuit capable of reducing the frequency of an input signal, a frequency dividing circuit can usually achieve a frequency dividing effect using a timer or a counter. Specifically, the frequency of the output signal can be controlled by setting a timing time in a timer, or the frequency dividing ratio of the input signal can be determined by the number of counts of a counter.
[0023] However, when the duty cycles of multiple clock signals inside the circuit are all 50% or the clock signals are four-phase clocks, multiple clock signals may change their logic states at the same time, which leads to overlapping clock signals, causing the circuit to output erroneous signals, and leakage current is easily generated at the overlapping points of the clock signals, thereby increasing the power consumption of the circuit.
[0024] To address the above problem, delay units can be added at the overlapping points of the clock signals to solve the clock overlap problem. However, this method requires adding a delay unit in each clock cycle, which increases the area and power consumption of the circuit structure. In addition, since the phase difference between different clocks is in a changing state, the delay time of the output clock signal is difficult to control.
[0025] Therefore, the existing frequency division circuit still has the problem of clock signal overlap.
[0026] Based on this, the present application proposes a frequency division circuit, in which different delay modules in the frequency division circuit can delay the output of signals of other modules connected to the frequency division circuit by changing the port level values, thereby avoiding the output of erroneous signals due to the overlap of multiple output signals of the frequency division circuit.
[0027] Figure 1 is a schematic diagram of a frequency division circuit provided in an embodiment of the present application, such as Figure 1 As shown, the circuit includes: a signal input terminal 101, a first delay module 102, a second delay module 103 and a third delay module 104, the signal input terminal 101 is respectively connected to the control input terminals of the first delay module 102, the second delay module 103 and the third delay module 104, the data input terminal of the first delay module 102 is connected to the negative output terminal of the second delay module 103, the positive output terminal of the first delay module 102 is connected to the data input terminal of the second delay module 103, and the negative output terminal of the first delay module 102 is connected to the data input terminal of the third delay module 104.
[0028] Specifically, the first delay module 102 is used to respond to the first level state of the output signal of the signal input terminal 101, set the level value of the positive output terminal of the first delay module 102 to the level value of the negative output terminal of the second delay module 103, and output the first signal based on the level value of the positive output terminal of the first delay module 102; the second delay module 103 is used to respond to the first level state, set the level value of the positive output terminal of the second delay module 103 based on the level value of the data input terminal of the first delay module 102 and the level value of the positive output terminal of the first delay module 102, and output the second signal based on the level value of the positive output terminal of the second delay module 103; the third delay module 104 is used to respond to the second level state of the output signal of the signal input terminal 101, determine the level value of the positive output terminal of the third delay module 104 based on the level value of the negative output terminal of the first delay module 102, and output the third signal based on the level value of the positive output terminal of the third delay module 104; wherein the first level state is opposite to the second level state.
[0029] In an embodiment of the present application, based on the connection state between the signal input terminal 101 in the frequency division circuit and the control input terminals of different delay modules, the level value of the output terminal of each delay module can be changed according to the different level states of the output signal of the signal input terminal 101, so that there is a difference in the duration of the high level in the output signal of each delay module output terminal, and then the output terminals of different delay modules can generate clock signals with different duty cycles based on different level values.
[0030] Exemplarily, the first level state of the output signal of the signal input terminal 101 can be a state in which the output signal changes from a low level to a high level (i.e., a rising edge in the corresponding signal output waveform); the second level state of the output signal of the signal input terminal 101 can be a state in which the output signal changes from a high level to a low level (i.e., a falling edge in the corresponding signal output waveform).
[0031] In a possible implementation, the control input of each delay module can be used to control the latching of data in each module. Specifically, the latching of data in the delay module can be achieved by outputting the data of the data input of the delay module from the positive output of the delay module.
[0032] Exemplarily, in response to a specific level state of the output signal of the signal input terminal 101, the control input terminal of each delay module can set the level value of the module's positive output terminal to the level value of the module's data input terminal.
[0033] Exemplarily, the duty cycle of the signal output by the signal input terminal 101 may be, for example, 50%.
[0034] The frequency division circuit provided in the embodiment of the present application is based on the interconnection between the ports of different delay modules inside the circuit. On the one hand, it can enable each delay module to respond to the level state of the signal input terminal, and affect the signal delay output of other modules connected to itself by changing the level value of its own port, thereby avoiding the output of erroneous signals due to the overlap of multiple output signals of the frequency division circuit; on the other hand, it can simplify the device structure inside the circuit, thereby solving the signal overlap problem in the existing frequency division circuit while reducing the design cost of the frequency division circuit.
[0035] In another embodiment of the present application, the specific structure of the first delay module 102 is also introduced. Figure 2 is another schematic diagram of the frequency division circuit provided in the embodiment of the present application, such as Figure 2 As shown, the first delay module 102 specifically includes a first trigger 1021; wherein, the control input terminal of the first trigger 1021 is connected to the signal input terminal 101, the data input terminal of the first trigger 1021 is connected to the negative output terminal of the second delay module 103, the positive output terminal of the first trigger 1021 is connected to the data input terminal of the second delay module 103, and the negative output terminal of the first trigger 1021 is connected to the data input terminal of the third delay module 104.
[0036] Specifically, the first trigger 1021 is used to set the level value of the positive output terminal of the first delay module 102 to the level value of the negative output terminal of the second delay module 103 in response to the first level state of the output signal of the signal input terminal 101, and output the first signal based on the level value of the positive output terminal of the first delay module 102.
[0037] Exemplarily, when the first delay module 102 includes a first trigger 1021, the control input terminal of the first delay module 102 can be a clock signal input terminal for controlling data storage in the first trigger 1021, the data input terminal of the first delay module 102 can be an input terminal for storing data in the first trigger 1021, the positive output terminal of the first delay module 102 can be an output terminal for storing data in the first trigger 1021, and the negative output terminal of the first delay module 102 can be a non-output terminal of the output terminal for storing data in the first trigger 1021; wherein, the control input terminal, data input terminal, positive output terminal and negative output terminal of the first delay module 102 can be respectively represented as CLK terminal, D terminal, Q terminal and Q' terminal.
[0038] Specifically, the CLK terminal of the first trigger 1021 can set the level value of the Q terminal to the level value of the D terminal in response to the state in which the output signal of the signal input terminal 101 changes from a low level to a high level. In the above-mentioned first trigger 1021, the D terminal is connected to the negative output terminal of the second delay module 103, so the first trigger 1021 can set the level value of the Q terminal to the level value of the negative output terminal of the second delay module 103.
[0039] It should be noted that the first flip-flop 1021 can be a data flip-flop (Data Flip-Flop, referred to as D flip-flop), and the data output by its negative output terminal can be the inverse data of the data output by its positive output terminal, that is, the Q' terminal level value of the first flip-flop 1021 can be the inverse level value of the Q terminal level value.
[0040] In another embodiment of the present application, the specific structure of the second delay module 103 is also introduced. Figure 3 is another schematic diagram of the frequency division circuit provided in the embodiment of the present application, such as Figure 3 As shown, the second delay module 103 specifically includes a second operator 1031 and a second trigger 1032; the input end of the second operator 1031 is respectively connected to the data input end of the first delay module 102 and the positive output end of the first delay module 102, and the output end of the second operator 1031 is connected to the data input end of the second trigger 1032; the control input end of the second trigger 1032 is connected to the signal input end 101, and the negative output end of the second trigger 1032 is connected to the data input end of the first delay module 102.
[0041] Specifically, the second operator 1031 is used to determine the level value of the data input terminal of the second trigger 1032 based on the level value of the data input terminal of the first delay module 102 and the level value of the positive output terminal of the first delay module 102; the second trigger 1032 is used to set the level value of the positive output terminal of the second trigger 1032 to the level value of the data input terminal of the second trigger 1032 in response to the first level state, and output a second signal based on the level value of the positive output terminal of the second trigger 1032.
[0042] Exemplarily, similar to the first flip-flop 1021 , the control input terminal, data input terminal, positive output terminal and negative output terminal of the second flip-flop 1032 may also be represented by the CLK terminal, D terminal, Q terminal and Q′ terminal.
[0043] Exemplarily, when the first delay module 102 includes a first trigger 1021, the second operator 1031 can determine the D-end level value of the second trigger 1032 based on the D-end level value of the first trigger 1021 and the Q-end level value of the first trigger 1021; wherein the second operator 1031 can, for example, be an AND operator (i.e., an AND operator).
[0044] Based on this, the second operator 1031 can set the level value of its own Q end to the level value of its own D end determined by the second operator 1031 in response to the state where the output signal of the signal input terminal 101 changes from a low level to a high level, and output a second signal based on the level value of the Q end.
[0045] In another embodiment of the present application, the specific structure of the third delay module 104 is also introduced. Figure 4 is another schematic diagram of the frequency division circuit provided in the embodiment of the present application, such as Figure 4 As shown, the third delay module 104 specifically includes a second inverter 1041, a third trigger 1042 and a third operator 1043; the input end of the second reverse phase 1041 is connected to the signal input end 101, the output end of the second inverter 1041 is connected to the control input end of the third trigger 1042, the data input end of the third trigger 1042 is connected to the negative output end of the first delay module 102, and the input end of the third operator 1043 is respectively connected to the negative output end of the first delay module 102 and the positive output end of the third trigger 1042.
[0046] Specifically, the second inverter 1041 is used to receive the first level state of the output signal of the signal input terminal 101, and invert the first level state to a second level state; the third trigger 1042 is used to set the level value of the positive output terminal of the third trigger 1042 to the level value of the negative output terminal of the first delay module 102 in response to the second level state; the third operator 1043 is used to determine the level value of the output terminal of the third operator 1043 based on the level value of the positive output terminal of the third trigger 1042 and the level value of the negative output terminal of the first delay module 102, and output a third signal based on the level value of the output terminal of the third operator 1043.
[0047] Exemplarily, similar to the first flip-flop 1021 and the second flip-flop 1032 , the control input terminal, data input terminal, positive output terminal and negative output terminal of the third flip-flop 1042 can also be represented by the CLK terminal, D terminal, Q terminal and Q′ terminal.
[0048] Exemplarily, when the first delay module 102 includes the first trigger 1021 , in response to the state where the output signal of the signal input terminal 101 changes from a high level to a low level, the third trigger 1042 sets the level value of its Q terminal to the level value of the Q′ terminal of the first trigger 1021 .
[0049] It should be noted that since the Q' terminal of the first trigger 1021 and the D terminal of the third trigger 1042 are of equal potential, when the third trigger 1042 outputs its own D terminal level value from its own Q terminal in response to the second level state, it actually outputs the Q' terminal level value of the first trigger 1021.
[0050] Exemplarily, when the first delay module 102 includes a first trigger 1021, the third operator 1043 can determine the level value of its own output terminal based on the level value of the Q' terminal of the first trigger 1021 and the level value of the Q terminal of the third trigger 1042, and output a third signal based on the level value of its own output terminal; wherein the third operator 1043 can be, for example, an OR operator (i.e., an OR operator).
[0051] In another embodiment of the present application, a process for generating different output signals of the frequency division circuit is also provided. Figure 4 The frequency dividing circuit shown takes the signal duty cycle of the signal output from the signal input terminal 101 as 50% and the frequency as 50 MHz as an example. When the first delay module 102 includes a first trigger 1021, the second delay module 103 is composed of a second operator 1031 and a second trigger 1032, and the third delay module 104 is composed of a second inverter 1041, a third trigger 1042 and a third operator 1043, the generation process of the first signal, the second signal and the third signal output by the frequency dividing circuit is specifically described as follows.
[0052] First, the reset terminal Reset in the first trigger 1021, the second trigger 1032 and the third trigger 1042 can be used to set the Q terminal of each trigger to a low level and the Q' terminal to a high level, that is, the level value of the Q terminal in the first trigger 1021, the second trigger 1032 and the third trigger 1042 is 0, and the level value of the Q' terminal is 1.
[0053] Based on this, the initial level value of the D terminal of the first trigger 1021 is 1, and the initial level value of the D terminal of the second trigger 1032 is 0.
[0054] When the output signal of the signal input terminal 101 is in the first level state for the first time (that is, when the output signal reaches the first rising edge from the initial state of 0), the first trigger 1021 and the second trigger 1032 respond to the first level state, and respectively set the level value of the Q terminal to the level value of the D terminal at the previous moment, that is, the first trigger 1021 sets the level value of the Q terminal to 1, and the second trigger 1032 sets the level value of the Q terminal to 0. At this time, the level values of the Q' terminal of the first trigger 1021 and the second trigger 1032 are 0 and 1 respectively.
[0055] Before the output signal of the signal input terminal 101 reaches the second first level state (i.e., before the output signal reaches the second rising edge), the D-terminal level value of the first trigger 1021 is set to 1 by the Q'-terminal level value of the second trigger 1032, and the D-terminal level value of the second trigger 1032 is set to 1.
[0056] When the output signal of the signal input terminal 101 is in the second first level state (that is, when the output signal reaches the second rising edge), the first trigger 1021 and the second trigger 1032 respond to the first level state, and respectively set the level value of the Q terminal to the level value of the D terminal at the previous moment, that is, the first trigger 1021 sets the level value of the Q terminal to 1, and the second trigger 1032 sets the level value of the Q terminal to 1. At this time, the level values of the Q' terminal of the first trigger 1021 and the second trigger 1032 are 0 and 0 respectively.
[0057] Before the output signal of the signal input terminal 101 reaches the first level state for the third time (i.e., before the output signal reaches the third rising edge), the D-terminal level value of the first trigger 1021 is set to 0 by the Q'-terminal level value of the second trigger 1032, and the D-terminal level value of the second trigger 1032 is set to 0.
[0058] When the output signal of the signal input terminal 101 is in the first level state for the third time (that is, when the output signal reaches the third rising edge), the first trigger 1021 and the second trigger 1032 respond to the first level state, and respectively set the level value of the Q terminal to the level value of the D terminal at the previous moment, that is, the first trigger 1021 sets the level value of the Q terminal to 0, and the second trigger 1032 sets the level value of the Q terminal to 0. At this time, the level values of the Q' terminal of the first trigger 1021 and the second trigger 1032 are 1 and 1 respectively.
[0059] Before the output signal of the signal input terminal 101 is in the first level state for the fourth time (i.e., before the output signal reaches the fourth rising edge), the level value of the D terminal of the first trigger 1021 is set to 1 by the level value of the Q' terminal of the second trigger 1032, and the level value of the D terminal of the second trigger 1032 is set to 0; wherein, before the output signal reaches the fourth rising edge, the level values of the ports of the first trigger 1021 and the second trigger 1032 are restored to the initial set values.
[0060] It can be known that, after every three cycles of the output signal of the signal input terminal 101 with a frequency of 50 MHz, the Q terminal of the first trigger 1021 first experiences a high level of two cycles of the output signal, and then experiences a low level of one cycle of the output signal; and the Q terminal of the second trigger 1032 first experiences a low level of one cycle of the output signal, and then experiences a high level of one cycle of the output signal, and finally experiences a low level of one cycle of the output signal; then when the signal input terminal 101 continues to output the signal, the Q terminals of the first trigger 1021 and the second trigger 1032 both repeat the above-mentioned level change state.
[0061] Based on this, the duty cycle of the first signal outputted from the Q terminal of the first trigger 1021 is specifically 8 / 12; and the duty cycle of the second signal outputted from the Q terminal of the second trigger 1032 is 4 / 12.
[0062] Secondly, when the Q end of the first trigger 1021 first experiences a high level for the length of two output signal cycles and then experiences a low level for the length of one output signal cycle, the Q' end of the first trigger 1021 first experiences a low level for the length of two output signal cycles and then experiences a high level for the length of one output signal cycle, and then the Q' end repeats the above level change state.
[0063] Based on this, when the output signal of the signal input terminal 101 is in the second level state for the first time (that is, when the output signal reaches the first falling edge from the initial state of 0), the third trigger 1042 responds to the second level state and sets the level value of the Q terminal to the level value of the Q' terminal of the first trigger 1021, that is, the third trigger 1042 sets the level value of the Q terminal to 0.
[0064] When the output signal of the signal input terminal 101 is in the second level state for the second time (that is, when the output signal reaches the second falling edge), the third trigger 1042 sets the level value of the Q terminal to the level value of the Q' terminal of the first trigger 1021 in response to the second level state, that is, the third trigger 1042 sets the level value of the Q terminal to 0.
[0065] When the output signal of the signal input terminal 101 is in the second level state for the third time (that is, when the output signal reaches the third falling edge), the third trigger 1042 sets the level value of the Q terminal to the level value of the Q' terminal of the first trigger 1021 in response to the second level state, that is, the third trigger 1042 sets the level value of the Q terminal to 1.
[0066] When the output signal of the signal input terminal 101 is in the second level state for the fourth time (i.e., when the output signal reaches the fourth falling edge), the third trigger 1042 sets the level value of the Q terminal to the level value of the Q' terminal of the first trigger 1021 in response to the second level state, that is, the third trigger 1042 sets the level value of the Q terminal to 0.
[0067] It can be known that after every three cycles of the output signal of the signal input terminal 101 with a frequency of 50 MHz, the Q terminal of the third trigger 1042 first experiences a low level of two cycles of the output signal, and then experiences a high level of one cycle of the output signal.
[0068] Based on this, when the third operator 1043 uses the Q-end level value of the third trigger 1042 and the Q'-end level value of the first trigger 1021 to determine the level value of its own output terminal, when the output signal of the signal input terminal 101 is between the first and third first level states (that is, when the output signal is between the first rising edge and the third rising edge), the Q-end level value of the third trigger 1042 and the Q'-end level value of the first trigger 1021 are both 0, and therefore, the level value of the output terminal of the third operator 1043 is also 0 in this stage.
[0069] When the output signal of the signal input terminal 101 is between the third first level state and the third second level state (that is, when the output signal is between the third rising edge and the third falling edge), the level value of the Q end of the third trigger 1042 is 0, and the level value of the Q' end of the first trigger 1021 is 1. Therefore, the level value of the output end of the third operator 1043 is 1 in this stage.
[0070] When the output signal of the signal input terminal 101 is between the third second level state and the fourth first level state (that is, when the output signal is between the third falling edge and the fourth rising edge), the level value of the Q end of the third trigger 1042 is 1, and the level value of the Q' end of the first trigger 1021 is 1, therefore, the level value of the output end of the third operator 1043 is also 1 in this stage.
[0071] When the output signal of the signal input terminal 101 is between the fourth first level state and the fourth second level state (that is, when the output signal is between the fourth rising edge and the fourth falling edge), the level value of the Q end of the third trigger 1042 is 1, and the level value of the Q' end of the first trigger 1021 is 0. Therefore, the level value of the output end of the third operator 1043 is also 1 in this stage.
[0072] When the output signal of the signal input terminal 101 is in the fourth second level state (that is, when the output signal reaches the fourth falling edge), the level value of the Q' terminal of the first trigger 1021 is 0, and the third trigger 1042 sets the level value of its own Q terminal to 0 in response to the second level state. Therefore, the level value of the output terminal of the third operator 1043 is 0.
[0073] It can be known that after every three rising edge cycles of the output signal of the signal input terminal 101 with a frequency of 50 MHz, the output terminal of the third operator 1043 first experiences a low level with a length of 1.5 cycles of the output signal, and then experiences a high level with a length of 1.5 cycles of the output signal; then when the signal input terminal 101 continues to output the signal, the output terminal of the third operator 1043 repeats the above level change state.
[0074] Based on this, the duty cycle of the third signal outputted from the output terminal of the third operator 1043 is 6 / 12.
[0075] Exemplarily, when the frequency of the signal output from the signal input terminal 101 is 50 MHz, the frequencies of the first signal, the second signal and the third signal are 16.667 MHz.
[0076] In the embodiment of the present application, the signal overlap problem in the existing frequency division circuit can be solved by adjusting the duty cycle of the output signal of the frequency division circuit, and the frequency division processing of the circuit input signal can be realized at the same time.
[0077] In another embodiment of the present application, other configurations of the first delay module 102 are also introduced. Exemplarily, the first delay module 102 further includes a first operator 1022; the input end of the first operator 1022 is respectively connected to the positive output end of the first trigger 1021 and the positive output end of the third delay module 104.
[0078] Specifically, the first operator 1022 is used to determine the level value of the output end of the first operator 1022 based on the level value of the positive output end of the first trigger 1021 and the level value of the positive output end of the third delay module 104, and output a fourth signal based on the level value of the output end of the first operator 1022.
[0079] For example, Figure 5 is another schematic diagram of the frequency division circuit provided in the embodiment of the present application, such as Figure 5 As shown, when the third delay module 104 includes the third operator 1043 , the input terminal of the first operator 1022 can be connected to the Q terminal of the first flip-flop 1021 and the Q terminal of the third operator 1043 , respectively.
[0080] Specifically, the first operator 1022 can determine the level value of its own output terminal based on the Q-terminal level value of the first trigger 1021 and the Q-terminal level value of the third operator 1043, and output the fourth signal based on the level value; wherein the first operator 1022 can be, for example, an OR operator (i.e., an OR operator).
[0081] By way of example, taking the signal duty cycle of the signal output from the signal input terminal 101 as 50% and the frequency as 50 MHz, when the first delay module 102 is composed of a first trigger 1021 and a first operator 1022, the second delay module 103 is composed of a second operator 1031 and a second trigger 1032, and the third delay module 104 is composed of a second inverter 1041, a third trigger 1042 and a third operator 1043, the generation process of the fourth signal is specifically described as follows.
[0082] First, when the output signal of the signal input terminal 101 with a frequency of 50 MHz goes through three cycles every time, it can be found that: the Q terminal of the first trigger 1021 first experiences a high level of two cycles of the output signal, and then experiences a low level of one cycle of the output signal; the Q terminal of the third trigger 1042 first experiences a high level of 0.5 cycles of the output signal, and then experiences a low level of 2 cycles of the output signal, and finally experiences a high level of 0.5 cycles of the output signal.
[0083] Based on this, the level value of the output terminal of the first operator 1022 first experiences a high level of 2 output signal cycle lengths, then experiences a low level of 0.5 output signal cycle lengths, and finally experiences a low level of 0.5 output signal cycle lengths; then when the signal input terminal 101 continues to output a signal, the output terminal of the first operator 1022 repeats the above level change state. That is, the duty cycle of the fourth signal output by the output terminal of the first operator 1022 is specifically 10 / 12.
[0084] Exemplarily, when the frequency of the signal output from the signal input terminal 101 is 50 MHz, the frequency of the fourth signal is also 16.667 MHz.
[0085] In another embodiment of the present application, other configurations of the first delay module 102 are also introduced. For example, Figure 6 is another schematic diagram of the frequency division circuit provided in the embodiment of the present application, such as Figure 6 As shown, the first delay module 102 further includes a first inverter 1023 ; an input end of the first inverter 1023 is connected to an output end of the first operator 1022 .
[0086] Specifically, the first inverter 1023 is used to determine the level value of the output terminal of the first inverter 1023 based on the level value of the output terminal of the first operator 1022 , and output the fifth signal based on the level value of the output terminal of the first inverter 1023 .
[0087] Exemplarily, taking the case where the duty cycle of the signal output from the signal input terminal 101 is 50%, when the duty cycle of the fourth signal output from the output terminal of the first operator 1022 is 10 / 12, the duty cycle of the fifth signal output from the output terminal of the first inverter 1023 is 2 / 12.
[0088] For example, when the frequency of the signal output from the signal input terminal 101 is 50 MHz, the frequency of the fifth signal is also 16.667 MHz.
[0089] In another embodiment of the present application, other configurations of the frequency division circuit are also introduced. For example, Figure 7 is another schematic diagram of the frequency division circuit provided in the embodiment of the present application, such as Figure 7 As shown, the frequency division circuit also includes a frequency multiplication module 105; the input end of the frequency multiplication module 105 is connected to the signal input end 101, and the output end of the frequency multiplication module 105 is connected to the control input ends of the first delay module 102, the second delay module 103 and the third delay module 104 respectively.
[0090] Specifically, the frequency doubling module 105 is used to receive the output signal of the signal input terminal 101, and output the frequency doubling signal of the output signal of the signal input terminal 101 to the first delay module 102, the second delay module 103 and the third delay module 104 respectively; wherein the ratio of the frequency of the frequency doubling signal to the frequency of the output signal of the signal input terminal 101 is a preset integer.
[0091] In the embodiment of the present application, before using the frequency division circuit to perform frequency division processing on the signal output from the signal input terminal 101, the frequency multiplication signal of the output signal can be first obtained through the above-mentioned frequency multiplication module 105, so as to obtain the fractional frequency division result of the output signal of the signal input terminal 101 after the frequency division action of the frequency division circuit.
[0092] In a possible implementation, the frequency multiplication module 105 may include a fourth operator 1051 , a delay submodule 1052 , and a fourth trigger 1053 .
[0093] For example, Figure 8 is another schematic diagram of the frequency division circuit provided in the embodiment of the present application, such as Figure 8 As shown, the input end of the fourth operator 1051 is respectively connected to the signal input end 101, the data input end of the fourth trigger 1053 and the negative output end of the fourth trigger 1053, the output end of the fourth operator 1051 is connected to the input end of the delay submodule 1052, and the output end of the delay submodule 1052 is respectively connected to the control input end of the fourth trigger 1053, the first delay module 102, the second delay module 103 and the third delay module 104; wherein the fourth operator 1051 can be an exclusive OR operator (i.e., an XOR operator).
[0094] Specifically, the delay submodule 1052 may include N inverters connected in series, where N is an odd number greater than 1; based on this, the delay submodule 1052 may also be referred to as an inverter odd-numbered series sequence (INV_ODD_SEQ).
[0095] For example, after a square wave signal of a specific frequency is input to the delay submodule 1052, the delay submodule 1052 can output an output signal whose delay relative to the input square wave signal is one quarter of the period of the square wave signal, thereby achieving a double frequency effect of the frequency multiplication module 105 on the output signal of the signal input terminal 101, that is, the double frequency signal of the output signal of the signal input terminal 101 can be obtained through the frequency multiplication module 105. Based on this, Figure 8 The signal output by the frequency dividing circuit shown may be a 3 / 2 frequency divided signal of the signal output by the signal input terminal 101 .
[0096] In the specific implementation, taking the signal duty cycle of the signal output from the signal input terminal 101 as 50% and the frequency as 50 MHz as an example, first, the reset terminal Reset in the fourth trigger 1053 can be used to set the Q terminal of the fourth trigger 1053 to a low level and the Q' terminal to a high level, that is, the level value of the Q terminal in the fourth trigger 1053 is 0, and the level value of the Q' terminal is 1.
[0097] Based on the initial state of the input signal of the frequency multiplication module 105 being 0 (i.e., the initial output signal of the signal input terminal 101 is 0), the initial level value of the output terminal of the fourth operator 1051 is 1, the initial level value of the output terminal of the delay submodule 1052 is 0, and the initial level value of the D terminal of the fourth trigger 1053 is 1.
[0098] When the input signal of the frequency multiplication module 105 is in the first level state for the first time (i.e., when the input signal reaches the first rising edge from the initial state of 0), the level values of the two input terminals of the fourth operator 1051 are both 1, and the output terminal of the fourth operator 1051 is set to 0; after a delay of half the high level duration in the unit cycle of the input signal, the level value of the output terminal of the delay submodule 1052 is set to 1, and the CLK terminal of the fourth trigger 1053 jumps to 1, thereby forming the first level state (i.e., rising edge); the fourth trigger In response to the first level state, the level value of its own Q terminal is set to 1, and the level value of the Q' terminal is set to 0. At this time, the level value of the input terminal of the frequency multiplication module 105 is still 1; based on this, the level value of the output terminal of the fourth operator 1051 is set to 1, and then after a delay of half the high level duration in the unit cycle of the input signal, the CLK terminal of the fourth trigger 1053 jumps to 0. At this time, the input signal at the input terminal of the frequency multiplication module 105 is the first second level state (that is, the input signal reaches the first falling edge).
[0099] When the input signal of the input end of the frequency multiplication module 105 reaches the first falling edge, the level values of the two input ends of the fourth operator 1051 are both 0, and the output end of the fourth operator 1051 is set to 0; after a delay of half the duration of the high level in the unit cycle of the input signal, the level value of the output end of the delay submodule 1052 is set to 1, and the CLK end of the fourth trigger 1053 jumps to 1, thereby forming a first level state (i.e., a rising edge); in response to the first level state, the fourth trigger 1053 The level value of its own Q terminal is set to 0, and the level value of the Q' terminal is set to 1. At this time, the level value of the input terminal of the frequency multiplication module 105 is still 0; based on this, the level value of the output terminal of the fourth operator 1051 is set to 1, and then after a delay of half of the high level duration in the unit cycle of the input signal, the CLK terminal of the fourth trigger 1053 jumps to 0. At this time, the input signal at the input terminal of the frequency multiplication module 105 is the second first level state (that is, the input signal reaches the next rising edge), and the above level change process is repeated. Based on this, the frequency multiplication module 105 realizes a double frequency with a duty cycle of half for the input signal at the input terminal.
[0100] Exemplary, reference Figure 8 When the frequency multiplication module 105 is a double frequency multiplication module, the first signal, the second signal, the third signal, the fourth signal and the fifth signal generated by the circuit are 3 / 2 frequency division signals with duty ratios of 8 / 12, 4 / 12, 6 / 12, 10 / 12 and 2 / 12 respectively.
[0101] For example, Fig. 9 3 / 2 frequency division output signal waveform diagram provided in the embodiment of the present application, such as Fig. 9As shown, when the output signal of the signal input terminal 101 is a signal with a duty cycle of 50% and a frequency of 50 MHz, waveform a can be used to represent the waveform diagram of the output signal of the signal input terminal 101, waveform b can be used to represent the waveform diagram of the fifth signal with a duty cycle of 2 / 12 and a 3 / 2 division, waveform c can be used to represent the waveform diagram of the second signal with a duty cycle of 4 / 12 and a 3 / 2 division, and waveform d can be used to represent the waveform diagram of the third signal with a duty cycle of 6 / 12 and a 3 / 2 division.
[0102] Compared with the prior art in which an equivalent fractional frequency division result is obtained by performing multiple integer frequency divisions with different proportions in a unit time, the embodiment of the present application can achieve a fractional frequency division effect on the input signal based on a frequency division circuit including a frequency doubling module 105, thereby improving the accuracy of the signal frequency division effect and avoiding the problem of large jitter in the output signal.
[0103] In another embodiment of the present application, another form of the frequency division circuit is introduced. For example, Fig.10 is another schematic diagram of the frequency division circuit provided in the embodiment of the present application, such as Fig.10 As shown, the frequency division circuit may include a signal input terminal 101 , a 3-frequency division output module 901 , a 1.5-frequency division output module 902 , and an extended output module 903 .
[0104] Exemplarily, the 3-frequency division output module 901 may be as follows: Figure 5 The integer frequency division circuit shown, namely the 3-division frequency output module 901, can be used to output 5 kinds of 3-division frequency signals with different duty cycles.
[0105] Specifically, B can correspond to the output end of the first inverter 1023 in the integer frequency division circuit, D can correspond to the positive output end of the second trigger 1032 in the integer frequency division circuit; F can correspond to the output end of the third operator 1043 in the integer frequency division circuit; D' can correspond to the positive output end of the first trigger 1021 in the integer frequency division circuit; B' can correspond to the output end of the first operator 1022 in the integer frequency division circuit.
[0106] For example, the 1.5-division output module 902 may be: Figure 7 The fractional frequency division circuit shown, namely, the 1.5 frequency division output module 902 can be used to output five 3 / 2 frequency division signals with different duty cycles.
[0107] Specifically, b can correspond to the output end of the first inverter 1023 in the fractional frequency division circuit; d can correspond to the positive output end of the second trigger 1032 in the fractional frequency division circuit; f can correspond to the output end of the third operator 1043 in the fractional frequency division circuit; d' can correspond to the positive output end of the first trigger 1021 in the fractional frequency division circuit; b' can correspond to the output end of the first operator 1022 in the fractional frequency division circuit.
[0108] It should be noted that the above-mentioned ports B and port b, port D and port d, port F and port f, port D' and port d', port B' and port b' correspond to each other, and specifically, the duty ratios of the output signals of the two corresponding ports are the same.
[0109] In a possible implementation, the duty cycle of the output signal of the frequency division circuit may be expanded based on the connection status of different ports of the expansion output module 903 and the 3-division output module 901 and / or the 1.5-division output module 902 .
[0110] Exemplarily, the extended output module 903 may include at least one operator. Fig.10 The extended output module 903 may include a third inverter 9031, an AND operator 9032, an AND operator 9033, an OR operator 9034, an OR operator 9035, and a three-input AND operator 9036.
[0111] Exemplarily, the input end of the AND operator 9032 is connected to the output end F of the 3-frequency division output module 901 and the output end b of the 1.5-frequency division output module 902 respectively.
[0112] Specifically, the AND operator 9032 is used to determine the level value of its own output terminal A based on the level value of the output terminal F and the level value of the output terminal b, and output the sixth signal based on the level value of the output terminal A.
[0113] Exemplarily, the input terminal of the third inverter 9031 is connected to the output terminal D of the 3-frequency division output module 901; the first input terminal of the three-input AND operator 9036 is connected to the output terminal of the third inverter 9031, the second input terminal of the three-input AND operator 9036 is connected to the output terminal F of the 3-frequency division output module 901, the second input terminal of the three-input AND operator 9036 is connected to the output terminal F of the 3-frequency division output module 901, and the third input terminal of the three-input AND operator 9036 is connected to the output terminal f of the 1.5-frequency division output module 902.
[0114] Specifically, the third inverter 9031 is used to determine the level value of its own output terminal based on the level value of the output terminal D, and input the level value of its own output terminal to the three-input AND operator 9036; the three-input AND operator 9036 is used to determine the level value of its own output terminal C based on the level value of the output terminal of the third inverter 9031, the level value of the output terminal F and the level value of the output terminal f, and output the seventh signal based on the level value of the output terminal C.
[0115] Exemplarily, the input end of the NOR operator 9034 is respectively connected to the output end D' of the 3-frequency division output module 901 and the output end C of the three-input AND operator 9036; the input end of the OR operator 9035 is respectively connected to the output end of the NOR operator 9034 and the output end D of the 3-frequency division output module 901; the input end of the AND operator 9033 is respectively connected to the output end of the OR operator 9035 and the output end b' of the 1.5-frequency division output module 902.
[0116] Specifically, the AND operator 9033 is used to determine the level value of its own output terminal E based on the level value of the output terminal of the OR operator 9035 and the level value of the output terminal b′, and output the eighth signal based on the level value of the output terminal E.
[0117] Exemplarily, when the output signals of the signal input terminals 101 of the 3-frequency division output module 901 and the 1.5-frequency division output module 902 are both 50 MHz of 3 cycles, the output terminal F of the 3-frequency division output module 901 first experiences a high level of 1.5 cycles of the output signal, then experiences a low level of 1.5 cycles of the output signal, and finally experiences a low level of 1 cycle of the output signal; the output terminal b of the 1.5-frequency division output module 902 first experiences a low level of 0.25 cycles of the output signal, then experiences a high level of 0.25 cycles of the output signal, then experiences a low level of 1.25 cycles of the output signal, then experiences a high level of 0.25 cycles of the output signal, and finally experiences a low level of 1 cycle of the output signal.
[0118] Based on this, Fig.11 is a waveform diagram of a three-frequency output signal provided in an embodiment of the present application, such as Fig.11 As shown, waveform a can be used to represent the waveform diagram of the output signal of the signal input terminal 101, and reference Fig.11As shown in waveform b, the output terminal of the AND operator 9032 first experiences a low level of 0.25 cycle length of the output signal, then experiences a high level of 0.25 cycle length of the output signal, and finally experiences a low level of 1.5 cycle length of the output signal; then when the signal input terminal 101 continues to output a signal, the output terminal of the AND operator 9032 repeats the above level change state. That is, the output terminal A of the AND operator 9032 outputs a three-frequency sixth signal with a duty cycle of 1 / 12.
[0119] Exemplarily, when the output signals of the signal input terminals 101 of the 3-way frequency division output module 901 and the 1.5-way frequency division output module 902 are both 50 MHz with 3 cycles, the output terminal D of the 3-way frequency division output module 901 first experiences a low level with a length of 2 cycles of the output signal, and then experiences a high level with a length of 1 cycle of the output signal; based on this, the output terminal of the third inverter 9031 first experiences a high level with a length of 2 cycles of the output signal, and then experiences a low level with a length of 1 cycle of the output signal.
[0120] Secondly, the output terminal F of the 3-frequency division output module 901 first experiences a high level of 1.5 output signal cycle lengths, then experiences a low level of 1.5 output signal cycle lengths, and finally experiences a low level of 1 output signal cycle length; the output terminal f of the 1.5-frequency division output module 902 first experiences a low level of 0.25 output signal cycle lengths, then experiences a high level of 0.75 output signal cycle lengths, then experiences a low level of 0.75 output signal cycle lengths, then experiences a high level of 0.75 output signal cycle lengths, and finally experiences a low level of 0.5 output signal cycle lengths; based on this, reference Fig.11 As shown in the waveform d, the output terminal C of the three-input AND operator 9036 first experiences a low level of 0.25 of the cycle length of the output signal, then experiences a high level of 0.75 of the cycle length of the output signal, and finally experiences a low level of 2 cycles of the output signal; then, when the signal input terminal 101 continues to output a signal, the output terminal of the three-input AND operator 9036 repeats the above level change state. That is, the output terminal C of the three-input AND operator 9036 outputs the third-frequency seventh signal with a duty cycle of 3 / 12.
[0121] Exemplarily, when the output signals of the signal input terminals 101 of the 3-frequency division output module 901 and the 1.5-frequency division output module 902 are both 50 MHz with 3 cycles, the output terminal C of the three-input AND operator 9036 first experiences a low level with a length of 0.25 cycles of the output signal, then experiences a high level with a length of 0.75 cycles of the output signal, and finally experiences a low level with a length of 2 cycles of the output signal; the output terminal D' of the 3-frequency division output module 901 first experiences a low level with a length of 1 cycle of the output signal, then experiences a high level with a length of 2 cycles of the output signal; based on this, the output terminal of the OR operator 9034 first experiences a high level with a length of 0.25 cycles of the output signal, and then experiences a low level with a length of 2.75 cycles of the output signal.
[0122] Secondly, the output terminal D of the 3-division output module 901 first experiences a low level of 2 output signal cycle lengths, and then experiences a high level of 1 output signal cycle length; based on this, the output terminal of the OR operator 9035 first experiences a high level of 0.25 output signal cycle lengths, and then experiences a low level of 1.75 output signal cycle lengths, and finally experiences a high level of 1 output signal cycle length.
[0123] In addition, the output terminal b of the 1.5-frequency division output module 902 first experiences a high level of 0.25 of the cycle length of the output signal, then experiences a low level of 0.25 of the cycle length of the output signal, then experiences a high level of 1.25 of the cycle length of the output signal, then experiences a high level of 0.25 of the cycle length of the output signal, and finally experiences a high level of 1 cycle length of the output signal; based on this, refer to Fig.11 As shown in the waveform f, the output terminal of the AND operator 9033 first experiences a high level of 0.25 cycle length of the output signal, then experiences a low level of 1.75 cycle length of the output signal, and finally experiences a low level of 1 cycle length of the output signal; then when the signal input terminal 101 continues to output the signal, the output terminal of the AND operator 9033 repeats the above level change state. That is, the output terminal E of the AND operator 9033 outputs a three-frequency eighth signal with a duty cycle of 5 / 12.
[0124] It should be noted that if Fig.11 As shown, waveform c can be used to represent the fifth signal output from the output end of the first inverter 1023, that is, it can be used to represent a 2 / 12 3-divided frequency signal; waveform e can be used to represent the second signal output from the Q end of the second trigger 1032, that is, it can be used to represent a 4 / 12 3-divided frequency signal; waveform g can be used to represent the third signal output from the output end of the third operator 1043, that is, it can be used to represent a 6 / 12 3-divided frequency signal.
[0125] In the embodiment of the present application, by combining and connecting different computing devices inside the circuit, the duty cycle of the circuit output signal can be expanded, thereby reducing the circuit design cost and expanding the application scope of the frequency division circuit.
[0126] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with (but not limited to) technical features with similar functions disclosed in the present application.
Claims
1. A frequency division circuit, characterized in that: It includes a signal input terminal, a first delay module, a second delay module and a third delay module, wherein the signal input terminal is connected to the control input terminals of the first delay module, the second delay module and the third delay module respectively, the data input terminal of the first delay module is connected to the negative output terminal of the second delay module, the positive output terminal of the first delay module is connected to the data input terminal of the second delay module, and the negative output terminal of the first delay module is connected to the data input terminal of the third delay module; The first delay module is used to, in response to a first level state of the output signal of the signal input terminal, set the level value of the positive output terminal of the first delay module to the level value of the negative output terminal of the second delay module, and output a first signal based on the level value of the positive output terminal of the first delay module; The second delay module is used for, in response to the first level state, setting the level value of the positive output terminal of the second delay module based on the level value of the data input terminal of the first delay module and the level value of the positive output terminal of the first delay module, and outputting a second signal based on the level value of the positive output terminal of the second delay module; The third delay module is used to, in response to the second level state of the output signal of the signal input terminal, determine the level value of the positive output terminal of the third delay module based on the level value of the negative output terminal of the first delay module, and output a third signal based on the level value of the positive output terminal of the third delay module; wherein the first level state is opposite to the second level state.
2. The frequency division circuit according to claim 1, characterized in that: The first delay module comprises: a first trigger; a control input terminal of the first trigger is connected to the signal input terminal, a data input terminal of the first trigger is connected to a negative output terminal of the second delay module, a positive output terminal of the first trigger is connected to a data input terminal of the second delay module, and a negative output terminal of the first trigger is connected to a data input terminal of the third delay module; The first trigger is used to set the level value of the positive output end of the first delay module to the level value of the negative output end of the second delay module in response to the first level state of the output signal of the signal input end, and output a first signal based on the level value of the positive output end of the first delay module.
3. The frequency division circuit according to claim 2, characterized in that: The first delay module further includes: a first operator; the input end of the first operator is respectively connected to the positive output end of the first trigger and the positive output end of the third delay module; The first operator is used to determine the level value of the output end of the first operator based on the level value of the positive output end of the first trigger and the level value of the positive output end of the third delay module, and output a fourth signal based on the level value of the output end of the first operator.
4. The frequency division circuit according to claim 3, characterized in that: The first delay module further includes: a first inverter; an input end of the first inverter is connected to an output end of the first operator; The first inverter is used to determine the level value of the output terminal of the first inverter based on the level value of the output terminal of the first operator, and output a fifth signal based on the level value of the output terminal of the first inverter.
5. The frequency division circuit according to claim 1, characterized in that: The second delay module includes a second operator and a second trigger; the input end of the second operator is respectively connected to the data input end of the first delay module and the positive output end of the first delay module, and the output end of the second operator is connected to the data input end of the second trigger; the control input end of the second trigger is connected to the signal input end, and the negative output end of the second trigger is connected to the data input end of the first delay module; The second operator is used to determine the level value of the data input terminal of the second trigger based on the level value of the data input terminal of the first delay module and the level value of the positive output terminal of the first delay module; The second trigger is used to set the level value of the positive output terminal of the second trigger to the level value of the data input terminal of the second trigger in response to the first level state, and output a second signal based on the level value of the positive output terminal of the second trigger.
6. The frequency division circuit according to claim 1, characterized in that: The third delay module includes a second inverter, a third trigger and a third operator; the input end of the second inverting phase is connected to the signal input end, the output end of the second inverter is connected to the control input end of the third trigger, the data input end of the third trigger is connected to the negative output end of the first delay module, and the input end of the third operator is respectively connected to the negative output end of the first delay module and the positive output end of the third trigger; The second inverter is used for receiving a first level state of the output signal of the signal input terminal, and inverting the first level state to the second level state; The third trigger is used for, in response to the second level state, setting the level value of the positive output terminal of the third trigger to the level value of the negative output terminal of the first delay module; The third operator is used to determine the level value of the output end of the third operator based on the level value of the positive output end of the third trigger and the level value of the negative output end of the first delay module, and output the third signal based on the level value of the output end of the third operator.
7. The frequency division circuit according to claim 1, characterized in that: The frequency division circuit further includes a frequency multiplication module; the input end of the frequency multiplication module is connected to the signal input end, and the output end of the frequency multiplication module is respectively connected to the control input ends of the first delay module, the second delay module and the third delay module; The frequency doubling module is used to receive the output signal of the signal input end, and output a frequency doubling signal of the output signal of the signal input end to the first delay module, the second delay module and the third delay module respectively; wherein the ratio of the frequency of the frequency doubling signal to the frequency of the output signal of the signal input end is a preset integer.
8. The frequency division circuit according to claim 7, characterized in that: The frequency multiplication module includes a fourth operator, a delay submodule and a fourth trigger; the input end of the fourth operator is respectively connected to the signal input end, the data input end of the fourth trigger and the negative output end of the fourth trigger, the output end of the fourth operator is connected to the input end of the delay submodule, and the output end of the delay submodule is respectively connected to the control input end of the fourth trigger, the first delay module, the second delay module and the third delay module.
9. The frequency division circuit according to claim 8, characterized in that: The delay submodule includes N inverters connected in series, wherein N is an odd number greater than 1.
10. The frequency division circuit according to claim 1, characterized in that: When the frequency of the signal output from the signal input terminal is 50 MHz, the frequencies of the first signal, the second signal and the third signal are 16.667 MHz.