Micro light-emitting diode chip and preparation method thereof

Abstract

The invention relates to a micro light-emitting diode chip and a preparation method thereof. The preparation method comprises the following steps: providing an epitaxial wafer; forming a current expansion film on the surface of the epitaxial wafer; forming a first light resistance pattern on the surface, deviating from the epitaxial wafer, of the current expansion film, wherein the first light resistance pattern exposes the periphery of the current expansion film; and etching the current expansion film and the epitaxial wafer by taking the first photoresist pattern as a mask to remove the part, which is not covered by the first photoresist pattern, of the current expansion film so as to form a current expansion layer, a first photoresist pattern is formed on the epitaxial wafer, a part, which is adjacent to the current expansion film and is not covered by the first photoresist pattern, of the epitaxial wafer is removed so as to form a step structure on the epitaxial wafer, the side edge of the current expansion layer is shrunk inwards relative to the step structure, and the shrunk size W0 meets the condition that W0 is more than 0.5 mu m and less than or equal to 4 mu m.

Description

Technical Field

[0001] The present application relates to the field of optical elements, and in particular to a micro light emitting diode chip and a preparation method thereof. Background Art

[0002] With the development of technology, light-emitting diode chips have been used more and more widely. Light-emitting diode chips are widely used in electronic devices such as mobile phones and tablets. Micro LED chips are expected to become a new development direction due to their advantages such as self-luminescence and low power consumption. However, the luminous efficiency of micro LEDs in related technologies needs to be improved. Summary of the invention

[0003] In a first aspect, the present application provides a method for preparing a micro light emitting diode chip, the method comprising:

[0004] Providing epitaxial wafers;

[0005] forming a current spreading film on a surface of the epitaxial wafer;

[0006] forming a first photoresist pattern on a surface of the current spreading film away from the epitaxial wafer, wherein the first photoresist pattern exposes a periphery of the current spreading film; and

[0007] The current spreading film and the epitaxial wafer are etched using the first photoresist pattern as a mask to remove a portion of the current spreading film not covered by the first photoresist pattern to form a current spreading layer, and a portion of the epitaxial wafer adjacent to the current spreading film and not covered by the first photoresist pattern is removed to form a step structure on the epitaxial wafer, wherein the current spreading layer is indented compared to a side of the step structure, and a size W0 of the indentation satisfies: 0.5 μm<W0≤4 μm.

[0008] In a second aspect, an embodiment of the present application provides a micro light emitting diode chip, the micro light emitting diode chip comprising:

[0009] An epitaxial wafer, the epitaxial wafer comprising a substrate and an N-type layer, an active layer, an electron blocking layer and a P-type layer stacked in sequence on the substrate;

[0010] The chip comprises a step structure, and the step structure comprises a side wall and a bottom wall connected by bending;

[0011] A current spreading layer, wherein the current spreading layer is disposed on a surface of the P-type layer away from the substrate, and the current spreading layer is inwardly contracted compared to a side of the step structure, and a size W0 of the inward contraction satisfies: 0.5 μm<W0≤4 μm;

[0012] A passivation layer, the passivation layer is disposed on the surface and the peripheral side of the current spreading layer, and is disposed on the sidewall and the bottom wall of the step structure, the passivation layer has a first through hole and a second through hole, wherein the first through hole exposes a portion of the current spreading layer, and the second through hole exposes a portion of the bottom wall of the step structure;

[0013] A first electrode, the first electrode is disposed in the first through hole; and

[0014] A second electrode is disposed in the second through hole.

[0015] In summary, in the method for preparing a micro-LED chip provided in the embodiment of the present application, the first photoresist pattern serves as an etching mask (also called an etching mask) of the current spreading film, and also serves as an etching mask of the epitaxial wafer. It can be seen that the method for preparing a micro-LED chip provided in the embodiment of the present application can use the first photoresist pattern as both a mask for the current spreading film and a mask for forming the step structure in the same preparation process, which can reduce the number of photolithography steps and thus reduce the preparation cost of the micro-LED chip. In addition, the current spreading layer of the micro-LED chip provided in the embodiment of the present application is inwardly shrunk compared to the side of the step structure, and the inwardly shrunk dimension W0 satisfies: 0.5μm<W0≤4μm. On the one hand, it can reduce the number of holes transmitted to the active layer through the side wall of the step structure, improve the current injection efficiency and thus improve the luminescence efficiency; on the other hand, it can also make the effective luminescence area of ​​the micro-LED chip larger. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the implementation will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 A flow chart of a method for preparing a micro light-emitting diode chip provided in one embodiment of the present application;

[0018] Figure 2 A schematic structural diagram of a micro light emitting diode chip provided in one embodiment;

[0019] Figure 3 for Figure 1 The flowchart included in S400 in the method for preparing a micro light emitting diode chip shown in ;

[0020] Figure 4 for Figure 3The flowchart included in S410 of the method for preparing a micro light emitting diode chip shown in ;

[0021] Figure 5 for Figure 3 The flowchart included in S420 in the method for preparing a micro light emitting diode chip shown in ;

[0022] Figure 6 for Figure 1 The flowchart included in S200 of one embodiment of the method for preparing a micro light emitting diode chip shown in ;

[0023] Figure 7 for Figure 1 A flowchart including S400 in another embodiment of the method for preparing a micro light emitting diode chip shown in ;

[0024] Figure 8 A flow chart of a method for preparing a micro light-emitting diode chip provided in another embodiment of the present application;

[0025] Fig. 9 for Figure 1 The flowchart included in S200 of another embodiment of the method for preparing a micro light emitting diode chip shown in ;

[0026] Fig.10 for Figure 1 In another embodiment of the method for preparing a micro light emitting diode chip shown in , S400 includes a flowchart;

[0027] Fig.11 A flow chart of a method for preparing a micro light emitting diode chip provided in yet another embodiment of the present application;

[0028] Fig.12 This is a flow chart included in S400 in the micro light emitting diode chip provided in one embodiment of the present application;

[0029] Fig.13 A flowchart included in S400 in a micro light emitting diode chip provided in another embodiment of the present application;

[0030] Fig.14 A schematic diagram of the steps included in a method for preparing a micro light-emitting diode chip provided in another embodiment of the present application;

[0031] Fig.15 A schematic diagram of the structures corresponding to each step of a method for preparing a micro-LED chip provided in an embodiment

[0032] Fig.16 A schematic structural diagram corresponding to each step in a method for preparing a light emitting diode provided in another embodiment;

[0033] Fig.17 for Fig.14 A schematic structural diagram corresponding to each step in the method for preparing a light-emitting diode provided in;

[0034] Fig.18 A schematic diagram of the structure of a micro light emitting diode chip provided in one embodiment of the present application;

[0035] Fig.19 for Fig.18 A schematic diagram showing some details of the micro-LED chip shown in FIG.

[0036] Fig. 20 for Fig.18 A schematic diagram of the thickness of the current spreading layer provided in one embodiment;

[0037] Fig.21 A schematic diagram of a partial structure of a micro light emitting diode chip provided in one embodiment.

[0038] Description of main numbers in the accompanying drawings:

[0039] Micro light emitting diode chip 1, epitaxial wafer 10, current spreading film 20a, current spreading layer 20, passivation layer 30;

[0040] Substrate 110, N-type layer 120, active layer 130, electron blocking layer 140, P-type layer 150;

[0041] Step structure 10b, side wall 10c, bottom wall 10d, side edge 10e;

[0042] A first sub-expansion film 210 a and a second sub-expansion film 210 b ;

[0043] A first sub-passivation film 310, a second sub-passivation film 320, a first through hole 30a, and a second through hole 30b;

[0044] A first electrode 410, a second electrode 420;

[0045] A first photoresist pattern 520 , a second photoresist pattern 540 , a first through hole 541 , and a second through hole 542 . DETAILED DESCRIPTION

[0046] The technical solution of the present application will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the embodiments described in the present application are only a part of the embodiments, not all of the embodiments. Based on the embodiments provided in the present application, all other embodiments obtained by ordinary technicians in this field without creative work belong to the protection scope of the present application.

[0047] Reference to "embodiments" in this application means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it mutually exclusive, independent, or alternative to other embodiments. It can be explicitly and implicitly understood by those skilled in the art that the embodiments described in this application can be combined with other embodiments.

[0048] The terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example: a component or device including one or more parts is not limited to the one or more parts listed, but optionally includes one or more parts that are not listed but inherent to the exemplified product, or one or more parts that it should have based on the described function.

[0049] See also Figure 1 , Figure 2 and Fig.15 , Figure 1 A flow chart of a method for preparing a micro light-emitting diode chip provided in one embodiment of the present application; Figure 2 A schematic structural diagram of a micro light emitting diode chip provided in one embodiment; Fig.15 The schematic diagram of the structure corresponding to each step of the preparation method of a micro light emitting diode chip provided in one embodiment. The preparation method includes S100, S200, S300 and S400. Next, S100, S200, S300 and S400 are introduced.

[0050] S100 , providing an epitaxial wafer 10 .

[0051] The micro LED chip 1 is also called a Micro LED chip. The size of a conventional LED chip is usually large, for example, the width of a conventional LED chip is usually two to three hundred microns. However, the size of the micro LED chip 1 provided in the embodiment of the present application is smaller, and the width of the micro LED chip 1 is smaller, usually tens of microns or less.

[0052] The micro LED chip 1 is used to emit light. The light emitted by the micro LED chip 1 may be, but is not limited to, blue light, green light, red light, ultraviolet (UV), and the like.

[0053] In this implementation, see Fig.15In (a), the epitaxial wafer 10 includes a substrate 110, an N-type layer 120, an active layer 130, an electron blocking layer 140 and a P-type layer 150 which are stacked in sequence.

[0054] In another embodiment, the epitaxial wafer 10 includes a substrate 110, a nucleation layer, an N-type layer 120, an active layer 130, an electron blocking layer 140, and a P-type layer 150 stacked in sequence. In other words, the epitaxial wafer 10 also includes a nucleation layer located between the substrate 110 and the N-type layer 120. The nucleation layer is used to improve the lattice matching between the substrate 110 and the N-type layer 120.

[0055] In another embodiment, the epitaxial wafer 10 includes a substrate 110, a buffer layer, an N-type layer 120, an active layer 130, an electron blocking layer 140, and a P-type layer 150 stacked in sequence. In other words, the epitaxial wafer 10 also includes a buffer layer located between the substrate 110 and the N-type layer 120. The buffer layer is used to better form the N-type layer 120 on the substrate 110.

[0056] The material of the substrate 110 may be, but is not limited to, sapphire, silicon, silicon carbide, gallium nitride (GaN), etc. The material of the substrate 110 in the currently industrialized micro-LED chip 1 is mainly sapphire, because compared with silicon, the lattice mismatch between sapphire and the N-type layer 120 (GaN) is relatively small, while the silicon carbide substrate 110 and the GaN substrate 110 are very expensive and are generally not suitable for mass production of MicroLED or LED.

[0057] In one embodiment, the material of the N-type layer 120 may be, but is not limited to, n-GaN. The n-GaN refers to a GaN layer doped with other impurities such as Si. In other words, the n-GaN refers to a GaN layer doped with Si. For example, the doping concentration of Si may be, but is not limited to, M*10 18 , wherein 1≤M≤8, and M is a positive integer. The N-type layer 120 can form an ohmic contact with the second electrode 420 (negative electrode, such as Cr / Au material) in the micro LED chip 1 .

[0058] In another embodiment, the N-type layer 120 includes a multi-layer superlattice structure of alternately stacked AlGaN and GaN.

[0059] The active layer 130 is also referred to as a multi-quantum well light emitting layer (MQWs). When electrons and holes are transferred to the active layer 130, the electrons and holes are recombined in the active layer 130 to emit light.

[0060] In one embodiment, the active layer 130 includes a plurality of alternately stacked InGaN layers and GaN layers.

[0061] The electron blocking layer 140 is used to block the electrons of the active layer 130 from moving toward the P-type layer 150 .

[0062] The P-type layer 150 may be, but is not limited to, GaN:Mg. That is, a GaN film layer doped with Mg. For example, the doping concentration of Mg may be, but is not limited to, K*10 17 , where 1≤K≤5, and K is a positive integer.

[0063] S200 , forming a current spreading film 20 a on the surface of the epitaxial wafer 10 .

[0064] For the structure corresponding to S200, please refer to Fig.15 In (b), the current spreading layer 20 may be, but is not limited to, a conductive thin layer such as ITO, Ni, NiAu, or Ag. The current spreading layer 20 will be described in detail later.

[0065] Specifically, in this embodiment, the current spreading film 20 a is formed on the surface of the epitaxial wafer 10 by forming the current spreading film 20 a on the surface of the P-type layer 150 away from the substrate 110 .

[0066] In one embodiment, since the doping concentration in the P-type layer 150 is low and the hole mobility in the P-type layer 150 is low, forming the current spreading film 20a on the surface of the P-type layer 150 can not only improve the ohmic contact between the first electrode 410 and the P-type layer 150, but also make the injected current more easily spread to the surface of the entire P-type layer 150.

[0067] S300 , forming a first photoresist pattern 520 on a surface of the current spreading film 20 a away from the epitaxial wafer 10 , wherein the first photoresist pattern 520 exposes a periphery of the current spreading film 20 a .

[0068] For the corresponding structure of S300, please refer to Fig.15 In (c), specifically, in one embodiment, a first photoresist layer is formed on a surface of the current spreading film 20 a away from the epitaxial wafer 10 , and the first photoresist layer covers the entire surface of the current spreading film 20 a away from the epitaxial wafer 10 .

[0069] The first photoresist layer is patterned, and the peripheral portion of the first photoresist layer is removed to form a first photoresist pattern 520. Specifically, the first photoresist pattern 520 is formed by photolithography and development.

[0070] In this embodiment, the first photoresist layer is a positive photoresist, and accordingly, the first photoresist pattern 520 is also a positive photoresist.

[0071] S400, etching the current spreading film 20a and the epitaxial wafer 10 using the first photoresist pattern 520 as a mask to remove a portion of the current spreading film 20a not covered by the first photoresist pattern 520 to form a current spreading layer 20, and removing a portion of the epitaxial wafer 10 adjacent to the current spreading film 20a and not covered by the first photoresist pattern 520 to form a step structure 10b on the epitaxial wafer 10, wherein the current spreading layer 20 is inwardly shrunk compared to a side 10e of the step structure 10b, and a shrunk dimension W0 satisfies: 0.5μm<W0≤4μm.

[0072] Please refer to the structure of S400 Fig.15 In (d) of FIG. 1 , the step structure 10b includes a side wall 10c and a bottom wall 10d connected by bending. The bottom wall 10d is formed at a portion of the N-type layer 120 away from the substrate 110. The step structure 10b will be described in detail later in conjunction with the specific structure of the micro LED chip 1 .

[0073] The current spreading film 20a and the epitaxial wafer 10 are etched using the first photoresist pattern 520 as a mask. In other words, the first photoresist pattern 520 serves as an etching mask for the current spreading film 20a and also as an etching mask for the epitaxial wafer 10. It can be seen that the method for preparing the micro-LED chip 1 provided in the embodiment of the present application can use the first photoresist pattern 520 as both a mask for the current spreading film 20a and a mask for forming the step structure 10b in the same preparation process, and also as an etching mask for causing the current spreading film 20a to shrink, which can reduce the number of photolithography steps and further reduce the preparation cost of the micro-LED chip 1.

[0074] In this embodiment, the inward dimension W0 may be, but is not limited to, 0.5 μm, 1.0 μm, 1.5 μm, 2.0 μm, 2.5 μm, 3.0 μm, 3.5 μm, or 4.0 μm. In other words, in this embodiment, W0 may be 2.0 μm or about 2.0 μm.

[0075] Generally speaking, during the preparation process of the micro-LED chip 1, the side wall 10c of the step structure 10b may have defects. If electrons and holes are transmitted to the active layer 130 via the side wall 10c of the step structure 10b, non-radiative recombination will occur, thereby generating heat, and light that can be emitted from the light-emitting surface of the micro-LED chip 1 cannot be generated. When the current spreading layer 20 is smaller than the side 10e of the step structure 10b, there will still be more holes transmitted to the active layer 130 via the side wall 10c of the step structure 10b, and the electrons transmitted to the active layer 130 will recombine to generate non-radiative recombination, thereby generating heat, resulting in low luminous efficiency. When the current spreading layer 20 is larger than the side 10e of the step structure 10b, the effective light-emitting area of ​​the micro-LED chip 1 is smaller. The current spreading layer 20 of the micro-LED chip 1 provided in the embodiment of the present application is retracted compared to the side 10e of the step structure 10b, and the retracted size W0 satisfies: 0.5μm<W0≤4μm. On the one hand, it can reduce the holes transmitted to the active layer 130 through the side wall 10c of the step structure 10b, improve the current injection efficiency and thus improve the luminous efficiency; on the other hand, it can also make the effective luminous area of ​​the micro-LED chip 1 larger.

[0076] In summary, in the method for preparing the micro-LED chip 1 provided in the embodiment of the present application, the first photoresist pattern 520 is used as an etching mask (also called an etching mask) for the current spreading film 20a, and is also used as an etching mask for the epitaxial wafer 10. It can be seen that the method for preparing the micro-LED chip 1 provided in the embodiment of the present application can use the first photoresist pattern 520 as both a mask for the current spreading film 20a and a mask for forming the step structure 10b in the same preparation process, which can reduce the photolithography steps and thus reduce the preparation cost of the micro-LED chip 1. In addition, the current spreading layer 20 of the micro-LED chip 1 provided in the embodiment of the present application is inwardly shrunk compared to the side 10e of the step structure 10b, and the inwardly shrunk size W0 satisfies: 0.5μm<W0≤4μm. On the one hand, it can reduce the number of holes transmitted to the active layer 130 through the side wall 10c of the step structure 10b, improve the current injection efficiency and thus improve the luminous efficiency; on the other hand, it can also make the effective luminous area of ​​the micro-LED chip 1 larger.

[0077] For further information, see Figure 3 , Figure 3 for Figure 1The flowchart of S400 in the method for preparing a micro-LED chip is shown in FIG. In one embodiment, the S400, using the first photoresist pattern 520 as a mask to etch the current spreading film 20a and the epitaxial wafer 10, specifically includes S410 and S420. S410 and S420 are described in detail as follows.

[0078] S410 , using the first photoresist pattern 520 as a mask, performing a first plasma etching on the current spreading film 20 a and the epitaxial wafer 10 , wherein the power of the first plasma etching is a first power, so as to form an original step structure.

[0079] S420, using the first photoresist pattern 520 as a mask, performing a second plasma etching on the original step structure to form the step structure 10b, wherein the power of the second plasma etching is a second power, and the second power is less than the first power.

[0080] In this embodiment, the current spreading film 20a and the epitaxial wafer 10 are subjected to a first plasma etching, wherein the power of the first plasma etching is a first power, and the first power is greater than the subsequent second power, so that the original step structure can be etched out relatively quickly, thereby saving time for preparing the micro-LED chip 1, which is conducive to reducing costs.

[0081] Furthermore, after the first plasma etching, the original step structure is subjected to a second plasma etching, and the power of the second plasma etching is a second power, which is less than the first power. Therefore, the damage to the side wall 10c and the step bottom wall 10d forming the step structure 10b can be reduced.

[0082] Specifically, during the plasma etching process, lattice damage will occur to the surface without photoresist protection. Generally speaking, the higher the power used, the greater the damage. This is mainly because during plasma etching, the surface of the chip to be prepared will be bombarded with plasma, so that the arrangement of the atoms on the surface and subsurface layer of the bombarded chip to be prepared will be disordered to varying degrees, causing the chemical ratio of the surface of the chip to be prepared (also called the etching surface) to deviate from the normal value. It is usually manifested as defects such as replacement atoms, interstitial atoms, or atomic vacancies on the surface of the chip to be prepared that is bombarded by plasma (also called the etching surface) and within a certain distance range from the surface. A small part of these defects is electrically neutral, and most of them are in a charged state. For example, the Ga vacancy formed on the etching surface of the chip to be prepared plays the main acceptor role, In vacancies and Al vacancies are also acceptors, Ga interstitials are donors, and N vacancies also play the role of donors. The surface defects of the etched surface in these charged states form non-radiative recombination centers, thereby causing the side leakage of the prepared micro-light-emitting diode chip 1. In particular, N vacancies are the main cause of the side leakage of the micro LED chip 1 due to their high concentration.

[0083] In addition, during the plasma etching process, the surface of the chip to be prepared that is bombarded by plasma (also called the etching surface) will break the chemical bonds between some atoms on the etching surface of the chip to be prepared, and other heterogeneous atoms in the etching reaction chamber can be injected into the lattice of the etching surface. In addition, the reaction products and polymers of plasma etching will also adhere to the surface of the chip to be prepared. For example, the complex of In atom InCl3 has a volatilization temperature of about 140°C, and some of it will remain on the etching surface.

[0084] Furthermore, in one embodiment, the chemical composition of the surface of the chip to be prepared (also referred to as the etching surface) mentioned above deviates from the normal value and is also manifested in the absence of N atoms, forming Al and Ga enriched areas on the surface.

[0085] In addition, the surface of the chip to be prepared (also called etching surface) may also be contaminated by metal ions, for example, mainly C contamination.

[0086] In summary, in the process of preparing the micro LED chip 1 by plasma etching (also known as ICP dry etching), the sidewalls of the formed original step structure may be damaged. The main reasons are as follows.

[0087] First, when the first photoresist pattern 520 is used as a mask and the first plasma etching is performed on the current spreading film 20a and the epitaxial wafer 10, various defects will be generated. Specifically, the lattice atoms near the etching surface will be misaligned, and the surface atomic ratio will deviate from the chemical ratio, thereby generating various charge centers, which are called non-radiative recombination centers. If these defects are not eliminated, the side wall 10c of the micro-LED chip 1 produced will cause leakage. This is also the main reason for the leakage of the side wall 10c of the micro-LED chip 1 in the related art. In this embodiment, the etching surface is the wall surface of the side wall 10c and the bottom wall 10d of the original step structure.

[0088] Second, when the first photoresist pattern 520 is used as a mask to perform the first plasma etching on the current spreading film 20a and the epitaxial wafer 10, the surface deposits formed during the etching process or the contamination caused by the normal cleaning equipment are mostly non-conductive, and only a small part participates in the conduction. If these are not eliminated, the side wall 10c of the micro-LED chip 1 produced will leak. This is also the secondary reason for the leakage of the side wall 10c of the micro-LED chip 1 in the related art. Among them, the surface deposits during the etching process can be but are not limited to polymers, oxides and metal particles.

[0089] Therefore, during the first plasma etching process, the current spreading film 20a and the surface of the epitaxial wafer 10 that is not protected by the first photoresist pattern 520 will be damaged in crystal lattice. Since the power of the first plasma etching is the first power, the first power is greater than the second power, that is, the first power is relatively large, therefore, although the speed of forming the original step structure of the micro-LED chip 1 is fast, sidewall damage will be caused.

[0090] Furthermore, in the preparation method of the micro-LED chip 1 provided in the embodiment of the present application, the first photoresist pattern 520 is used as a mask to perform a second plasma etching on the original step structure to form the step structure 10b, wherein the power of the second plasma etching is a second power, and the second power is less than the first power, thereby reducing the side wall damage of the formed step structure 10b.

[0091] For example, the first plasma etching causes damage to the current spreading film 20a and the epitaxial wafer 10 at a depth of micrometer level. In other words, the original step structure obtained after the first plasma etching has damage at a depth of micrometer level (for example, 1μm to 5μm). The damage in the step structure 10b formed after the second plasma etching is at a nanometer level (for example, 10nm to 50nm). It can be seen that the preparation method of the micro-LED chip 1 provided in the embodiment of the present application can reduce the damage of the step structure 10b close to the side wall of the active area in the micro-LED chip 1. In other words, after the first plasma etching, the original step structure obtained has a first damage layer; after the second plasma etching, the step structure 10b obtained has a second damage layer, wherein the thickness of the second damage layer is much smaller than the thickness of the first damage layer. Wherein, the thickness of the first damage layer is 1μm to 5μm, and the thickness of the second damage layer is 10nm to 50nm.

[0092] In the related art, in order to form the step structure, usually only one plasma (ICP) etching is used to form the step structure. However, in the related art, the step structure is formed by one plasma etching, which will make the thickness of the damaged layer in the step structure larger, for example, several microns. In addition, if a less damaging corrosion is used in the first plasma etching, the preparation process of the micro light emitting diode chip 1 is longer.

[0093] In the preparation method of the micro-LED chip 1 provided in the embodiment of the present application, the current spreading film 20a and the epitaxial wafer 10 are firstly subjected to a first plasma etching using a first power to form an original step structure, and then the original step structure is subjected to a second plasma etching using a second power, and the second power is less than the first power, so that the side wall damage of the step structure 10b close to the active area can be reduced. The side wall damage of the step structure 10b formed after the second plasma etching in the active area is small (for example, 10nm to 50nm), and it is easier to etch away the side wall damage layer in the step structure 10b in the subsequent chemical treatment process. It can be understood that the recombination of electrons and holes on the side wall of the active area plays a major role in the non-radiative recombination.

[0094] In one embodiment, the method for preparing the micro-LED chip 1 provided in the embodiment of the present application can remove the second damaged layer of the step structure 10b in the micro-LED chip 1, which will be described in detail later. It can be understood that in other embodiments, the second damaged layer of the step structure 10b in the micro-LED chip 1 may not be removed.

[0095] In summary, the preparation method of the micro-LED chip 1 provided in the embodiment of the present application first uses a first power to perform a first plasma rapid etching on the current spreading film 20a and the epitaxial wafer 10 to form an original step structure, and then uses a second power to perform a second plasma etching on the original step structure. The second power is less than the first power, and therefore, the side wall damage of the step structure 10b can be reduced.

[0096] See also Figure 4 , Figure 4 for Figure 3 The flowchart of S410 in the method for preparing a micro-LED chip is shown in FIG. The S410, using the first photoresist pattern 520 as a mask, performs a first plasma etching on the current spreading film 20a and the epitaxial wafer 10, including S411, which is described in detail as follows.

[0097] S411 , using the first photoresist pattern 520 as a mask, etching the current spreading film 20 a and the epitaxial wafer 10 at a first ICP power and a first RF power, wherein the first ICP power is 550W to 650W, and the first RF power is 80W to 120W.

[0098] The first ICP power may be, but is not limited to, 550W, or 560W, or 570W, or 580W, or 590W, or 600W, or 610W, or 620W, or 630W, or 640W, or 650W.

[0099] The first RF power may be, but is not limited to, 80 W, 90 W, 100 W, 110 W, or 120 W.

[0100] In one embodiment, the first ICP power is 600W, and the first RF power is 100W.

[0101] In one embodiment, the micro-LED chip 1 is a GaN-based LED. The materials in the micro-LED chip 1 are mainly composed of GaN, InGaN, and AlGaN. The binding energy between the atoms of these materials is relatively high. When a device composed of such materials is corroded, if a chemical etching method is used, the etching speed is very slow. In the embodiment of the present application, the first plasma etching (also called dry etching, or dry etching) is used in S411, which can have a faster etching speed.

[0102] When the first ICP power is 550W-650W and the first RF power is 80W-120W, the etching speed is fast and the main part of the micro-LED chip 1 can be etched. That is, the N-type layer 120 in the epitaxial wafer 10 is exposed, or the N-type layer 120 is partially etched away by 100nm-200nm. In this way, the depth of the subsequently formed step structure 10b is about 800nm.

[0103] Furthermore, when etching the current spreading film 20a and the epitaxial wafer 10 under the first ICP power and the first RF power, the required gases include boron trichloride, chlorine and argon, and the ratio of boron trichloride, chlorine and argon is 10sccm:25sccm:5sccm. In this way, the etching speed of the current spreading film 20a and the epitaxial wafer 10 can be faster.

[0104] To sum up, in the embodiment of the present application, the first photoresist pattern 520 is used as a mask, and the current spreading film 20a and the epitaxial wafer 10 are etched under the first ICP power and the first RF power, wherein the first ICP power is 550W~650W, and the first RF power is 80W~120W, and the etching speed is fast, and the prototype of the step structure 10b can be quickly formed.

[0105] See also Figure 5 , Figure 5 for Figure 3 The flowchart of S420 in the method for preparing a micro-LED chip is shown in FIG. S420, using the first photoresist pattern 520 as a mask, performing a second plasma etching on the original step structure to form the step structure 10b, including S421, which is described in detail as follows.

[0106] S421, using the first photoresist pattern 520 as a mask, etching the original step structure at a second ICP power and a second RF power to form the step structure 10b, wherein the second ICP power is 0W to 350W, and the second RF power is 20W to 40W.

[0107] The second ICP power may be, but is not limited to, 0 W, 50 W, 100 W, 150 W, 200 W, 250 W, 300 W, or 350 W. It should be noted that when the second ICP is 0 W, the step S421 becomes reactive ion etching (RIE).

[0108] The second RF power may be, but is not limited to, 20 W, 25 W, 30 W, 35 W, or 40 W.

[0109] In one embodiment, the second ICP power is 300W, and the second RF power is 30W.

[0110] In this embodiment, the first photoresist pattern 520 is used as a mask, and the original step structure is etched at the second ICP power and the second RF power to form the step structure 10b, wherein the second ICP power is 0W to 350W, and the second RF power is 20W to 40W, so that the damage in the step structure 10b formed after the second plasma etching is nanometer-level (for example, 10nm to 50nm) damage. It can be seen that the preparation method of the micro-light-emitting diode chip 1 provided in the embodiment of the present application can reduce the damage of the step structure 10b in the micro-light-emitting diode chip 1. In other words, after the first plasma etching, the original step structure obtained has a first damage layer; after the second plasma etching, the step structure 10b obtained has a second damage layer, wherein the thickness of the second damage layer is less than the thickness of the first damage layer. Wherein, the thickness of the first damage layer is 1μm to 5μm, and the thickness of the second damage layer is 10nm to 50nm.

[0111] In summary, the method for preparing the micro-LED chip 1 provided in the embodiment of the present application first uses the first ICP power of 550W to 650W and the first RF power of 80W to 120W to perform a first plasma etching on the current spreading film 20a and the epitaxial wafer 10 to form an original step structure. Then, the second ICP power of 0W to 350W and the second RF power of 20W to 40W are used to perform a second plasma etching on the original step structure. The second power is less than the first power, so the sidewall damage of the step structure 10b can be reduced.

[0112] See also Figure 6 , Figure 6 for Figure 1 The flowchart of S200 in one embodiment of the method for preparing a micro-LED chip is shown in FIG. The epitaxial wafer 10 includes a substrate 110 and a P-type layer 150 facing away from the substrate 110. In this embodiment, the S200, forming a current spreading film 20a on the surface of the epitaxial wafer 10, includes S200A, and S200A is described in detail as follows.

[0113] S200A, forming a current spreading film 20 a on a surface of the P-type layer 150 away from the substrate 110 , wherein the current spreading film 20 a includes indium tin oxide.

[0114] When the current spreading layer 20 includes indium tin oxide (ITO), the P-type layer 150 of the epitaxial wafer 10 may be deposited on the surface facing away from the substrate by electron beam evaporation or sputtering.

[0115] In one embodiment, the thickness of the current spreading film 20a (that is, the thickness of the current spreading layer 20) is d1=(2N+1)λ / (4n), wherein the unit of d1 is nanometers, N is 0 or a positive integer, λ is the wavelength of the light emitted by the micro-LED chip 1, and n is the refractive index of the current spreading layer 20.

[0116] Taking the light emitted by the micro-LED chip 1 as blue light as an example, the wavelength of the blue light is 450nm. At this wavelength, take the current spreading layer 20 as an indium tin oxide film as an example. The refractive index of indium tin oxide is about 1.95. It can be calculated that when N=0, the thickness of the current spreading layer 20 is 58nm; when N=1, the thickness of the current spreading layer 20 is 173nm; when N=2, the thickness of the current spreading layer 20 is 288nm. The thicker the thickness of the current spreading layer 20, the better the conductivity of the current spreading layer 20. Normally, the thickness of the current spreading layer 20 is selected to be about 173nm. It can be understood that since the refractive index of indium tin oxide is related to the coating method, coating rate and temperature adopted, the specific numerical value selection should be adjusted according to the measured data.

[0117] See also Figure 7 , Figure 7 for Figure 1 The flowchart of S400 in another embodiment of the method for preparing a micro-LED chip shown in FIG. In this embodiment, S400 includes S410, S420, and S430A located after S420. Please refer to the previous description of S410 and S420, which will not be repeated here.

[0118] S410 , using the first photoresist pattern 520 as a mask, performing a first plasma etching on the current spreading film 20 a and the epitaxial wafer 10 , wherein the power of the first plasma etching is a first power, so as to form an original step structure.

[0119] S420, using the first photoresist pattern 520 as a mask, performing a second plasma etching on the original step structure to form the step structure 10b, wherein the power of the second plasma etching is a second power, and the second power is less than the first power.

[0120] S430A, using the first photoresist pattern 520 as a mask, etching the current spreading film 20 a and the step structure 10 b with a first etching solution.

[0121] In this embodiment, the current spreading film 20a and the step structure 10b are etched with the first etching solution to obtain the current spreading layer 20. As described above, the current spreading layer 20 is inwardly shrunk compared to the side 10e of the step structure 10b, and the inwardly shrunk dimension W0 satisfies: 0.5μm<W0≤4μm.

[0122] In this embodiment, when the current spreading film 20a includes indium tin oxide, the first etching solution includes hydrochloric acid. For example, the first etching solution is a hydrochloric acid solution, or the first etching solution is a mixed solution of a hydrochloric acid solution and a nitric acid solution. When the first etching solution is a mixed solution of a hydrochloric acid solution and a nitric acid solution, in other words, the mixed solution includes hydrochloric acid, nitric acid and water.

[0123] When the mixed solution includes hydrochloric acid, nitric acid and water, the ratio of the hydrochloric acid: the nitric acid: the water is 10:1:50 respectively.

[0124] In this embodiment, the first photoresist pattern 520 is used as a mask and the first etching solution is used to etch the current spreading film 20a and the step structure 10b. On the one hand, the second damaged layer formed in the second plasma etching can be removed; on the other hand, the first etching solution can have a lateral corrosion effect on the current spreading layer 20 under the first photoresist pattern 520, and the current spreading layer 20 can be formed to be retracted.

[0125] By precisely controlling the chemical ratio of each substance in the first etching solution and the etching time, the shrinkage size of the current spreading layer 20 relative to the step structure 10 b can be controlled.

[0126] In this embodiment, S430A can be regarded as a step of surface treatment of the second damaged layer in an embodiment (can also be referred to as the first step in an embodiment).

[0127] See also Figure 8 , Figure 8 This is a flow chart of a method for preparing a micro light emitting diode chip provided in another embodiment of the present application. After S430A, the preparation method further includes S500A, which is described in detail as follows.

[0128] S500A, annealing the current spreading layer 20 at 500° C. to 550° C. under nitrogen protection, and the annealing time is 10 minutes to 25 minutes.

[0129] For example, when the current spreading layer 20 is annealed at 500° C. to 550° C. under nitrogen protection, furnace annealing may be used.

[0130] In one embodiment, in the preparation method, S500A is performed after removing the first photoresist pattern 520 and washing. In other words, in one embodiment, after S430, the preparation method further includes: removing the first photoresist pattern 520; and then performing S500A.

[0131] The temperature for annealing the current spreading layer 20 may be, but is not limited to, 500°C, 510°C, 520°C, 530°C, 540°C, or 550°C.

[0132] The annealing time may be, but is not limited to, 10 minutes, 15 minutes, 20 minutes, or 25 minutes.

[0133] In one embodiment, the current spreading layer 20 is annealed at 500° C. under the protection of nitrogen. The current spreading layer 20 prepared in this way not only has good ohmic contact, but also has high transmittance. In this embodiment, the transmittance Tr of the current spreading layer 20 obtained can be greater than 90%.

[0134] In addition, the current spreading layer 20 is annealed at 500° C. to 550° C. under nitrogen protection for 10 minutes to 25 minutes; the current spreading layer 20 forms a good ohmic contact with the P-type layer 150 .

[0135] See also Fig. 9 and Fig.16 , Fig. 9 for Figure 1 The flowchart included in S200 of another embodiment of the method for preparing a micro light emitting diode chip shown in ; Fig.16 A schematic structural diagram of each step in a method for preparing a light-emitting diode provided in another embodiment. The epitaxial wafer 10 includes a substrate 110 and a P-type layer 150 facing away from the substrate 110. In this embodiment, the S200, forming a current spreading film 20a on the surface of the epitaxial wafer 10, includes S200B, and S200B is described in detail below.

[0136] S200B, forming a first sub-expansion film 210 a and a second sub-expansion film 210 b on the surface of the epitaxial wafer 10 , wherein the first sub-expansion film 210 a includes a Ni film, and the second sub-expansion film 210 b includes an Au film.

[0137] Please refer to the structural diagram of S200B Fig.16In (a), in this embodiment, the current spreading film 20a includes a first sub-spreading film 210a and a second sub-spreading film 210b. When the first sub-spreading film 210a includes a Ni film and the second sub-spreading film 210b includes an Au film, the current spreading film 20a is also called a NiAu film.

[0138] In one embodiment, when the first sub-extension film 210 a includes a Ni film, the thickness of the first sub-extension film 210 a is 10 angstroms to 50 angstroms, wherein 1 nanometer (nm) = 10 angstroms. In other words, 1 angstrom = 1 / 10 nm.

[0139] For example, the thickness of the first sub-expansion film 210 a may be, but is not limited to, 10 angstroms, 15 angstroms, 20 angstroms, 25 angstroms, 30 angstroms, 35 angstroms, 40 angstroms, 45 angstroms, or 50 angstroms.

[0140] In one embodiment, when the second sub-extension film 210 b includes an Au film, the thickness of the second sub-extension film 210 b is 10 angstroms to 50 angstroms.

[0141] For example, the thickness of the second sub-expansion film 210 b may be, but is not limited to, 10 angstroms, 15 angstroms, 20 angstroms, 25 angstroms, 30 angstroms, 35 angstroms, 40 angstroms, 45 angstroms, or 50 angstroms.

[0142] The thickness of the second sub-expansion film 210 b may be the same as or different from the thickness of the first sub-expansion film 210 a , which is not limited herein.

[0143] In one embodiment, the first sub-extension film 210 a includes a Ni film, and the thickness of the first sub-extension film 210 a is 20 angstroms; the second sub-extension film 210 b includes an Au film, and the thickness of the second sub-extension film 210 b is 30 angstroms.

[0144] When the current spreading film 20a includes a first sub-spreading film 210a and a second sub-spreading film 210b, wherein the first sub-spreading film 210a includes a Ni film and the second sub-spreading film 210b includes an Au film, if the thickness of the current spreading film 20a is thicker, the ohmic contact between the current spreading film 20a and the P-type layer 150 is better, however, the transmittance of the prepared micro-LED chip 1 is affected. Taking all factors into consideration, in the preparation method of the micro-LED chip 1 provided in an embodiment of the present application, when the first sub-spreading film 210a includes a Ni film, the thickness of the first sub-spreading film 210a is 10 angstroms to 50 angstroms; when the second sub-spreading film 210b includes an Au film, the thickness of the second sub-spreading film 210b is 10 angstroms to 50 angstroms. On the one hand, the ohmic contact between the prepared micro-LED chip 1 and the P-type layer 150 is better; on the other hand, the transmittance of the prepared micro-LED chip 1 is better.

[0145] When the first sub-expansion film 210a includes a Ni film and the thickness of the first sub-expansion film 210a is 20 angstroms; the second sub-expansion film 210b includes an Au film and the thickness of the second sub-expansion film 210b is 30 angstroms, on the one hand, the prepared micro-LED chip 1 can have excellent ohmic contact with the P-type layer 150; on the other hand, the prepared micro-LED chip 1 can also have better light transmittance.

[0146] See also Fig.10 , Fig.10 for Figure 1 In the method for preparing a micro-LED chip shown in FIG. 1 , S400 includes a flow chart. In this embodiment, S400 includes S430B-1 and S430B-2, and S430B-1 and S430B-2 are described in detail as follows.

[0147] S430B-1, using the first photoresist pattern 520 as a mask, using a second etching solution to etch the second sub-expansion film 210b, wherein the second sub-expansion film 210b is retracted relative to the side 10e of the step structure 10b, and the retracted dimension W2 satisfies: 0.5μm<W2≤4μm.

[0148] In one embodiment, the second sub-extension film 210 b is covered with an Au film, and therefore, when etching the second sub-extension film 210 b , the second etching solution includes an iodine-containing etching solution.

[0149] In one embodiment, the size W2 may be, but is not limited to, 0.5 μm, 1.0 μm, 1.5 μm, 2.0 μm, 2.5 μm, 3.0 μm, 3.5 μm, or 4.0 μm. In other words, in this embodiment, the size W2 may be 2.0 μm or about 2.0 μm.

[0150] S430B-2, using the first photoresist pattern 520 as a mask, using a third etching solution to etch the first sub-expansion film 210a, wherein the first sub-expansion film 210a is retracted relative to the side 10e of the step structure 10b, and the retracted dimension W1 satisfies: 0.5μm<W1≤4μm.

[0151] Please refer to the structural diagram of S430B-2 Fig.16 In (b), in this embodiment, the first sub-expansion film 210a includes a Ni film, and the third etching solution includes hydrochloric acid and nitric acid. In other words, the third etching solution includes diluted aqua regia.

[0152] In one embodiment, the size W1 may be, but is not limited to, 0.5 μm, or 1.0 μm, or 1.5 μm, or 2.0 μm, or 2.5 μm, or 3.0 μm, or 3.5 μm, or 4.0 μm. In other words, in this embodiment, the size W1 may be selected to be 2.0 μm or about 2.0 μm. In the schematic diagram of this embodiment, W1=W2 is used as an example for illustration. It can be understood that W1=W2 is an optimal choice, which can ensure the consistency of electrical parameters and transmittance of the NiAu alloy film formed after annealing at the edge and inside. In other embodiments, W1 may not be equal to W2.

[0153] In this embodiment, the first photoresist pattern 520 is used as a mask, and the second sub-expansion film 210b is corroded by a second etching solution; and the current spreading film 20a and the step structure 10b are etched by a third etching solution. On the one hand, the second damaged layer formed in the second plasma etching can be removed; on the other hand, the first etching solution can have a lateral corrosion effect on the current spreading layer 20 under the first photoresist pattern 520, and the current spreading layer 20 can be formed to be retracted.

[0154] By precisely controlling the chemical ratio of each substance in the second etching solution and the etching time, the shrinking size of the second sub-expansion film 210b relative to the step structure 10b can be controlled. Correspondingly, by precisely controlling the chemical ratio of each substance in the third etching solution and the etching time, the shrinking size of the first sub-expansion film 210a relative to the step structure 10b can be controlled.

[0155] In this embodiment, S430B-1 and S430B-2 can be regarded as a step of surface treatment of the second damaged layer in another embodiment (can also be referred to as the first step in another embodiment).

[0156] See also Fig.11 , Fig.11 This is a flow chart of a method for preparing a micro light emitting diode chip provided in another embodiment of the present application. After S430B-2, the preparation method further includes S500B, which is described in detail as follows.

[0157] S500B, annealing the current spreading film 20a at 500°C-600°C.

[0158] The temperature for annealing the current spreading film 20a may be, but is not limited to, 500°C, 550°C, or 600°C.

[0159] In this embodiment, the current spreading film 20a is annealed at 500°C-600°C, so that the current spreading layer 20 prepared in this way not only has good ohmic contact, but also has high transmittance. In this embodiment, the transmittance Tr of the obtained current spreading layer 20 satisfies: Tr≥80%. For example, when the current spreading layer 20 includes Ni and Au, the current spreading film 20a is annealed at 500°C-600°C, so that Ni and Au can form a transparent NiAu alloy film, so that the transmittance of the current spreading layer 20 is high.

[0160] In addition, the current spreading film 20 a is annealed at 500° C.-600° C., so that the current spreading layer 20 forms a good ohmic contact with the P-type layer 150 .

[0161] See also Fig.12 , Fig.12 This is a flowchart of S400 in a micro-LED chip provided in one embodiment of the present application. After S430A or after S430B-2, S400 uses the first photoresist pattern 520 as a mask to etch the current spreading film 20a and the step structure 10b, and also includes S440 and S450. S440 and S450 are described in detail as follows.

[0162] S440 , removing the first photoresist pattern 520 .

[0163] In one embodiment, acetone combined with a photoresist remover can be used to remove the first photoresist pattern 520. For example, the photoresist remover includes PRS3000, etc. In addition, in another embodiment, a plasma dry method can also be used to remove the first photoresist pattern 520.

[0164] S450 , removing stains on the surface of the step structure 10 b and the current spreading layer 20 .

[0165] In S450, after removing the first photoresist pattern 520, it is necessary to remove stains on the surface of the step structure 10b and the current spreading layer 20, including removing stains caused in the process of removing the first photoresist pattern 520 in S440.

[0166] For example, the first cleaning liquid (e.g., NH4OH / H2O2 / H2O) and the second cleaning liquid (e.g., HF:H2O) are used alternately twice. In this way, the polymer formed on the surface of the step structure 10b and the current spreading layer 20 and the organic contaminants adhering to the surface, including oxides, can be removed.

[0167] S440 and S450 may be regarded as another step of surface treatment of the second damaged layer in one embodiment or another embodiment, also referred to as a second step.

[0168] The second damaged layer can be reduced through S440 and S450, that is, the damage on the sidewall of the stepped structure 10b can be reduced.

[0169] See also Fig.13 , Fig.13 This is a flowchart of S400 in a micro LED chip provided in another embodiment of the present application. After S450, S400 etches the current spreading film 20a and the step structure 10b using the first photoresist pattern 520 as a mask, and also includes S460 and S470. S460 and S470 are described in detail below.

[0170] S460 , removing stains on the surface of the step structure 10 b and the current spreading layer 20 .

[0171] In this embodiment, the step structure 10b and the current spreading layer 20 may be cleaned with hydrochloric acid (HCl:H2O) to remove metal ions, including In, C, and enriched Ga and Al, etc., remaining on the surface of the sidewall 10c of the step structure 10b.

[0172] S470 , performing plasma treatment on the step structure 10 b and the current spreading layer 20 to reduce surface recombination centers.

[0173] In this embodiment, NH 3 or N 2 plasma treatment may be used to reduce or eliminate surface recombination centers caused by N vacancies.

[0174] S460 and S470 may be regarded as another step of surface treatment of the second damaged layer in one embodiment or another embodiment, also referred to as the third step.

[0175] After S460 and S470, the second damaged layer can be reduced or even eliminated, that is, the sidewall damage of the stepped structure 10b can be reduced or even eliminated.

[0176] See also Fig.14 and Fig.17 , Fig.14 A schematic diagram of the steps included in a method for preparing a micro light-emitting diode chip provided in another embodiment of the present application; Fig.17 for Fig.14 The structural schematic diagram corresponding to each step in the preparation method of the light emitting diode provided in the embodiment. In this embodiment, the preparation method further includes S600, S700, S800 and S900, wherein the preparation method further includes S600, S700, S800 and S900 combined with Figure 1 The preparation method provided in the corresponding embodiment is used as an example for illustration. In this embodiment, the preparation method includes S100, S200, S300 and S400. Please refer to the previous description for S100, S200, S300 and S400, which will not be repeated here. It can be understood that the preparation method also includes S600, S700, S800 and S900, which can be combined with the preparation method provided in any of the previous embodiments. The schematic diagram of this application should not be understood as a limitation on the embodiments of this application.

[0177] S600 , forming a passivation layer 30 on the surface of the current spreading layer 20 from which the first photoresist pattern 520 is removed.

[0178] Please also read Fig.17 (a) and Fig.17 (b) in which, Fig.17 (a) is a schematic diagram showing the removal of the first photoresist pattern. Fig.17 (b) in Fig.17 Schematic diagram of the structure of the current spreading layer 20 in (a) in which the passivation layer 30 is formed on the surface of the current spreading layer 20. In this embodiment, the passivation layer 30 is formed and combined with the structure provided in the previous embodiment (this embodiment is Fig.15 The structure in FIG. 1 is used as an example to illustrate. It can be understood that the formation of the passivation layer 30 can also be combined with the structure in other embodiments, for example, it can be combined with Fig.16 In one embodiment, the passivation layer 30 may be formed by PECVD. In another embodiment, the passivation layer 30 may be formed by sputtering. It is understood that the embodiments of the present application provide Fig.17The structure of the first photoresist pattern in should not be understood as a limitation to the embodiments of the present application.

[0179] The passivation layer 30 is disposed on the surface of the current spreading layer 20 away from the substrate 110, and the passivation layer 30 is also disposed on the sidewall 10c of the step structure 10b. In this way, the non-radiative recombination of the surface and the sidewall 10c of the prepared micro-LED chip 1 is further reduced, the leakage of the sidewall 10c of the prepared micro-LED chip 1 can be reduced, and the luminous efficiency of the LED is improved.

[0180] In one embodiment, S600 specifically includes sequentially forming a first sub-passivation film 310 and a second sub-passivation film 320 on the surface of the current spreading layer 20 from which the first photoresist pattern 520 is removed, wherein the passivation layer 30 includes a stacked first sub-passivation film 310 and a second sub-passivation film 320. It can be understood that in other embodiments, the passivation layer 30 is a layer.

[0181] In one embodiment, the second sub-passivation film 320 plays a role of both passivation and anti-reflection film. In other words, the second sub-passivation film 320 has the functions of passivation and anti-reflection. In this way, it can protect the current spreading layer 20 and the N-type layer 120 under the passivation layer 30, so that more light can be emitted from the micro-LED chip 1, and the brightness of the light emitted by the micro-LED chip 1 can be increased.

[0182] In one embodiment, the first sub-passivation film 310 includes aluminum nitride (AlN). In one embodiment, the first sub-passivation film 310 may be formed by atomic layer deposition (ALD). The thickness d21 of the first sub-passivation film 310 satisfies: 2nm≤d21≤5nm.

[0183] For example, the thickness d21 of the first sub-passivation film 310 may be, but is not limited to, 2 nm, 3 nm, 4 nm, or 5 nm.

[0184] Generally speaking, the growth rate of the first sub-passivation film 310 formed by atomic layer deposition is slow. For example, if an additional 5nm is grown on the basis of the current thickness d21, an additional half an hour is required. In the embodiment of the present application, the thickness d21 of the first sub-passivation film 310 satisfies: 2nm≤d21≤5nm. On the one hand, it can meet the passivation requirements for the sidewalls; on the other hand, it can also save preparation time.

[0185] In addition, the combination of the first sub-passivation film 310 and the second sub-passivation film 320 can further reduce the non-radiative recombination on the surface and side wall 10c of the prepared micro-LED chip 1, reduce the leakage of the side wall 10c of the prepared micro-LED chip 1, and improve the luminous efficiency of the micro-LED chip 1.

[0186] In one embodiment, the second sub-passivation film 320 includes silicon nitride (SiN), or aluminum oxide (Al2O3), or silicon dioxide (SiO2). In one embodiment, the second sub-passivation film 320 can be grown by PECVD. The thickness d22 of the second sub-passivation film 320 satisfies: d22 = λ / 4n, where λ is the wavelength of the light emitted by the micro-LED chip 1, and n is the refractive index of the second sub-passivation film 320. For example, when the second sub-passivation film 320 includes silicon nitride, n is the refractive index of silicon nitride.

[0187] Taking the second sub-passivation film 320 including silicon nitride (SiN) as an example, the refractive index of silicon nitride (SiN) corresponding to a wavelength of 450nm is around 2.0 or 2.0 (for example, 2.0 or 2.05). Therefore, the thickness corresponding to the wavelength of 450 nanometers can be 56 nanometers, 169 nanometers, 281 nanometers, etc., with 170 nanometers being preferred here.

[0188] In this embodiment, S600 specifically includes sequentially forming a first sub-passivation film 310 and a second sub-passivation film 320 on the surface of the current spreading layer 20 from which the first photoresist pattern 520 has been removed, wherein the passivation layer 30 includes a first sub-passivation film 310 and a second sub-passivation film 320 that are stacked, which can further reduce the non-radiative recombination of the surface and side wall 10c of the prepared micro-LED chip 1, reduce the leakage of the side wall 10c of the prepared micro-LED chip 1, and improve the luminous efficiency of the micro-LED chip 1.

[0189] In addition, in the related art, the passivation film may also be a single layer of silicon dioxide, or a single layer of silicon nitride, or silicon oxynitride (i.e., SiON). In other embodiments of the present application, the passivation film may be a single layer or a composite multilayer passivation film, such as a composite film formed by aluminum oxide (Al2O3) and silicon nitride (SiN), so that the non-radiative recombination of the side wall 10c of the step structure 10b of the prepared micro-LED chip 1 can be reduced, the leakage of the side wall 10c of the prepared micro-LED chip 1 can be reduced, and the luminous efficiency of the micro-LED chip 1 can be improved.

[0190] S700, forming a second photoresist pattern 540 on the surface of the passivation layer 30, the second photoresist pattern 540 includes a first through hole 541 and a second through hole 542, the first through hole 541 is used to expose the passivation layer 30 and is arranged corresponding to the current spreading layer 20, and the second through hole 542 is used to expose the passivation layer 30 and is arranged corresponding to the bottom of the step structure 10b. It can be understood that in the embodiment of the present application, the structure of each step in each film layer (for example, the second photoresist pattern 540) is illustrated by taking a right angle as an example, and it can be understood that it should not be understood as a limitation on the embodiment of the present application. For example, in one embodiment, the step of the second photoresist pattern 540 (such as the first step on the side, etc.) is a circular chamfer.

[0191] Please refer to the structure of S700 Fig.17 Specifically, in S700 , a second photoresist film is first formed on the surface of the passivation layer 30 , and then the second photoresist film is patterned to obtain a second photoresist pattern 540 , wherein the second photoresist pattern 540 has a first through hole 541 and a second through hole 542 .

[0192] The first through hole 541 is a contact window for the first electrode 410 in the micro LED chip 1 , and the second through hole 542 is a contact window for the second electrode 420 in the micro LED chip 1 .

[0193] In this embodiment, the second photoresist film is a negative photoresist, and accordingly, the second photoresist pattern 540 is also a negative photoresist. It can be understood that in other embodiments, the second photoresist film is a positive photoresist, and accordingly, the second photoresist pattern 540 is also a positive photoresist.

[0194] S800, using the second photoresist pattern 540 as a mask, removing the portion of the passivation layer 30 exposed in the first through hole 541 and the portion exposed in the second through hole 542, so as to form a first through hole 30a corresponding to the first through hole 541 and a second through hole 30b corresponding to the second through hole 542 in the passivation layer 30.

[0195] Please refer to the structure of S800 Fig.17 In this embodiment, wet etching or dry etching may be used to remove the portion of the passivation layer 30 exposed in the first through hole 541 and the portion exposed in the second through hole 542, so as to form a first through hole 30a and a second through hole 30b in the passivation layer 30. The first through hole 30a corresponds to the first through hole 541, and the second through hole 30b corresponds to the second through hole 542.

[0196] S900 , forming a first electrode 410 in the first through hole 30 a and forming a second electrode 420 in the second through hole 30 b to obtain a micro light emitting diode chip 1 .

[0197] After S900, please refer to Fig.17 (e) in the embodiment. In this embodiment, a metal layer is deposited from the surface of the second photoresist pattern 540 away from the passivation layer 30, part of the metal enters the first through hole 30a, part of the metal enters the second through hole 30b, and part of the metal covers the surface of the passivation layer 30 away from the passivation layer 30. The second photoresist pattern 540 is stripped (also referred to as a stripping process) to remove the second photoresist layer 530 and the metal layer on the second photoresist layer 530. The metal in the first through hole 30a forms the first electrode 410, and the metal in the second through hole 30b forms the second electrode 420.

[0198] In one embodiment, the metal layer may be, but is not limited to, a metal combination such as Cr / Au, Cr / Pt / Au, Cr / Pd / Au, etc.

[0199] In this embodiment, the first electrode 410 is a P electrode, and the second electrode 420 is an N electrode.

[0200] It can be seen that the method for preparing the micro light emitting diode chip 1 provided in the embodiment of the present application can form the first electrode 410 and the second electrode 420 in the same process.

[0201] In the method for preparing the micro-LED chip 1 provided in the related art, the deposition step of the passivation layer 30 is usually completed before the step of forming the first electrode 410 and the second electrode 420. It can be seen that in the method for preparing the micro-LED chip 1 in the related art, one photolithography step is used to form the first electrode 410 and the second electrode 420; and another photolithography step is required to form the passivation layer 30 and expose the first electrode 410 and the second electrode 420. In the method for preparing the micro-LED chip 1 provided in the embodiment of the present application, a passivation layer 30 is first formed, a second photoresist film is formed on the surface of the passivation layer 30, and then the second photoresist film is patterned to form a second photoresist pattern 540, and the first through hole 30a and the second through hole 30b are formed on the passivation layer 30 using the second photoresist pattern 540 as a mask; next, a metal layer is formed on the surface of the second photoresist pattern 540 away from the substrate 110 using the second photoresist pattern 540 as a mask, and the second photoresist layer 530 and the metal layer on the second photoresist layer 530 are removed. The metal in the first through hole 30a forms the first electrode 410, and the metal in the second through hole 30b forms the second electrode 420. Therefore, in the method for preparing the micro-LED chip 1 provided in the embodiment of the present application, the passivation layer 30, the first electrode 410 and the second electrode 420 are formed by one photolithography step. In other words, the passivation layer 30 , the first electrode 410 , and the second electrode 420 can be formed by using one second photoresist pattern 540 , thereby achieving the effect of a single second photoresist pattern 540 having multiple uses.

[0202] The embodiment of the present application also provides a micro-LED chip 1. The micro-LED chip 1 provided in the embodiment of the present application can be prepared by the preparation method of the micro-LED chip 1 described above. Accordingly, the preparation method of the micro-LED chip 1 provided above can also prepare the micro-LED chip 1 provided in the embodiment of the present application.

[0203] Next, the micro-LED chip 1 provided in the embodiment of the present application is described in detail. Fig.18 and Fig.19 , Fig.18 A schematic diagram of the structure of a micro light emitting diode chip provided in one embodiment of the present application; Fig.19 for Fig.18Schematic diagram of partial details of the micro-LED chip shown in . The micro-LED chip 1 includes an epitaxial wafer 10, a current spreading layer 20, a passivation layer 30, a first electrode 410 and a second electrode 420. The epitaxial wafer 10 includes a substrate 110 and a P-type layer 150 facing away from the substrate 110. Specifically, the epitaxial wafer 10 includes a substrate 110 and an N-type layer 120, an active layer 130, an electron blocking layer 140 and a P-type layer 150 stacked on the substrate 110 in sequence. The micro-LED chip 1 includes a step structure 10b, and the step structure 10b includes a side wall 10c and a bottom wall 10d connected by bending. The current spreading layer 20 is arranged on the surface of the P-type layer 150 facing away from the substrate 110, and the current spreading layer 20 is indented compared to the side 10e of the step structure 10b, and the indented size W0 satisfies: 0.5μm<W0≤4μm. The passivation layer 30 is disposed on the surface and the surrounding side of the current spreading layer 20, and is disposed on the side wall 10c and the bottom wall 10d of the step structure 10b. The passivation layer 30 has a first through hole 30a and a second through hole 30b, wherein the first through hole 30a exposes a portion of the current spreading layer 20, and the second through hole 30b exposes a portion of the bottom wall 10d of the step structure 10b. The first electrode 410 is disposed in the first through hole 30a. The second electrode 420 is disposed in the second through hole 30b.

[0204] In this embodiment, the inward dimension W0 may be, but is not limited to, 0.5 μm, 1.0 μm, 1.5 μm, 2.0 μm, 2.5 μm, 3.0 μm, 3.5 μm, or 4.0 μm. In other words, in this embodiment, W0 may be 2.0 μm or about 2.0 μm.

[0205] Generally speaking, during the preparation process of the micro-LED chip 1, the side wall 10c of the step structure 10b may have defects. If electrons and holes are transmitted to the active layer 130 via the side wall 10c of the step structure 10b, non-radiative recombination will be formed, thereby generating heat, and light that can be emitted from the light-emitting surface of the micro-LED chip 1 cannot be generated. When the current spreading layer 20 is smaller than the side 10e of the step structure 10b, there will still be more holes transmitted to the active layer 130 via the side wall 10c of the step structure 10b, and non-radiative recombination with the electrons transmitted to the active layer 130 will generate heat, resulting in low luminous efficiency. When the current spreading layer 20 is larger than the side 10e of the step structure 10b, the effective light-emitting area of ​​the micro-LED chip 1 is smaller. The current spreading layer 20 of the micro-LED chip 1 provided in the embodiment of the present application is retracted compared to the side 10e of the step structure 10b, and the retracted size W0 satisfies: 0.5μm<W0≤4μm. On the one hand, it can reduce the holes transmitted to the active layer 130 through the side wall 10c of the step structure 10b, thereby improving the luminous efficiency; on the other hand, it can also make the effective luminous area of ​​the micro-LED chip 1 larger.

[0206] In summary, the current spreading layer 20 of the micro-LED chip 1 provided in the embodiment of the present application is retracted compared to the side 10e of the step structure 10b, and the retracted size W0 satisfies: 0.5μm<W0≤4μm. On the one hand, the holes transmitted to the active layer 130 through the side wall 10c of the step structure 10b can be reduced, thereby improving the luminous efficiency; on the other hand, the effective luminous area of ​​the micro-LED chip 1 can also be made larger.

[0207] Further, in one embodiment, please refer to Fig. 20 , Fig. 20 for Fig.18 A schematic diagram of the thickness of the current spreading layer provided in one embodiment. The current spreading layer 20 includes indium tin oxide, and the thickness d1 of the current spreading layer 20 satisfies: d1 = (2N + 1) λ / (4n), wherein the unit of d1 is nanometers, N is 0 or a positive integer, λ is the wavelength of the light emitted by the micro-LED chip 1, and n is the refractive index of the current spreading layer 20.

[0208] In one embodiment, the thickness of the current spreading layer 20 is d1=(2N+1)λ / (4n), wherein the unit of d1 is nanometers, N is 0 or a positive integer, λ is the wavelength of the light emitted by the micro-LED chip 1, and n is the refractive index of the current spreading layer 20.

[0209] Take the light emitted by the micro-LED chip 1 as blue light, for example, the wavelength of the blue light is 450nm. Take the current spreading layer 20 as an example, including indium tin oxide. The refractive index of indium tin oxide is 1.95. When N=0, the thickness of the current spreading layer 20 is 58nm; when N=1, the thickness of the current spreading layer 20 is 173nm; when N=2, the thickness of the current spreading layer 20 is 288nm. The thicker the thickness of the current spreading layer 20, the better the conductivity of the current spreading layer 20. Usually, the thickness of the current spreading layer 20 is selected to be 173nm.

[0210] For further information, see Fig.21 , Fig.21 A partial structural diagram of a micro-LED chip provided in one embodiment. The current spreading layer 20 includes a first sub-spreading film 210a and a second sub-spreading film 210b stacked in sequence. The first sub-spreading film 210a includes a Ni film, and the first sub-spreading film 210a is inwardly shrunk compared to the side 10e of the step structure 10b, and the inwardly shrunk dimension W1 satisfies: 0.5μm<W1≤4μm; the second sub-spreading film 210b includes an Au film, and the second sub-spreading film 210b is inwardly shrunk compared to the side 10e of the step structure 10b, and the inwardly shrunk dimension W2 satisfies: 0.5μm<W2≤4μm.

[0211] In this embodiment, the first sub-expansion film 210a includes a Ni film. In one embodiment, the size W1 may be, but is not limited to, 0.5 μm, 1.0 μm, 1.5 μm, 2.0 μm, 2.5 μm, 3.0 μm, 3.5 μm, or 4.0 μm. In other words, in this embodiment, the size W1 may be 2.0 μm or about 2.0 μm.

[0212] Further, in one embodiment, the second sub-expansion film 210b is a Au film. In one embodiment, the size W2 may be, but is not limited to, 0.5 μm, 1.0 μm, 1.5 μm, 2.0 μm, 2.5 μm, 3.0 μm, 3.5 μm, or 4.0 μm. In other words, in this embodiment, the size W2 may be 2.0 μm or about 2.0 μm.

[0213] In this embodiment, W1=W2 is an optimal choice, which can ensure the consistency of electrical parameters and transmittance of the NiAu alloy film formed after annealing at the edge and inside. Taking W1=W2 as an example, it can be understood that in other embodiments, W1 may not be equal to W2.

[0214] In summary, the current spreading layer 20 of the micro-LED chip 1 provided in the embodiment of the present application includes a first sub-spreading film 210a and a second sub-spreading film 210b stacked in sequence. The first sub-spreading film 210a includes a Ni film, and the first sub-spreading film 210a is inwardly shrunk compared to the side 10e of the step structure 10b, and the inwardly shrunk dimension W1 satisfies: 0.5μm<W1≤4μm; the second sub-spreading film 210b includes an Au film, and the second sub-spreading film 210b is inwardly shrunk compared to the side 10e of the step structure 10b, and the inwardly shrunk dimension W2 satisfies: 0.5μm<W2≤4μm; on the one hand, the holes transmitted to the active layer 130 through the side wall 10c of the step structure 10b can be reduced, thereby improving the luminous efficiency; on the other hand, the effective luminous area of ​​the micro-LED chip 1 can also be made larger.

[0215] In one embodiment, when the first sub-extension film 210 a includes a Ni film, the thickness of the first sub-extension film 210 a is 10 angstroms to 50 angstroms, wherein 1 nanometer (nm) = 10 angstroms. In other words, 1 angstrom = 1 / 10 nm.

[0216] For example, the thickness of the first sub-expansion film 210 a may be, but is not limited to, 10 angstroms, 15 angstroms, 20 angstroms, 25 angstroms, 30 angstroms, 35 angstroms, 40 angstroms, 45 angstroms, or 50 angstroms.

[0217] In one embodiment, when the second sub-extension film 210 b includes an Au film, the thickness of the second sub-extension film 210 b is 10 angstroms to 50 angstroms.

[0218] For example, the thickness of the second sub-expansion film 210 b may be, but is not limited to, 10 angstroms, 15 angstroms, 20 angstroms, 25 angstroms, 30 angstroms, 35 angstroms, 40 angstroms, 45 angstroms, or 50 angstroms.

[0219] The thickness of the second sub-expansion film 210 b may be the same as or different from the thickness of the first sub-expansion film 210 a , which is not limited herein.

[0220] In one embodiment, the first sub-extension film 210 a includes a Ni film, and the thickness of the first sub-extension film 210 a is 20 angstroms; the second sub-extension film 210 b includes an Au film, and the thickness of the second sub-extension film 210 b is 30 angstroms.

[0221] When the current spreading film 20a includes a first sub-spreading film 210a and a second sub-spreading film 210b, wherein the first sub-spreading film 210a includes a Ni film and the second sub-spreading film 210b includes an Au film, if the thickness of the current spreading film 20a is thicker, the ohmic contact between the current spreading film 20a and the P-type layer 150 is better, however, the transmittance of the prepared micro-LED chip 1 is affected. Taking all factors into consideration, in the preparation method of the micro-LED chip 1 provided in an embodiment of the present application, when the first sub-spreading film 210a includes a Ni film, the thickness of the first sub-spreading film 210a is 10 angstroms to 50 angstroms; when the second sub-spreading film 210b includes an Au film, the thickness of the second sub-spreading film 210b is 10 angstroms to 50 angstroms. On the one hand, the ohmic contact between the prepared micro-LED chip 1 and the P-type layer 150 is better; on the other hand, the transmittance of the prepared micro-LED chip 1 is better.

[0222] When the first sub-expansion film 210a includes a Ni film and the thickness of the first sub-expansion film 210a is 20 angstroms; the second sub-expansion film 210b includes an Au film and the thickness of the second sub-expansion film 210b is 30 angstroms, on the one hand, the prepared micro-LED chip 1 can have excellent ohmic contact with the P-type layer 150; on the other hand, the prepared micro-LED chip 1 can also have better light transmittance.

[0223] For further information, see Fig.18 , the passivation film includes a first sub-passivation film 310 and a second sub-passivation film 320 which are stacked, and the second sub-passivation film 320 is away from the substrate 110 compared with the first sub-passivation film 310. The first sub-passivation film 310 includes AlN, and the thickness d21 of the first sub-passivation film 310 satisfies: 2nm≤d21≤5nm. The second sub-passivation film 320 includes SiN, or Al2O3, or SiO2, and the thickness d22 of the second sub-passivation film 320 satisfies: d22=λ / 4n, wherein n is the refractive index of the second sub-passivation film 320 for the light emitted by the micro-LED chip, and λ is the wavelength of the light emitted by the micro-LED chip 1.

[0224] In one embodiment, the first sub-passivation film 310 includes aluminum nitride (AlN). In one embodiment, the first sub-passivation film 310 may be formed by ALD growth. The thickness d21 of the first sub-passivation film 310 satisfies: 2nm≤d21≤5nm.

[0225] For example, the thickness d21 of the first sub-passivation film 310 may be, but is not limited to, 2 nm, 3 nm, 4 nm, or 5 nm.

[0226] In one embodiment, the second sub-passivation film 320 includes silicon nitride (SiN), aluminum oxide (Al2O3), or silicon dioxide (SiO2). In one embodiment, the second sub-passivation film 320 can be grown by PECVD. The thickness d22 of the second sub-passivation film 320 satisfies: d22 = λ / 4n, where n is the refractive index of the second sub-passivation film 320 for the light emitted by the micro-LED chip, and λ is the wavelength of the light emitted by the micro-LED chip 1.

[0227] Taking the second sub-passivation film 320 comprising SiN as an example, the thickness corresponding to a wavelength of 450 nanometers can be 56 nanometers, 169 nanometers, 281 nanometers, etc., and 170 nanometers is preferred.

[0228] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in the field can change, modify, replace and modify the above embodiments within the scope of the present application, and these improvements and modifications are also regarded as the scope of protection of the present application.

Claims

1. A method for preparing a micro light emitting diode chip, characterized in that: The preparation method comprises: Providing epitaxial wafers; forming a current spreading film on a surface of the epitaxial wafer; forming a first photoresist pattern on a surface of the current spreading film away from the epitaxial wafer, wherein the first photoresist pattern exposes a periphery of the current spreading film; and The current spreading film and the epitaxial wafer are etched using the first photoresist pattern as a mask to remove a portion of the current spreading film not covered by the first photoresist pattern to form a current spreading layer, and a portion of the epitaxial wafer adjacent to the current spreading film and not covered by the first photoresist pattern is removed to form a step structure on the epitaxial wafer, wherein the current spreading layer is indented compared to a side of the step structure, and a size W0 of the indentation satisfies: 0.5 μm<W0≤4 μm.

2. The preparation method according to claim 1, characterized in that The etching of the current spreading film and the epitaxial wafer using the first photoresist pattern as a mask comprises: Using the first photoresist pattern as a mask, performing a first plasma etching on the current spreading film and the epitaxial wafer, wherein the power of the first plasma etching is a first power, so as to form an original step structure; and The first photoresist pattern is used as a mask to perform a second plasma etching on the original step structure to form the step structure, wherein the power of the second plasma etching is a second power, and the second power is less than the first power.

3. The preparation method according to claim 2, characterized in that: The first photoresist pattern is used as a mask to perform a first plasma etching on the current spreading film and the epitaxial wafer, comprising: Using the first photoresist pattern as a mask, etching the current spreading film and the epitaxial wafer under a first ICP power and a first RF power, wherein the first ICP power is 550W to 650W, and the first RF power is 80W to 120W; Using the first photoresist pattern as a mask, performing a second plasma etching on the original step structure to form the step structure, comprising: Using the first photoresist pattern as a mask, the original step structure is etched at a second ICP power and a second RF power to form the step structure, wherein the second ICP power is 0W to 350W, and the second RF power is 20W to 40W.

4. The preparation method according to claim 2, characterized in that: in, The epitaxial wafer includes a substrate and a P-type layer away from the substrate; The step of forming a current spreading film on the surface of the epitaxial wafer comprises: forming a current spreading film on a surface of the P-type layer facing away from the substrate, wherein the current spreading film comprises indium tin oxide; and After the original step structure is subjected to a second plasma etching using the first photoresist pattern as a mask to form the step structure, the current spreading film and the epitaxial wafer are etched using the first photoresist pattern as a mask, further comprising: Using the first photoresist pattern as a mask, etching the current spreading film and the step structure with a first etching solution to obtain the current spreading layer; The preparation method further comprises: The current spreading layer is annealed at 500° C. to 550° C. under nitrogen protection, and the annealing time is 10 minutes to 25 minutes.

5. The preparation method according to claim 2, characterized in that: The epitaxial wafer includes a substrate and a P-type layer away from the substrate; the current spreading film is formed on the surface of the epitaxial wafer, including: forming a first sub-extension film and a second sub-extension film on the surface of the epitaxial wafer, wherein the first sub-extension film comprises a Ni film, and the second sub-extension film comprises an Au film; After the original step structure is subjected to a second plasma etching using the first photoresist pattern as a mask to form the step structure, the current spreading film and the epitaxial wafer are etched using the first photoresist pattern as a mask, further comprising: Using the first photoresist pattern as a mask, etching the second sub-expansion film with a second etching solution, wherein the second sub-expansion film is indented compared to the side of the step structure, and the indented dimension W2 satisfies: 0.5 μm<W2≤4 μm; and Using the first photoresist pattern as a mask, the first sub-expanded film is etched with a third etching solution, wherein the first sub-expanded film is indented compared to the side of the step structure, and the indented dimension W1 satisfies: 0.5 μm<W1≤4 μm; The preparation method further comprises: The current spreading film is annealed at 500° C.-600° C.

6. The preparation method according to claim 1, characterized in that: The preparation method further comprises: forming a passivation layer on the surface of the current spreading layer from which the first photoresist pattern is removed; forming a second photoresist pattern on the surface of the passivation layer, wherein the second photoresist pattern includes a first through hole and a second through hole, wherein the first through hole is used to expose the passivation layer and is arranged corresponding to the current spreading layer, and the second through hole is used to expose the passivation layer and is arranged corresponding to the bottom of the step structure; Using the second photoresist pattern as a mask, removing the portion of the passivation layer exposed in the first through hole and the portion exposed in the second through hole, so as to form a first through hole corresponding to the first through hole and a second through hole corresponding to the second through hole in the passivation layer; and A first electrode is formed in the first through hole and a second electrode is formed in the second through hole to obtain a micro light emitting diode chip.

7. A micro light emitting diode chip, characterized in that: The micro light emitting diode chip comprises: An epitaxial wafer, the epitaxial wafer comprising a substrate and an N-type layer, an active layer, an electron blocking layer and a P-type layer stacked in sequence on the substrate; The chip comprises a step structure, and the step structure comprises a side wall and a bottom wall connected by bending; A current spreading layer, wherein the current spreading layer is disposed on a surface of the P-type layer away from the substrate, and the current spreading layer is inwardly contracted compared to a side of the step structure, and a size W0 of the inward contraction satisfies: 0.5 μm<W0≤4 μm; A passivation layer, the passivation layer is disposed on the surface and the peripheral side of the current spreading layer, and is disposed on the sidewall and the bottom wall of the step structure, the passivation layer has a first through hole and a second through hole, wherein the first through hole exposes a portion of the current spreading layer, and the second through hole exposes a portion of the bottom wall of the step structure; A first electrode, the first electrode is disposed in the first through hole; and A second electrode is disposed in the second through hole.

8. The micro light emitting diode chip according to claim 7, characterized in that: The current spreading layer includes indium tin oxide, and the thickness d1 of the current spreading layer satisfies: d1=(2N+1)λ / (4n), wherein the unit of d1 is nanometer, N is 0 or a positive integer, λ is the wavelength of the light emitted by the micro-LED chip, and n is the refractive index of the current spreading layer.

9. The micro light emitting diode chip according to claim 7, characterized in that: The current spreading layer includes a first sub-spreading film and a second sub-spreading film stacked in sequence, the first sub-spreading layer includes a Ni film, the first sub-spreading film is retracted compared to the side of the step structure, and the retracted size W1 satisfies: 0.5μm<W1≤4μm; the second sub-spreading layer includes an Au film, the second sub-spreading film is retracted compared to the side of the step structure, and the retracted size W2 satisfies: 0.5μm<W2≤4μm.

10. The micro light emitting diode chip according to claim 7, characterized in that: The passivation film includes a first sub-passivation film and a second sub-passivation film which are stacked, and the second sub-passivation film is farther away from the substrate than the first sub-passivation film; The first sub-passivation film includes AlN, and a thickness d21 of the first sub-passivation film satisfies: 2nm≤d21≤5nm; The second sub-passivation film includes SiN, or Al2O3, or SiO2, and the thickness d22 of the second sub-passivation film satisfies: d22=λ / 4n, wherein n is the refractive index of the second sub-passivation film for the light emitted by the micro-LED chip, and λ is the wavelength of the light emitted by the micro-LED chip.

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