Time synchronization device and method

Abstract

The invention discloses a time synchronization device and method, and relates to the technical field of time synchronization, and the method comprises the steps: a satellite navigation module receives a satellite signal, outputs a first second pulse signal and a timestamp signal according to the satellite signal, transmits the timestamp signal to a time service slave device, and transmits the first second pulse signal to a digital phase discriminator; the digital phase discriminator receives a second pulse-per-second signal sent by the digital oscillator, obtains a phase discrimination value according to the first pulse-per-second signal and the second pulse-per-second signal, and inputs the phase discrimination value to the first filter or the second filter for filtering to obtain a filtered signal; the digital oscillator receives the filtering signal and processes the filtering signal to obtain a target second pulse signal; and the time service slave device receives the target pulse per second signal and performs time synchronization according to the target pulse per second signal and the timestamp. A jitter offset device is formed by a digital phase discriminator, a first filter and a digital oscillator and is used for reducing jitter of pulse per second output by a satellite navigation module and improving the accuracy of time synchronization.

Description

Technical Field

[0001] The present application relates to the field of time synchronization technology, and in particular to a time synchronization device and method. Background Art

[0002] After receiving GNSS satellite signals, GNSS (Global Navigation Satellite System) decodes and outputs 1PPS pulse-seconds and TOD timestamp signals to timing slave devices (such as network devices). The timing slave device compares the local timestamp with the TOD timestamp, adjusts the local clock oscillator frequency and time, and synchronizes the local clock frequency and time with the GPS clock frequency and time. Due to the satellite signal passing through the atmosphere and the multipath effect of the wireless signal, the 1PPS pulse-seconds usually has a jitter of tens to more than one hundred nanoseconds, which restricts the precision of time synchronization and leads to low accuracy of time synchronization. Summary of the invention

[0003] The main purpose of the present application is to provide a time synchronization device and method, aiming to solve the technical problem of low accuracy caused by jitter in time synchronization.

[0004] To achieve the above-mentioned purpose, the present application proposes a time synchronization device, which includes: a satellite navigation module, a digital phase detector, a first filter and a digital oscillator connected in sequence, a second filter is further provided between the digital phase detector and the digital oscillator, the bandwidths of the first filter and the second filter are different, and the digital phase detector is further connected to a timing slave device;

[0005] The satellite navigation module is used to receive satellite signals, and output a first second pulse signal and a time stamp signal according to the satellite signals, and send the time stamp signal to the timing slave device, and send the first second pulse signal to the digital phase detector;

[0006] The digital phase detector is used to receive the second pulse signal sent by the digital oscillator, and obtain a phase detection value according to the first pulse signal and the second pulse signal;

[0007] The digital phase detector is further used to input the phase detection value into the first filter or the second filter for filtering to obtain a filtered signal;

[0008] The digital oscillator is used to receive the filtered signal and process the filtered signal to obtain a target pulse per second signal;

[0009] The timing slave device is used to receive the target second pulse signal and perform time synchronization according to the target second pulse signal and the timestamp.

[0010] In one embodiment, the digital phase detector is further used to determine a locking state between the first pulse-per-second signal and the second pulse-per-second signal according to the phase detector value;

[0011] The digital phase detector is further used to send the phase detection value to the first filter or the second filter for filtering according to the locking state to obtain a filtered signal.

[0012] In one embodiment, the first filter comprises: a discreteness determination module, a median digital filter and a first bandwidth filter connected in sequence;

[0013] The digital phase detector is further used to send the phase detection value to the discreteness judgment module when the locking state is the first locking state;

[0014] The discreteness determination module is used to determine the distribution law of the phase-discrimination values, select a target phase-discrimination value array from the phase-discrimination values ​​according to the distribution law, and send the target phase-discrimination value array to the median digital filter;

[0015] The median digital filter is used to perform median filtering on the target phase-discrimination value array to obtain a current phase-discrimination value, and send the current phase-discrimination value to the first bandwidth filter;

[0016] The first bandwidth filter is used to filter the current phase-locked value to obtain a filtered signal.

[0017] In one embodiment, the second filter comprises: a second bandwidth filter, the bandwidth of the second bandwidth filter being greater than the bandwidth of the first bandwidth filter;

[0018] The digital phase detector is further used to send the phase detection value to the second bandwidth filter when the locking state is an unlocked state;

[0019] The second bandwidth filter is used to filter the phase detection value to obtain a filtered signal.

[0020] In one embodiment, the digital phase detector is further used to compare the phase detection value with a first preset threshold and a second preset threshold, and the first preset threshold is smaller than the second preset threshold;

[0021] The digital phase detector is further used to determine that the locking state between the first second pulse signal and the second second pulse signal is a first locking state when the phase detection value is less than or equal to the first preset threshold;

[0022] The digital phase detector is further used to determine that the locking state between the first second pulse signal and the second second pulse signal is a second locking state when the phase detection value is less than or equal to the second preset threshold and greater than the first preset threshold;

[0023] The digital phase detector is further used to determine that the locking state between the first second pulse signal and the second second pulse signal is an unlocked state when the phase detection value is greater than the second preset threshold.

[0024] In one embodiment, the digital oscillator is further used to receive a time reference sent by a local clock;

[0025] The digital oscillator is further used to adjust the oscillation frequency according to the time reference, output a second pulse signal, and send the second second pulse signal to the digital phase detector;

[0026] The digital oscillator is also used to receive the filtered signal, adjust the oscillation frequency according to the filtered signal, obtain a reference second pulse signal, and send the reference second pulse signal as a second second pulse signal to the digital phase detector until the phase detection value between the second second pulse signal and the first second pulse signal is in a first locked state, and output a target second pulse signal.

[0027] In one embodiment, the timing slave device is also used to receive the target second pulse signal and compare the timestamp with the local timestamp of the local clock, and adjust the oscillation frequency and time of the local clock through the target second pulse signal and the timestamp to synchronize the time and clock frequency of the local clock with the clock frequency and time of the satellite navigation module.

[0028] In addition, to achieve the above-mentioned purpose, the present application also proposes a time synchronization method, which is applied to the time synchronization device described above, and the time synchronization device includes: a satellite navigation module, a digital phase detector, a first filter and a digital oscillator connected in sequence, and a second filter is also provided between the digital phase detector and the digital oscillator, and the bandwidths of the first filter and the second filter are different, and the digital phase detector is also connected to a timing slave device; the method includes:

[0029] The satellite navigation module receives satellite signals, and outputs a first second pulse signal and a time stamp signal according to the satellite signals, and sends the time stamp signal to the timing slave device, and sends the first second pulse signal to the digital phase detector;

[0030] The digital phase detector receives the second pulse signal sent by the digital oscillator, and obtains a phase detection value according to the first pulse signal and the second pulse signal;

[0031] The digital phase detector inputs the phase detection value into the first filter or the second filter for filtering to obtain a filtered signal;

[0032] The digital oscillator receives the filtered signal and processes the filtered signal to obtain a target pulse per second signal;

[0033] The timing slave device receives the target second pulse signal and performs time synchronization according to the target second pulse signal and the timestamp.

[0034] In one embodiment, the digital phase detector inputs the phase detection value into the first filter or the second filter for filtering, and the step of obtaining the filtered signal includes:

[0035] The digital phase detector determines the locking state between the first pulse-per-second signal and the second pulse-per-second signal according to the phase detection value;

[0036] The digital phase detector sends the phase detection value to the first filter or the second filter for filtering according to the locking state to obtain a filtered signal.

[0037] In one embodiment, the first filter comprises: a discreteness determination module, a median digital filter and a first bandwidth filter connected in sequence;

[0038] The digital phase detector sends the phase detection value to the first filter or the second filter for filtering according to the locking state, and the step of obtaining the filtered signal includes:

[0039] The digital phase detector sends the phase detection value to the discreteness determination module when the locking state is the first locking state;

[0040] The discreteness determination module determines the distribution law of the phase discrimination values, selects a target phase discrimination value array from the phase discrimination values ​​according to the distribution law, and sends the target phase discrimination value array to the median digital filter;

[0041] The median digital filter performs median filtering on the target phase discrimination value array to obtain a current phase discrimination value, and sends the current phase discrimination value to the first bandwidth filter;

[0042] The first bandwidth filter filters the current phase-discrimination value to obtain a filtered signal.

[0043] One or more technical solutions proposed in the present application, the time synchronization device includes: a satellite navigation module, a digital phase detector, a first filter and a digital oscillator connected in sequence, a second filter is also provided between the digital phase detector and the digital oscillator, the bandwidth of the first filter and the second filter are different, and the digital phase detector is also connected to the timing slave device; the satellite navigation module is used to receive satellite signals, and output a first second pulse signal and a timestamp signal according to the satellite signals, and send the timestamp signal to the timing slave device, and send the first second pulse signal to the digital phase detector; the digital phase detector is used to receive the second second pulse signal sent by the digital oscillator, and obtain a phase detection value according to the first second pulse signal and the second second pulse signal; the digital phase detector is also used to input the phase detection value into the first filter or the second filter for filtering to obtain a filtered signal; the digital oscillator is used to receive the filtered signal and process the filtered signal to obtain a target second pulse signal; the timing slave device is used to receive the target second pulse signal and perform time synchronization according to the target second pulse signal and the timestamp. The jitter compensation device is composed of a digital phase detector, a first filter and a digital oscillator. Through the coupling of multiple modules, the jitter of the 1PPS second pulse can be significantly reduced, the jitter of the second pulse output by the satellite navigation module can be reduced, and the accuracy of time synchronization can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0045] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0046] Figure 1 A schematic diagram of the current time synchronization device;

[0047] Figure 2 This is a schematic diagram of the jitter of the pulse-per-second signal output by the GNSS module;

[0048] Figure 3 This is a schematic diagram of the structure of the first embodiment of the time synchronization device of the present application;

[0049] Figure 4 This is a schematic diagram of the structure of the second embodiment of the time synchronization device of the present application;

[0050] Figure 5This is a flowchart of the first embodiment of the time synchronization method of the present application.

[0051] Description of Figure Numbers:

[0052] Satellite navigation module 10, digital phase detector 20, first filter 30, digital oscillator 40, second filter 50, timing slave device 60, local clock 70;

[0053] A discreteness determination module 301, a median digital filter 302, and a first bandwidth filter 303;

[0054] Second bandwidth filter 501 .

[0055] The purpose, features and advantages of this application will be further described in conjunction with the embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0056] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the present application and are not used to limit the present application.

[0057] In order to better understand the technical solution of the present application, a detailed description will be given below in conjunction with the accompanying drawings and specific implementation methods.

[0058] The main solution of the embodiment of the present application is: the time synchronization device includes: a satellite navigation module, a digital phase detector, a first filter and a digital oscillator connected in sequence, a second filter is also provided between the digital phase detector and the digital oscillator, the bandwidth of the first filter and the second filter are different, and the digital phase detector is also connected to the timing slave device; the satellite navigation module is used to receive satellite signals, and output a first second pulse signal and a timestamp signal according to the satellite signals, and send the timestamp signal to the timing slave device, and send the first second pulse signal to the digital phase detector; the digital phase detector is used to receive the second second pulse signal sent by the digital oscillator, and obtain a phase detection value according to the first second pulse signal and the second second pulse signal; the digital phase detector is also used to input the phase detection value into the first filter or the second filter for filtering to obtain a filtered signal; the digital oscillator is used to receive the filtered signal and process the filtered signal to obtain a target second pulse signal; the timing slave device is used to receive the target second pulse signal and perform time synchronization according to the target second pulse signal and the timestamp.

[0059] like Figure 1 As shown, Figure 1This is a schematic diagram of the current time synchronization device. Due to the existing satellite signals passing through the atmosphere and the multipath effect of wireless signals, the 1PPS second pulse usually has a jitter of tens to more than a hundred nanoseconds, which limits the accuracy of time synchronization.

[0060] This application provides a solution. After analysis, the jitter of the 1PPS second pulse recovered from the GNSS module has a Gaussian distribution characteristic that is symmetrical around the center frequency, such as Figure 2 As shown, Figure 2 The diagram is a jitter diagram of the pulse-per-second signal output by the GNSS module. If this 1PPS pulse-per-second is compared with a signal with very small jitter, a phase-locked signal with the same left-right symmetry will be obtained. The left-right symmetric phase-locked signal is processed by a digital filter so that the left-right symmetric signals cancel each other out, leaving the center signal. The 1PPS pulse-per-second is then restored using this center signal, and the accurate value of the 1PPS pulse-per-second with low jitter can be obtained. The reference clock is provided to the digital oscillator by an oven controlled crystal oscillator (OXCO) or an atomic clock, and the digital oscillator outputs a feedback signal, which can achieve extremely low jitter.

[0061] It should be noted that the execution subject of this embodiment may be a computing service device with data processing, network communication and program running functions, such as a tablet computer, a personal computer, a mobile phone, etc., or an electronic device capable of realizing the above functions, a time synchronization device, etc. The following takes the time synchronization device as an example to illustrate this embodiment and the following embodiments.

[0062] Based on this, the embodiment of the present application provides a time synchronization device, referring to Figure 3 , Figure 3 FIG. 4 is a schematic diagram of the structure of the first embodiment of the time synchronization device.

[0063] In this embodiment, the time synchronization device includes: a satellite navigation module 10, a digital phase detector 20, a first filter 30 and a digital oscillator 40 connected in sequence, and a second filter 50 is also provided between the digital phase detector 20 and the digital oscillator 40. The bandwidths of the first filter 30 and the second filter 50 are different. The digital phase detector 20 is also connected to the timing slave device 60.

[0064] The satellite navigation module 10 is used to receive satellite signals, and output a first second pulse signal and a timestamp signal according to the satellite signals, and send the timestamp signal to the timing slave device 60 , and send the first second pulse signal to the digital phase detector 20 .

[0065] It should be noted that the satellite navigation module 10 is connected to the digital phase detector 20, and the satellite navigation module can be a GPS module, a Beidou module, etc., or other modules that can receive satellite signals, and this embodiment does not limit this. The satellite signal can be a signal sent by a GPS satellite, a signal sent by a Beidou satellite, etc. After the satellite navigation module 10 receives the satellite signal, it will decode the satellite signal and output a 1PPS (one pulse per second) second pulse (i.e., the first second pulse signal) and a TOD (Time of Date) timestamp signal.

[0066] After outputting the first pulse per second signal and the timestamp signal, the satellite navigation module 10 sends the timestamp signal to the timing slave device. Meanwhile, the satellite navigation module 10 also sends the first pulse per second signal to the digital phase detector 20 .

[0067] In this embodiment, the digital phase detector 20 is used to receive the second pulse signal sent by the digital oscillator 40, and obtain a phase detection value according to the first pulse signal and the second pulse signal.

[0068] It can be understood that the digital phase detector 20 can be an XOR gate phase detector, and the digital phase detector 20 is mainly used to compare the phase difference between the first pulse per second signal output by the satellite navigation module 10 and the second pulse per second signal (also called feedback signal) output by the digital oscillator 40. The phase detection value is the phase difference between the first pulse per second signal and the second pulse per second signal, and the phase detection value also indicates the magnitude and direction of the phase difference.

[0069] After obtaining the phase detection value, the digital phase detector 20 can select a specific filter for filtering according to the magnitude of the phase detection value.

[0070] In this embodiment, the digital phase detector 20 is further used to input the phase detection value into the first filter 30 or the second filter 50 for filtering to obtain a filtered signal.

[0071] It should be noted that the bandwidth setting of the first filter 30 is different from the bandwidth setting of the second filter 50. For example, the bandwidth of the first filter 30 is smaller than the bandwidth of the second filter 50. When the phase detection value changes greatly, the digital phase detector 20 selects the second filter 50 to filter the phase detection value to obtain a filtered signal. When the phase detection value changes greatly, the digital phase detector 20 selects the first filter 30 to filter the phase detection value to obtain a filtered signal.

[0072] It is understandable that the magnitude of the phase-detection value change can be determined by setting a threshold value or by other methods, which is not limited in this embodiment. The filtered signal is the filtered phase-detection value.

[0073] In this embodiment, the digital oscillator 40 is used to receive the filtered signal and process the filtered signal to obtain a target pulse per second signal.

[0074] It should be noted that the function of the digital oscillator 40 is to adjust the oscillation frequency according to the phase detection signal and output the required frequency through frequency division. The digital oscillator 40 adopts digital frequency synthesis technology to generate controllable square waves and sine waves.

[0075] In a specific implementation, after receiving the filtered signal, the digital oscillator 40 can adjust the frequency according to the filtered signal, thereby outputting the required frequency, and finally obtaining the target second pulse signal, which is a second pulse signal with smaller jitter.

[0076] In a feasible implementation, the digital oscillator 40 is also used to receive a time reference sent by a local clock 70; the digital oscillator 40 is also used to adjust the oscillation frequency according to the time reference, output a second pulse signal, and send the second second pulse signal to the digital phase detector 20.

[0077] It should be noted that, in the initial synchronization stage, the digital oscillator 40 receives the time reference sent by the local clock 70. The local clock 70 is a highly stable reference clock, which provides a highly stable clock source for the digital oscillator 40. When the phase detection signal is constant, the stability of the digital oscillator output frequency depends on the frequency stability of the reference clock. The highly stable reference clock is an oven controlled crystal oscillator (OXCO) or an atomic clock.

[0078] The digital oscillator 40 adjusts the oscillation frequency according to the time reference sent by the local clock 70, thereby outputting a second pulse signal, i.e., a feedback signal, and sends the feedback signal to the digital phase detector 20. In the subsequent time synchronization stage, if the jitter of the second pulse signal is still large, the digital phase detector 20 will also send the output second pulse signal to the digital phase detector 20.

[0079] In this embodiment, the digital oscillator 40 is also used to receive the filtered signal, and adjust the oscillation frequency according to the filtered signal to obtain a reference second pulse signal, and send the reference second pulse signal as a second second pulse signal to the digital phase detector 20 until the phase detection value between the second second pulse signal and the first second pulse signal is in a first locked state, and the target second pulse signal is output.

[0080] It should be understood that the digital oscillator 40 is also used to receive the filtered signal sent by the first filter 30 or the second filter 50, and adjust the oscillation frequency according to the filtered signal to obtain a reference second pulse signal, and transmit the reference second pulse signal as a new second second pulse signal to the digital phase detector 20, and when the phase detection value between the first second pulse signal and the second second pulse signal is in a first locked state, output the target second pulse signal to the timing slave device.

[0081] The first locking state is a state when the phase detection value is infinitely close to 0. For example, the threshold is set to 0.1. When the phase detection value is less than or equal to 0.1, it is determined that the phase detection value is in the first locking state.

[0082] In this embodiment, the timing slave device 60 is used to receive the target pulse second signal and perform time synchronization according to the target pulse second signal and the timestamp.

[0083] It should be noted that the timing slave device 60 is connected to the digital oscillator 40. The timing slave device 60 generally refers to those devices that can obtain accurate time signals from an external time source and provide them to other devices or systems to achieve time synchronization. The timing slave device 60 can be a network device or other devices, which is not limited in this embodiment. The timing master device can be a satellite, and the timing slave device 60 can receive the target second pulse signal sent by the digital oscillator 40, and perform time synchronization according to the target second pulse signal and the timestamp sent by the satellite navigation module 10, specifically, perform time synchronization on the local clock according to the target second pulse signal and the timestamp.

[0084] In a feasible implementation, the timing slave device 60 is also used to receive the target second pulse signal and compare the timestamp with the local timestamp of the local clock, and adjust the oscillation frequency and time of the local clock through the target second pulse signal and the timestamp to synchronize the time and clock frequency of the local clock with the clock frequency and time of the satellite navigation module 10.

[0085] It should be understood that after receiving the target second pulse signal, the timing slave device 60 can compare the timestamp with the local timestamp of the local clock to obtain the time difference, and adjust the oscillator frequency and time of the local clock through the target second pulse signal and the corresponding time difference, so that the local clock frequency and time are synchronized with the clock frequency and time of the satellite navigation module 10.

[0086] In this embodiment, the time synchronization device includes a satellite navigation module 10, a digital phase detector 20, a first filter 30 and a digital oscillator 40 connected in sequence, a second filter 50 is further provided between the digital phase detector 20 and the digital oscillator 40, the first filter 30 and the second filter 50 have different bandwidths, and the digital phase detector 20 is further connected to a timing slave device 60; the satellite navigation module 10 is used to receive a satellite signal, and output a first second pulse signal and a timestamp signal according to the satellite signal, and send the timestamp signal to the timing slave device 60, and send the first second pulse signal to the digital oscillator 40. Phase detector 20; the digital phase detector 20 is used to receive the second second pulse signal sent by the digital oscillator 40, and obtain the phase detection value according to the first second pulse signal and the second second pulse signal; the digital phase detector 20 is also used to input the phase detection value into the first filter 30 or the second filter 50 for filtering to obtain a filtered signal; the digital oscillator 40 is used to receive the filtered signal and process the filtered signal to obtain a target second pulse signal; the timing slave device 60 is used to receive the target second pulse signal and perform time synchronization according to the target second pulse signal and the timestamp. The jitter compensation device is formed by the digital phase detector 20, the first filter 30 and the digital oscillator 40. Through the coupling of multiple modules, the jitter of the 1PPS second pulse can be significantly reduced, the jitter of the second pulse output by the satellite navigation module 10 can be reduced, and the accuracy of time synchronization can be improved.

[0087] Based on the first embodiment of the time synchronization device of the present application, in the second embodiment of the time synchronization device of the present application, the same or similar contents as those in the first embodiment of the time synchronization device mentioned above can be referred to the above introduction, and will not be repeated later. On this basis, the second embodiment of the time synchronization device of the present application is proposed.

[0088] In this embodiment, the digital phase detector 20 is further used to determine the locking state between the first pulse-per-second signal and the second pulse-per-second signal according to the phase detection value.

[0089] It should be noted that the digital phase detector 20 is used to determine the locking state between the first pulse per second signal and the second pulse per second signal according to the magnitude of the phase detector value, and the locking state may include a first locking state, a second locking state and an unlocked state.

[0090] In a specific implementation, when the magnitude of the phase detection value is different, the corresponding locking state is different.

[0091] In this embodiment, the digital phase detector 20 is further used to send the phase detection value to the first filter 30 or the second filter 50 for filtering according to the locking state to obtain a filtered signal.

[0092] It can be understood that the digital phase detector 20 can determine the use of corresponding filters to filter the phase detection value according to different locking states. For example, when the locking state is the first locking state, the digital phase detector 20 can send the phase detection value to the first filter 30 for filtering. When the locking state is the second locking state, the phase detection value does not need to be filtered again. When the locking state is the unlocked state, the digital phase detector 20 can send the phase detection value to the second filter 50 for filtering.

[0093] like Figure 4 As shown, Figure 4 2 is another structural diagram of the time synchronization device. The first filter 30 includes: a discreteness determination module 301, a median digital filter 302 and a first bandwidth filter 303 which are connected in sequence.

[0094] The digital phase detector 20 is further configured to send the phase detector value to the discreteness determination module 301 when the locking state is the second locking state.

[0095] It should be noted that the second locking state represents that the phase detection value gradually decreases from a large jump, but there is still a certain jump. At this time, the phase detection value needs to be filtered more finely. Therefore, after determining that the locking state of the phase detection value is the second locking state, the digital phase detector 20 sends the phase detection value to the discreteness judgment module 301.

[0096] In this embodiment, the discreteness determination module 301 is used to determine the distribution law of the phase detection values, select a target phase detection value array from the phase detection values ​​according to the distribution law, and send the target phase detection value array to the median digital filter 302.

[0097] It should be noted that the discreteness determination module 301 is mainly used to analyze the distribution law of the phase detection value, so as to select a sufficiently large phase detection value array size, that is, a target phase detection value array, which conforms to the left-right symmetrical Gaussian distribution law.

[0098] After the discreteness determination module 301 determines the target phase detection value array, the target phase detection value array may be sent to the median digital filter 302 for filtering.

[0099] In this embodiment, the median digital filter 302 is used to perform median filtering on the target phase-discrimination value array to obtain a current phase-discrimination value, and send the current phase-discrimination value to the first bandwidth filter 303;

[0100] The first bandwidth filter 303 is used to filter the current phase detection value to obtain a filtered signal.

[0101] It should be noted that the target phase-detection value array is subjected to median filtering by the median digital filter 302, the median in the target phase-detection value array is selected as the current phase-detection value, and the current phase-detection value is sent to the first bandwidth filter 303. The first bandwidth filter adopts a Hertz-level bandwidth filter, which is a digital or analog filter with a very narrow bandwidth, and can smooth the current phase-detection value signal in a very low frequency range, smooth the sudden change of the phase-detection value, thereby reducing high-frequency noise and rapid changes, while maintaining the long-term stability of the signal, and obtain a filtered signal, and send the filtered signal to the digital oscillator 40. At this time, the digital oscillator 40 processes the filtered signal to obtain a second pulse signal, and the phase-detection value between the second pulse signal and the first second pulse signal may be in the second locked state or in the first locked state. If the phase-detection value is in the second locked state, the obtained second pulse signal is sent to the digital phase detector 20 as the second second pulse signal, until the second pulse signal and the phase-detection value corresponding to the first second pulse signal are in the first locked state, and the target second pulse signal is obtained.

[0102] The first bandwidth filter may be a 1 MHz bandwidth digital filter, a 5 MHz bandwidth digital filter, etc. This embodiment does not impose any limitation on this and may be flexibly selected according to requirements.

[0103] For example, if the target phase-detection value array is an array of 15 values, the median digital filter 302 performs median filtering on the array of 15 values ​​composed of the current phase-detection value, the first 7 phase-detection values ​​and the last 7 phase-detection values, and replaces the current phase-detection value with the median. Then, the current phase-detection value is sent to the first bandwidth filter 303. The first bandwidth filter 303 uses an extremely low bandwidth to filter the phase-detection value, smoothes the sudden change of the phase-detection value, and sends the processed phase-detection value to the digital oscillator 40.

[0104] In this embodiment, the second filter 50 includes: a second bandwidth filter 501 , and the bandwidth of the second bandwidth filter 501 is greater than the bandwidth of the first bandwidth filter 303 .

[0105] It should be noted that the second filter 50 includes a second bandwidth filter 501 , and the second bandwidth filter 501 is a wide bandwidth filter, for example, the bandwidth is 100 KHz, 500 KHz, etc., which is not limited in this embodiment.

[0106] In this embodiment, the digital phase detector 20 is further used to send the phase detection value to the second bandwidth filter 501 when the locking state is an unlocked state;

[0107] The second bandwidth filter 501 is used to filter the phase detection value to obtain a filtered signal.

[0108] It should be noted that when the digital phase detector 20 determines that the locked state of the phase detection value is an unlocked state, it means that the phase detection value fluctuates greatly. At this time, the digital phase detector 20 selects a wide bandwidth filter to filter the phase detection value, and the digital phase detector 20 sends the phase detection value to the second bandwidth filter 501. Thus, the phase detection value is filtered by the second bandwidth filter 501 to obtain a filtered signal, which is sent to the digital oscillator 40.

[0109] In this embodiment, the digital phase detector 20 is further used to compare the phase detection value with a first preset threshold and a second preset threshold, and the first preset threshold is smaller than the second preset threshold;

[0110] It should be noted that the first preset threshold can be set to a smaller value, such as 0.1, 0.05, etc., and the second preset threshold can be set to 50, 30, etc. This embodiment does not limit this. The locking state of the phase-locked value can be determined by comparing the phase-locked value with the first preset threshold and the second preset threshold respectively.

[0111] In this embodiment, the digital phase detector 20 is further used to determine that the locking state between the first pulse-per-second signal and the second pulse-per-second signal is the first locking state when the phase detection value is less than or equal to the first preset threshold.

[0112] It can be understood that the first locking state is a state in which the phase-locking value jumps very little or the phase-locking value is infinitely close to 0. At this time, the phase-locking value has extremely low jitter. When the phase-locking value is less than the first preset threshold, the locking state between the first second pulse signal and the second second pulse signal is the first locking state. At this time, the second second pulse signal can be directly output as the target second pulse signal to the timing slave device 60 for time synchronization.

[0113] In this embodiment, the digital phase detector 20 is further used to determine that the locking state between the first second pulse signal and the second second pulse signal is a second locking state when the phase detection value is less than or equal to the second preset threshold and greater than the first preset threshold.

[0114] It can be understood that the second locking state is a state in which the jitter of the phase-lock value gradually decreases. When the phase-lock value gradually becomes less than or equal to the second preset threshold but greater than the first preset threshold, the locking state is determined to be the second locking state. At this time, the first filter 30 can be selected to perform fine filtering on the phase-lock value to gradually reduce the jitter of the phase-lock value.

[0115] In this embodiment, the digital phase detector 20 is further used to determine that the locking state between the first pulse-per-second signal and the second pulse-per-second signal is an unlocked state when the phase detection value is greater than the second preset threshold.

[0116] It should be understood that the unlocked state is a state in which the phase detection value changes greatly. The phase detection value is the phase difference between the first second pulse signal and the second second pulse signal. The phase difference is digitally quantized, and the output phase detection value is a numerical value of 128-255, which means that the phase detection value changes greatly. For example, 127 is taken as the second preset threshold. When the phase detection value is any one within the range of 128-255, it is determined that the locked state between the first second pulse signal and the second second pulse signal is an unlocked state. 3 is taken as the first preset value. If the phase detection value output is any one of 4-127, the locked state between the first second pulse signal and the second second pulse signal is the second locked state. If the phase detection value output is less than or equal to 3, the locked state between the first second pulse signal and the second second pulse signal is the first locked state.

[0117] The digital phase detector 20 in this embodiment is further used to determine the locking state between the first second pulse signal and the second second pulse signal according to the phase detection value; the digital phase detector 20 is further used to send the phase detection value to the first filter 30 or the second filter 50 for filtering according to the locking state to obtain a filtered signal. By using the digital phase detector 20 and the corresponding filter in combination, the jitter and error in the time synchronization system can be effectively reduced, and the accuracy and stability of time synchronization can be improved.

[0118] This application also provides a time synchronization method, please refer to Figure 5 , Figure 5 This is a flowchart of the first embodiment of the time synchronization method of the present application.

[0119] In this embodiment, the time synchronization method is applied to the time synchronization device described above, and the time synchronization device includes: a satellite navigation module, a digital phase detector, a first filter and a digital oscillator connected in sequence, and a second filter is also provided between the digital phase detector and the digital oscillator. The bandwidths of the first filter and the second filter are different, and the digital phase detector is also connected to the timing slave device.

[0120] The method comprises steps S10 to S50:

[0121] Step S10: The satellite navigation module receives the satellite signal, and outputs a first second pulse signal and a timestamp signal according to the satellite signal, and sends the timestamp signal to the timing slave device, and sends the first second pulse signal to the digital phase detector.

[0122] It should be noted that the satellite navigation module is connected to the digital phase detector, and the satellite navigation module can be a GPS module, a Beidou module, etc., or other modules that can receive satellite signals, and this embodiment does not limit this. The satellite signal can be a signal sent by a GPS satellite, a signal sent by a Beidou satellite, etc. After the satellite navigation module receives the satellite signal, it will decode the satellite signal and output a 1PPS (one pulse per second) second pulse (i.e., the first second pulse signal) and a TOD (Time of Date) timestamp signal.

[0123] After outputting the first second pulse signal and the timestamp signal, the satellite navigation module sends the timestamp signal to the timing slave device. At the same time, the satellite navigation module also sends the first second pulse signal to the digital phase detector.

[0124] Step S20: the digital phase detector receives the second pulse signal sent by the digital oscillator, and obtains a phase detection value according to the first pulse signal and the second pulse signal.

[0125] It can be understood that the digital phase detector can be an XOR gate phase detector, which is mainly used to compare the phase difference between the first pulse per second signal output by the satellite navigation module and the second pulse per second signal (also called feedback signal) output by the digital oscillator. The phase detector value is the phase difference between the first pulse per second signal and the second pulse per second signal, and the phase detector value also indicates the magnitude and direction of the phase difference.

[0126] After obtaining the phase detection value, the digital phase detector can select a specific filter for filtering according to the size of the phase detection value.

[0127] Step S30: the digital phase detector inputs the phase detection value into the first filter or the second filter for filtering to obtain a filtered signal.

[0128] It should be noted that the bandwidth setting of the first filter is different from the bandwidth setting of the second filter. For example, the bandwidth of the first filter is smaller than the bandwidth of the second filter. When the phase-detection value changes greatly, the digital phase detector selects the second filter to filter the phase-detection value to obtain a filtered signal. When the phase-detection value changes greatly, the digital phase detector selects the first filter to filter the phase-detection value to obtain a filtered signal.

[0129] It is understandable that the magnitude of the phase-detection value change can be determined by setting a threshold value or by other methods, which is not limited in this embodiment. The filtered signal is the filtered phase-detection value.

[0130] In a feasible implementation, step 30 may include steps A11 to A12:

[0131] Step A11: the digital phase detector determines the locking state between the first pulse-per-second signal and the second pulse-per-second signal according to the phase detection value.

[0132] It should be noted that the digital phase detector is used to determine the locking state between the first pulse per second signal and the second pulse per second signal according to the magnitude of the phase detector value, and the locking state may include a first locking state, a second locking state and an unlocked state.

[0133] In a specific implementation, when the magnitude of the phase detection value is different, the corresponding locking state is different.

[0134] Step A12: The digital phase detector sends the phase detection value to the first filter or the second filter for filtering according to the locking state to obtain a filtered signal.

[0135] It can be understood that the digital phase detector can determine the use of corresponding filters to filter the phase detection value according to different locking states. For example, when the locking state is the first locking state, the digital phase detector can send the phase detection value to the first filter for filtering. When the locking state is the second locking state, the phase detection value does not need to be filtered again. When the locking state is the unlocked state, the digital phase detector can send the phase detection value to the second filter for filtering.

[0136] In a specific implementation, the first filter includes: a discreteness judgment module, a median digital filter and a first bandwidth filter connected in sequence; the step A12 includes: when the locking state is the first locking state, the digital phase detector sends the phase detection value to the discreteness judgment module; the discreteness judgment module judges the distribution law of the phase detection value, selects a target phase detection value array from the phase detection value according to the distribution law, and sends the target phase detection value array to the median digital filter; the median digital filter performs median filtering on the target phase detection value array to obtain a current phase detection value, and sends the current phase detection value to the first bandwidth filter; the first bandwidth filter filters the current phase detection value to obtain a filtered signal.

[0137] It should be noted that the second locking state represents that the phase detection value gradually decreases from a large jump, but there is still a certain jump. At this time, the phase detection value needs to be filtered more finely. Therefore, after the digital phase detector determines that the locking state of the phase detection value is the second locking state, the phase detection value is sent to the discreteness judgment module.

[0138] It should be noted that the discreteness judgment module is mainly used to analyze the distribution law of the phase detection value, so as to select a sufficiently large phase detection value array size, that is, a target phase detection value array, which conforms to the left-right symmetrical Gaussian distribution law.

[0139] After the discreteness judgment module determines the target phase discrimination value array, the target phase discrimination value array can be sent to the median digital filter for filtering.

[0140] It should be noted that the target phase-discrimination value array is subjected to median filtering by a median digital filter, the median in the target phase-discrimination value array is selected as the current phase-discrimination value, and the current phase-discrimination value is sent to the first bandwidth filter. The first bandwidth filter adopts a Hertz-level bandwidth filter, which is a digital or analog filter with a very narrow bandwidth, and can smooth the current phase-discrimination value signal in a very low frequency range, smooth the mutation of the phase-discrimination value, thereby reducing high-frequency noise and rapid changes, while maintaining the long-term stability of the signal, and obtain a filtered signal, and send the filtered signal to the digital oscillator. At this time, the digital oscillator processes the filtered signal to obtain a second pulse signal, and the phase-discrimination value between the second pulse signal and the first second pulse signal may be in the second locked state or in the first locked state. If the phase-discrimination value is in the second locked state, the obtained second pulse signal is sent to the digital phase detector as the second second pulse signal until the second pulse signal and the phase-discrimination value corresponding to the first second pulse signal are in the first locked state, and the target second pulse signal is obtained.

[0141] The first bandwidth filter may be a 1 MHz bandwidth digital filter, a 5 MHz bandwidth digital filter, etc. This embodiment does not impose any limitation on this and may be flexibly selected according to requirements.

[0142] For example, if the target phase-detection value array is an array of 15 values, the median digital filter performs median filtering on the array of 15 values ​​consisting of the current phase-detection value together with the first 7 phase-detection values ​​and the last 7 phase-detection values, and replaces the current phase-detection value with the median. Then, the current phase-detection value is sent to the first bandwidth filter, and the first bandwidth filter uses an extremely low bandwidth to filter the phase-detection value, smoothes the mutation of the phase-detection value, and sends the processed phase-detection value to the digital oscillator.

[0143] Step S40: The digital oscillator receives the filtered signal and processes the filtered signal to obtain a target pulse per second signal.

[0144] It should be noted that the function of the digital oscillator is to adjust the oscillation frequency according to the phase detection signal and output the required frequency after frequency division. The digital oscillator uses digital frequency synthesis technology to generate controllable square waves and sine waves.

[0145] In a specific implementation, after receiving the filtered signal, the digital oscillator can adjust the frequency according to the filtered signal, thereby outputting the required frequency, and finally obtaining the target second pulse signal, which is a second pulse signal with smaller jitter.

[0146] Step S50: the timing slave device receives the target pulse second signal, and performs time synchronization according to the target pulse second signal and the timestamp.

[0147] It should be noted that the timing slave device is connected to the digital oscillator. The timing slave device can receive the target second pulse signal sent by the digital oscillator, and perform time synchronization according to the target second pulse signal and the timestamp sent by the satellite navigation module, specifically, synchronize the local clock according to the target second pulse signal and the timestamp.

[0148] This embodiment provides a time synchronization method, wherein the satellite navigation module receives a satellite signal, and outputs a first second pulse signal and a timestamp signal according to the satellite signal, and sends the timestamp signal to a timing slave device, and sends the first second pulse signal to a digital phase detector; the digital phase detector receives a second second pulse signal sent by a digital oscillator, and obtains a phase detection value according to the first second pulse signal and the second second pulse signal; the digital phase detector inputs the phase detection value into a first filter or a second filter for filtering to obtain a filtered signal; the digital oscillator receives the filtered signal, and processes the filtered signal to obtain a target second pulse signal; the timing slave device receives the target second pulse signal, and performs time synchronization according to the target second pulse signal and the timestamp. A jitter compensation device is formed by a digital phase detector, a first filter, and a digital oscillator. Through the coupling of multiple modules, the jitter of the 1PPS second pulse can be significantly reduced, the jitter of the second pulse output by the satellite navigation module can be reduced, and the accuracy of time synchronization can be improved.

[0149] This embodiment provides a time synchronization method, which is as follows: (1) The GPS module receives the satellite signal, and after decoding, outputs the first second pulse signal and the timestamp signal. The first second pulse is sent to the XOR gate phase detector, and the timestamp is sent to the timing slave device. (2) The XOR gate phase detector compares the phase difference between the first second pulse signal of the GPS module and the feedback signal (the second second pulse signal), and then digitally quantizes the phase difference. The output value of 128-255 indicates that the phase of the 1PPS second pulse leads the feedback signal. The larger the value, the more it leads; the output value of 0-127 indicates that the phase of the 1PPS second pulse lags behind the feedback signal. The larger the value, the more it lags. This value is the phase detection value. (3) Since the first second pulse signal and the feedback signal of the GPS module have not been locked, the phase detection value jumps greatly at this time. The XOR gate phase detector selects the 100KHz bandwidth digital filter and sends the phase detection value to the 100KHz bandwidth digital filter. The 100KHz bandwidth digital filter filters the phase detection value and sends it to the digital control oscillator. (4) The digitally controlled oscillator is provided with a high-stability reference clock by OXCO, and the oscillation frequency is adjusted according to the phase-locked value. After the oscillation frequency is divided, two second pulse signals are output, one of which is sent to the timing slave device, and the other is sent to the XOR gate phase detector as a feedback signal. (5) Repeat steps (2)-(4) until the feedback signal and the first second pulse signal of the GPS module are in the second locked state. After being in the second locked state, the XOR gate phase detector selects the discreteness judgment module and sends the phase-locked value to the discreteness judgment module. (6) The discreteness judgment module analyzes the distribution law of the phase-locked value and selects a sufficiently large phase-locked value array size so that the array conforms to the left-right symmetrical Gaussian distribution law. Assume that in this embodiment, the selected phase-locked value array size is 15. (7) The median digital filter performs median filtering on the array of 15 values ​​composed of the current phase-locked value, the first 7 phase-locked values ​​and the last 7 phase-locked values, and replaces the current value with the median. Then, the current value is sent to the 1mHz bandwidth digital filter. (8) The 1mHz bandwidth digital filter uses an extremely low bandwidth to filter the phase-locked value and smooth out the sudden changes in the phase-locked value. The processed phase-locked value is sent to the digitally controlled oscillator. (9) Repeat steps (6)-(8). At this time, the target second pulse signal output by the digitally controlled oscillator and the first second pulse signal of the GPS module are in a locked state, and the target second pulse signal output by the digitally controlled oscillator has a smaller jitter. (10) The timing slave device receives the target second pulse signal output by the digitally controlled oscillator and the TOD timestamp output by the GPS module, compares the local timestamp with the TOD timestamp, and adjusts the local clock oscillator frequency and time to synchronize the local clock frequency and time with the GPS clock frequency and time.

[0150] It should be noted that the above examples are only used to understand the present application and do not constitute a limitation on the time synchronization method of the present application. More simple transformations based on this technical concept are all within the scope of protection of the present application.

[0151] The above descriptions are only some embodiments of the present application, and are not intended to limit the patent scope of the present application. All equivalent structural changes made using the contents of the present application specification and drawings under the technical concept of the present application, or direct / indirect applications in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A time synchronization device, characterized in that: The time synchronization device comprises: a satellite navigation module, a digital phase detector, a first filter and a digital oscillator connected in sequence, a second filter is further provided between the digital phase detector and the digital oscillator, the first filter and the second filter have different bandwidths, and the digital phase detector is further connected to a timing slave device; The satellite navigation module is used to receive satellite signals, and output a first second pulse signal and a time stamp signal according to the satellite signals, and send the time stamp signal to the timing slave device, and send the first second pulse signal to the digital phase detector; The digital phase detector is used to receive the second pulse signal sent by the digital oscillator, and obtain a phase detection value according to the first pulse signal and the second pulse signal; The digital phase detector is further used to input the phase detection value into the first filter or the second filter for filtering to obtain a filtered signal; The digital oscillator is used to receive the filtered signal and process the filtered signal to obtain a target pulse per second signal; The timing slave device is used to receive the target second pulse signal and perform time synchronization according to the target second pulse signal and the timestamp.

2. The device according to claim 1, characterized in that The digital phase detector is further used to determine the locking state between the first pulse-per-second signal and the second pulse-per-second signal according to the phase detection value; The digital phase detector is further used to send the phase detection value to the first filter or the second filter for filtering according to the locking state to obtain a filtered signal.

3. The device according to claim 2, characterized in that The first filter comprises: a discreteness determination module, a median digital filter and a first bandwidth filter connected in sequence; The digital phase detector is further used to send the phase detection value to the discreteness determination module when the locking state is the second locking state; The discreteness determination module is used to determine the distribution law of the phase-discrimination values, select a target phase-discrimination value array from the phase-discrimination values ​​according to the distribution law, and send the target phase-discrimination value array to the median digital filter; The median digital filter is used to perform median filtering on the target phase-discrimination value array to obtain a current phase-discrimination value, and send the current phase-discrimination value to the first bandwidth filter; The first bandwidth filter is used to filter the current phase-locked value to obtain a filtered signal.

4. The device according to claim 2, characterized in that The second filter comprises: a second bandwidth filter, the bandwidth of the second bandwidth filter being greater than the bandwidth of the first bandwidth filter; The digital phase detector is further used to send the phase detection value to the second bandwidth filter when the locking state is an unlocked state; The second bandwidth filter is used to filter the phase detection value to obtain a filtered signal.

5. The device according to claim 2, characterized in that The digital phase detector is further used to compare the phase detection value with a first preset threshold and a second preset threshold, wherein the first preset threshold is smaller than the second preset threshold; The digital phase detector is further used to determine that the locking state between the first second pulse signal and the second second pulse signal is a first locking state when the phase detection value is less than or equal to the first preset threshold; The digital phase detector is further used to determine that the locking state between the first second pulse signal and the second second pulse signal is a second locking state when the phase detection value is less than or equal to the second preset threshold and greater than the first preset threshold; The digital phase detector is further used to determine that the locking state between the first second pulse signal and the second second pulse signal is an unlocked state when the phase detection value is greater than the second preset threshold.

6. The device according to claim 1, characterized in that The digital oscillator is also used to receive a time reference sent by a local clock; The digital oscillator is further used to adjust the oscillation frequency according to the time reference, output a second pulse signal, and send the second second pulse signal to the digital phase detector; The digital oscillator is also used to receive the filtered signal, adjust the oscillation frequency according to the filtered signal, obtain a reference second pulse signal, and send the reference second pulse signal as a second second pulse signal to the digital phase detector until the phase detection value between the second second pulse signal and the first second pulse signal is in a first locked state, and output a target second pulse signal.

7. The device according to any one of claims 1 to 6, characterized in that The timing slave device is also used to receive the target second pulse signal and compare the timestamp with the local timestamp of the local clock, and adjust the oscillation frequency and time of the local clock through the target second pulse signal and the timestamp to synchronize the time and clock frequency of the local clock with the clock frequency and time of the satellite navigation module.

8. A time synchronization method, characterized in that: The time synchronization method is applied to the time synchronization device described in any one of claims 1 to 7, the time synchronization device comprising: a satellite navigation module, a digital phase detector, a first filter and a digital oscillator connected in sequence, a second filter is further provided between the digital phase detector and the digital oscillator, the first filter and the second filter have different bandwidths, and the digital phase detector is further connected to a timing slave device; the method comprises: The satellite navigation module receives satellite signals, and outputs a first second pulse signal and a time stamp signal according to the satellite signals, and sends the time stamp signal to the timing slave device, and sends the first second pulse signal to the digital phase detector; The digital phase detector receives the second pulse signal sent by the digital oscillator, and obtains a phase detection value according to the first pulse signal and the second pulse signal; The digital phase detector inputs the phase detection value into the first filter or the second filter for filtering to obtain a filtered signal; The digital oscillator receives the filtered signal and processes the filtered signal to obtain a target pulse per second signal; The timing slave device receives the target second pulse signal and performs time synchronization according to the target second pulse signal and the timestamp.

9. The method according to claim 8, characterized in that The digital phase detector inputs the phase detection value into the first filter or the second filter for filtering, and the step of obtaining the filtered signal includes: The digital phase detector determines the locking state between the first pulse-per-second signal and the second pulse-per-second signal according to the phase detection value; The digital phase detector sends the phase detection value to the first filter or the second filter for filtering according to the locking state to obtain a filtered signal.

10. The method according to claim 9, characterized in that The first filter comprises: a discreteness determination module, a median digital filter and a first bandwidth filter connected in sequence; The digital phase detector sends the phase detection value to the first filter or the second filter for filtering according to the locking state, and the step of obtaining the filtered signal includes: The digital phase detector sends the phase detection value to the discreteness determination module when the locking state is the first locking state; The discreteness determination module determines the distribution law of the phase discrimination values, selects a target phase discrimination value array from the phase discrimination values ​​according to the distribution law, and sends the target phase discrimination value array to the median digital filter; The median digital filter performs median filtering on the target phase discrimination value array to obtain a current phase discrimination value, and sends the current phase discrimination value to the first bandwidth filter; The first bandwidth filter filters the current phase-discrimination value to obtain a filtered signal.

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